necpb.c revision 1.39.2.1
1 /* $NetBSD: necpb.c,v 1.39.2.1 2014/05/18 17:44:56 rmind Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: necpb.c,v 1.39.2.1 2014/05/18 17:44:56 rmind Exp $"); 65 66 #include "opt_pci.h" 67 68 #include <sys/types.h> 69 #include <sys/param.h> 70 #include <sys/time.h> 71 #include <sys/systm.h> 72 #include <sys/errno.h> 73 #include <sys/device.h> 74 #include <sys/malloc.h> 75 #include <sys/extent.h> 76 77 #include <uvm/uvm_extern.h> 78 79 #define _ARC_BUS_DMA_PRIVATE 80 #include <sys/bus.h> 81 82 #include <machine/pio.h> 83 84 #include <machine/autoconf.h> 85 #include <machine/cpu.h> 86 #include <machine/platform.h> 87 88 #include <mips/cache.h> 89 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcidevs.h> 93 #ifdef PCI_NETBSD_CONFIGURE 94 #include <dev/pci/pciconf.h> 95 #endif 96 97 #include <arc/jazz/rd94.h> 98 #include <arc/pci/necpbvar.h> 99 100 #include "ioconf.h" 101 102 static int necpbmatch(device_t, cfdata_t, void *); 103 static void necpbattach(device_t, device_t, void *); 104 105 static void necpb_attach_hook(device_t, device_t, 106 struct pcibus_attach_args *); 107 static int necpb_bus_maxdevs(pci_chipset_tag_t, int); 108 static pcitag_t necpb_make_tag(pci_chipset_tag_t, int, int, int); 109 static void necpb_decompose_tag(pci_chipset_tag_t, pcitag_t, int *, 110 int *, int *); 111 static pcireg_t necpb_conf_read(pci_chipset_tag_t, pcitag_t, int); 112 static void necpb_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 113 static int necpb_intr_map(const struct pci_attach_args *, 114 pci_intr_handle_t *); 115 static const char *necpb_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 116 char *, size_t); 117 static void *necpb_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 118 int, int (*func)(void *), void *); 119 static void necpb_intr_disestablish(pci_chipset_tag_t, void *); 120 #ifdef PCI_NETBSD_CONFIGURE 121 static void necpb_conf_interrupt(pci_chipset_tag_t, int, int, int, int, 122 int *); 123 static int necpb_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t); 124 #endif 125 126 static uint32_t necpb_intr(uint32_t, struct clockframe *); 127 128 129 CFATTACH_DECL_NEW(necpb, sizeof(struct necpb_softc), 130 necpbmatch, necpbattach, NULL, NULL); 131 132 static struct necpb_intrhand *necpb_inttbl[4]; 133 134 /* There can be only one. */ 135 int necpbfound; 136 struct necpb_context necpb_main_context; 137 static long necpb_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 138 static long necpb_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 139 140 static int 141 necpbmatch(device_t parent, cfdata_t cf, void *aux) 142 { 143 struct confargs *ca = aux; 144 145 if (strcmp(ca->ca_name, necpb_cd.cd_name) != 0) 146 return 0; 147 148 if (necpbfound) 149 return 0; 150 151 return 1; 152 } 153 154 /* 155 * Set up the chipset's function pointers. 156 */ 157 void 158 necpb_init(struct necpb_context *ncp) 159 { 160 pci_chipset_tag_t pc; 161 #ifndef PCI_NETBSD_CONFIGURE 162 pcitag_t tag; 163 pcireg_t id, class, csr; 164 u_int dev; 165 #endif 166 167 if (ncp->nc_initialized) 168 return; 169 170 arc_large_bus_space_init(&ncp->nc_memt, "necpcimem", 171 RD94_P_PCI_MEM, 0, RD94_S_PCI_MEM); 172 arc_bus_space_init_extent(&ncp->nc_memt, (void *)necpb_mem_ex_storage, 173 sizeof(necpb_mem_ex_storage)); 174 175 arc_bus_space_init(&ncp->nc_iot, "necpciio", 176 RD94_P_PCI_IO, RD94_V_PCI_IO, 0, RD94_S_PCI_IO); 177 arc_bus_space_init_extent(&ncp->nc_iot, (void *)necpb_io_ex_storage, 178 sizeof(necpb_io_ex_storage)); 179 180 jazz_bus_dma_tag_init(&ncp->nc_dmat); 181 182 pc = &ncp->nc_pc; 183 pc->pc_attach_hook = necpb_attach_hook; 184 pc->pc_bus_maxdevs = necpb_bus_maxdevs; 185 pc->pc_make_tag = necpb_make_tag; 186 pc->pc_decompose_tag = necpb_decompose_tag; 187 pc->pc_conf_read = necpb_conf_read; 188 pc->pc_conf_write = necpb_conf_write; 189 pc->pc_intr_map = necpb_intr_map; 190 pc->pc_intr_string = necpb_intr_string; 191 pc->pc_intr_establish = necpb_intr_establish; 192 pc->pc_intr_disestablish = necpb_intr_disestablish; 193 #ifdef PCI_NETBSD_CONFIGURE 194 pc->pc_conf_interrupt = necpb_conf_interrupt; 195 pc->pc_conf_hook = necpb_conf_hook; 196 #endif 197 198 #ifndef PCI_NETBSD_CONFIGURE 199 /* 200 * XXX: 201 * NEC's firmware does not configure PCI devices completely. 202 * We need to disable expansion ROM and enable mem/io/busmaster 203 * bits here. 204 */ 205 for (dev = 3; dev <= 5; dev++) { 206 tag = necpb_make_tag(pc, 0, dev, 0); 207 id = necpb_conf_read(pc, tag, PCI_ID_REG); 208 209 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 210 continue; 211 212 class = necpb_conf_read(pc, tag, PCI_CLASS_REG); 213 csr = necpb_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 214 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 215 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 216 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 217 necpb_conf_write(pc, tag, PCI_MAPREG_ROM, 0); 218 } 219 csr |= PCI_COMMAND_MASTER_ENABLE; 220 necpb_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 221 } 222 #endif 223 224 ncp->nc_initialized = 1; 225 } 226 227 static void 228 necpbattach(device_t parent, device_t self, void *aux) 229 { 230 struct necpb_softc *sc = device_private(self); 231 struct pcibus_attach_args pba; 232 pci_chipset_tag_t pc; 233 int i; 234 235 sc->sc_dev = self; 236 237 necpbfound = 1; 238 239 aprint_normal("\n"); 240 241 sc->sc_ncp = &necpb_main_context; 242 necpb_init(sc->sc_ncp); 243 244 pc = &sc->sc_ncp->nc_pc; 245 #ifdef PCI_NETBSD_CONFIGURE 246 pc->pc_ioext = extent_create("necpbio", 0x00100000, 0x01ffffff, 247 NULL, 0, EX_NOWAIT); 248 pc->pc_memext = extent_create("necpbmem", 0x08000000, 0x3fffffff, 249 NULL, 0, EX_NOWAIT); 250 pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0, 251 mips_cache_info.mci_dcache_align); 252 #endif 253 254 out32(RD94_SYS_PCI_INTMASK, 0xf); 255 256 for (i = 0; i < 4; i++) 257 necpb_inttbl[i] = NULL; 258 259 (*platform->set_intr)(MIPS_INT_MASK_2, necpb_intr, ARC_INTPRI_PCIISA); 260 261 pba.pba_iot = &sc->sc_ncp->nc_iot; 262 pba.pba_memt = &sc->sc_ncp->nc_memt; 263 pba.pba_dmat = &sc->sc_ncp->nc_dmat; 264 pba.pba_dmat64 = NULL; 265 pba.pba_pc = pc; 266 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 267 pba.pba_bus = 0; 268 pba.pba_bridgetag = NULL; 269 270 config_found_ia(self, "pcibus", &pba, pcibusprint); 271 } 272 273 static void 274 necpb_attach_hook(device_t parent, device_t self, 275 struct pcibus_attach_args *pba) 276 { 277 } 278 279 static int 280 necpb_bus_maxdevs(pci_chipset_tag_t pc, int busno) 281 { 282 283 return 32; 284 } 285 286 static pcitag_t 287 necpb_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 288 { 289 pcitag_t tag; 290 291 if (bus >= 256 || device >= 32 || function >= 8) 292 panic("%s: bad request", __func__); 293 294 tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8); 295 return tag; 296 } 297 298 static void 299 necpb_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, 300 int *fp) 301 { 302 303 if (bp != NULL) 304 *bp = (tag >> 16) & 0xff; 305 if (dp != NULL) 306 *dp = (tag >> 11) & 0x1f; 307 if (fp != NULL) 308 *fp = (tag >> 8) & 0x07; 309 } 310 311 static pcireg_t 312 necpb_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 313 { 314 pcireg_t data; 315 int s; 316 317 s = splhigh(); 318 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 319 data = in32(RD94_SYS_PCI_CONFDATA); 320 out32(RD94_SYS_PCI_CONFADDR, 0); 321 splx(s); 322 323 return data; 324 } 325 326 static void 327 necpb_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 328 { 329 int s; 330 331 s = splhigh(); 332 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 333 out32(RD94_SYS_PCI_CONFDATA, data); 334 out32(RD94_SYS_PCI_CONFADDR, 0); 335 splx(s); 336 } 337 338 static int 339 necpb_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 340 { 341 pci_chipset_tag_t pc = pa->pa_pc; 342 pcitag_t intrtag = pa->pa_intrtag; 343 int pin = pa->pa_intrpin; 344 int bus, dev; 345 346 if (pin == 0) { 347 /* No IRQ used. */ 348 *ihp = -1; 349 return 1; 350 } 351 352 if (pin > 4) { 353 printf("necpb_intr_map: bad interrupt pin %d\n", pin); 354 *ihp = -1; 355 return 1; 356 } 357 358 necpb_decompose_tag(pc, intrtag, &bus, &dev, NULL); 359 if (bus != 0) { 360 printf("necpb_intr_map: unknown bus %d\n", bus); 361 *ihp = -1; 362 return 1; 363 } 364 365 switch (dev) { 366 case 3: 367 *ihp = 3; 368 break; 369 case 4: 370 *ihp = 2; 371 break; 372 case 5: 373 *ihp = 1; 374 break; 375 default: 376 *ihp = -1; 377 return 1; 378 } 379 380 return 0; 381 } 382 383 static const char * 384 necpb_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 385 size_t len) 386 { 387 if (ih >= 4) 388 panic("%s: bogus handle %ld", __func__, ih); 389 snprintf(buf, len, "int %c", 'A' + (int)ih); 390 return buf; 391 } 392 393 static void * 394 necpb_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 395 int (*func)(void *), void *arg) 396 { 397 struct necpb_intrhand *n, *p; 398 uint32_t mask; 399 char buf[PCI_INTRSTR_LEN]; 400 401 if (ih >= 4) 402 panic("%s: bogus handle", __func__); 403 404 n = malloc(sizeof(struct necpb_intrhand), M_DEVBUF, M_NOWAIT); 405 if (n == NULL) 406 panic("%s: can't malloc interrupt handle", __func__); 407 408 n->ih_func = func; 409 n->ih_arg = arg; 410 n->ih_next = NULL; 411 n->ih_intn = ih; 412 strlcpy(n->ih_evname, necpb_intr_string(pc, ih, buf, sizeof(buf)), 413 sizeof(n->ih_evname)); 414 evcnt_attach_dynamic(&n->ih_evcnt, EVCNT_TYPE_INTR, NULL, "necpb", 415 n->ih_evname); 416 417 if (necpb_inttbl[ih] == NULL) { 418 necpb_inttbl[ih] = n; 419 mask = in32(RD94_SYS_PCI_INTMASK); 420 mask |= 1 << ih; 421 out32(RD94_SYS_PCI_INTMASK, mask); 422 } else { 423 p = necpb_inttbl[ih]; 424 while (p->ih_next != NULL) 425 p = p->ih_next; 426 p->ih_next = n; 427 } 428 429 return n; 430 } 431 432 static void 433 necpb_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 434 { 435 struct necpb_intrhand *n, *p, *q; 436 uint32_t mask; 437 438 n = cookie; 439 440 q = NULL; 441 p = necpb_inttbl[n->ih_intn]; 442 while (p != n) { 443 if (p == NULL) 444 panic("%s: broken intr table", __func__); 445 q = p; 446 p = p->ih_next; 447 } 448 449 if (q == NULL) { 450 necpb_inttbl[n->ih_intn] = n->ih_next; 451 if (n->ih_next == NULL) { 452 mask = in32(RD94_SYS_PCI_INTMASK); 453 mask &= ~(1 << n->ih_intn); 454 out32(RD94_SYS_PCI_INTMASK, mask); 455 } 456 } else 457 q->ih_next = n->ih_next; 458 459 evcnt_detach(&n->ih_evcnt); 460 461 free(n, M_DEVBUF); 462 } 463 464 /* 465 * Handle PCI/EISA interrupt. 466 */ 467 static uint32_t 468 necpb_intr(uint32_t mask, struct clockframe *cf) 469 { 470 uint32_t vector, stat; 471 struct necpb_intrhand *p; 472 int i, handled; 473 474 handled = 0; 475 vector = in32(RD94_SYS_INTSTAT2) & 0xffff; 476 477 if (vector == 0x4000) { 478 stat = in32(RD94_SYS_PCI_INTSTAT); 479 stat &= in32(RD94_SYS_PCI_INTMASK); 480 for (i = 0; i < 4; i++) { 481 if (stat & (1 << i)) { 482 #if 0 483 printf("pint %d\n", i); 484 #endif 485 p = necpb_inttbl[i]; 486 while (p != NULL) { 487 if ((*p->ih_func)(p->ih_arg)) { 488 p->ih_evcnt.ev_count++; 489 handled |= 1; 490 } 491 p = p->ih_next; 492 } 493 } 494 } 495 } else if (vector == 0x8000) { 496 printf("eisa_nmi\n"); 497 } else { 498 printf("eint %d\n", vector & 0xff); 499 #if 0 500 if (eisa_intr(vector & 0xff)) { 501 handled |= 1; 502 } 503 #endif 504 } 505 506 return handled ? MIPS_INT_MASK_2 : 0; 507 } 508 509 #ifdef PCI_NETBSD_CONFIGURE 510 static void 511 necpb_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int func, 512 int swiz, int *iline) 513 { 514 515 return; 516 } 517 518 static int 519 necpb_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, 520 pcireg_t id) 521 { 522 523 /* ignore bogus IDs */ 524 if (id == 0) 525 return 0; 526 527 /* don't configure bridges */ 528 if (bus == 0 && (dev == 1 || dev == 2)) 529 return 0; 530 531 return PCI_CONF_DEFAULT; 532 } 533 #endif 534
Indexes created Thu Oct 23 18:09:57 GMT 2025