necpb.c revision 1.4
1 /* $NetBSD: necpb.c,v 1.4 2000/06/29 08:34:12 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/types.h> 71 #include <sys/param.h> 72 #include <sys/time.h> 73 #include <sys/systm.h> 74 #include <sys/errno.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #include <sys/extent.h> 78 79 #include <uvm/uvm_extern.h> 80 81 #define _ARC_BUS_DMA_PRIVATE 82 #include <machine/bus.h> 83 84 #include <machine/pio.h> 85 86 #include <machine/autoconf.h> 87 #include <machine/cpu.h> 88 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcireg.h> 91 92 #include <arc/pica/rd94.h> 93 #include <arc/pci/necpbvar.h> 94 95 int necpbmatch __P((struct device *, struct cfdata *, void *)); 96 void necpbattach __P((struct device *, struct device *, void *)); 97 98 static int necpbprint __P((void *, const char *)); 99 100 void necpb_attach_hook __P((struct device *, struct device *, 101 struct pcibus_attach_args *)); 102 int necpb_bus_maxdevs __P((pci_chipset_tag_t, int)); 103 pcitag_t necpb_make_tag __P((pci_chipset_tag_t, int, int, int)); 104 void necpb_decompose_tag __P((pci_chipset_tag_t, pcitag_t, int *, 105 int *, int *)); 106 pcireg_t necpb_conf_read __P((pci_chipset_tag_t, pcitag_t, int)); 107 void necpb_conf_write __P((pci_chipset_tag_t, pcitag_t, int, 108 pcireg_t)); 109 int necpb_intr_map __P((pci_chipset_tag_t, pcitag_t, int, int, 110 pci_intr_handle_t *)); 111 const char * necpb_intr_string __P((pci_chipset_tag_t, pci_intr_handle_t)); 112 void * necpb_intr_establish __P((pci_chipset_tag_t, pci_intr_handle_t, 113 int, int (*func)(void *), void *)); 114 void necpb_intr_disestablish __P((pci_chipset_tag_t, void *)); 115 116 int necpb_intr(unsigned, struct clockframe *); 117 118 119 struct cfattach necpb_ca = { 120 sizeof(struct necpb_softc), necpbmatch, necpbattach, 121 }; 122 123 extern struct cfdriver necpb_cd; 124 125 static struct necpb_intrhand *necpb_inttbl[4]; 126 127 /* There can be only one. */ 128 int necpbfound; 129 struct necpb_config necpb_configuration; 130 static long necpb_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 131 static long necpb_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 132 133 int 134 necpbmatch(parent, match, aux) 135 struct device *parent; 136 struct cfdata *match; 137 void *aux; 138 { 139 struct confargs *ca = aux; 140 141 if (strcmp(ca->ca_name, necpb_cd.cd_name) != 0) 142 return (0); 143 144 if (necpbfound) 145 return (0); 146 147 return (1); 148 } 149 150 /* 151 * Set up the chipset's function pointers. 152 */ 153 void 154 necpb_init(ncp) 155 struct necpb_config *ncp; 156 { 157 pcitag_t tag; 158 pcireg_t csr; 159 160 if (ncp->nc_initialized) 161 return; 162 163 arc_large_bus_space_init(&ncp->nc_memt, "necpcimem", 164 RD94_P_PCI_MEM, 0, RD94_S_PCI_MEM); 165 arc_bus_space_init_extent(&ncp->nc_memt, (caddr_t)necpb_mem_ex_storage, 166 sizeof(necpb_mem_ex_storage)); 167 168 arc_bus_space_init(&ncp->nc_iot, "necpciio", 169 RD94_P_PCI_IO, RD94_V_PCI_IO, 0, RD94_S_PCI_IO); 170 arc_bus_space_init_extent(&ncp->nc_iot, (caddr_t)necpb_io_ex_storage, 171 sizeof(necpb_io_ex_storage)); 172 173 jazz_bus_dma_tag_init(&ncp->nc_dmat); 174 175 ncp->nc_pc.pc_attach_hook = necpb_attach_hook; 176 ncp->nc_pc.pc_bus_maxdevs = necpb_bus_maxdevs; 177 ncp->nc_pc.pc_make_tag = necpb_make_tag; 178 ncp->nc_pc.pc_conf_read = necpb_conf_read; 179 ncp->nc_pc.pc_conf_write = necpb_conf_write; 180 ncp->nc_pc.pc_intr_map = necpb_intr_map; 181 ncp->nc_pc.pc_intr_string = necpb_intr_string; 182 ncp->nc_pc.pc_intr_establish = necpb_intr_establish; 183 ncp->nc_pc.pc_intr_disestablish = necpb_intr_disestablish; 184 185 /* XXX: enable all mem/io/busmaster */ 186 tag = necpb_make_tag(&ncp->nc_pc, 0, 3, 0); 187 csr = necpb_conf_read(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG); 188 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 189 PCI_COMMAND_MASTER_ENABLE; 190 necpb_conf_write(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 191 192 tag = necpb_make_tag(&ncp->nc_pc, 0, 4, 0); 193 csr = necpb_conf_read(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG); 194 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 195 PCI_COMMAND_MASTER_ENABLE; 196 necpb_conf_write(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 197 198 tag = necpb_make_tag(&ncp->nc_pc, 0, 5, 0); 199 csr = necpb_conf_read(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG); 200 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 201 PCI_COMMAND_MASTER_ENABLE; 202 necpb_conf_write(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 203 204 ncp->nc_initialized = 1; 205 } 206 207 void 208 necpbattach(parent, self, aux) 209 struct device *parent, *self; 210 void *aux; 211 { 212 struct necpb_softc *sc = (struct necpb_softc *)self; 213 struct pcibus_attach_args pba; 214 int i; 215 216 necpbfound = 1; 217 218 printf("\n"); 219 220 sc->sc_ncp = &necpb_configuration; 221 necpb_init(sc->sc_ncp); 222 223 out32(RD94_SYS_PCI_INTMASK, 0xf); 224 225 for (i = 0; i < 4; i++) 226 necpb_inttbl[i] = NULL; 227 228 set_intr(MIPS_INT_MASK_2, necpb_intr, 3); 229 230 pba.pba_busname = "pci"; 231 pba.pba_iot = &sc->sc_ncp->nc_iot; 232 pba.pba_memt = &sc->sc_ncp->nc_memt; 233 pba.pba_dmat = &sc->sc_ncp->nc_dmat; 234 pba.pba_pc = &sc->sc_ncp->nc_pc; 235 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 236 pba.pba_bus = 0; 237 238 config_found(self, &pba, necpbprint); 239 } 240 241 static int 242 necpbprint(aux, pnp) 243 void *aux; 244 const char *pnp; 245 { 246 struct pcibus_attach_args *pba = aux; 247 248 if (pnp) 249 printf("%s at %s", pba->pba_busname, pnp); 250 printf(" bus %d", pba->pba_bus); 251 return (UNCONF); 252 } 253 254 void 255 necpb_attach_hook(parent, self, pba) 256 struct device *parent, *self; 257 struct pcibus_attach_args *pba; 258 { 259 } 260 261 int 262 necpb_bus_maxdevs(pc, busno) 263 pci_chipset_tag_t pc; 264 int busno; 265 { 266 return (32); 267 } 268 269 pcitag_t 270 necpb_make_tag(pc, bus, device, function) 271 pci_chipset_tag_t pc; 272 int bus, device, function; 273 { 274 pcitag_t tag; 275 276 if (bus >= 256 || device >= 32 || function >= 8) 277 panic("necpb_make_tag: bad request"); 278 279 tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8); 280 return (tag); 281 } 282 283 void 284 necpb_decompose_tag(pc, tag, bp, dp, fp) 285 pci_chipset_tag_t pc; 286 pcitag_t tag; 287 int *bp, *dp, *fp; 288 { 289 if (bp != NULL) 290 *bp = (tag >> 16) & 0xff; 291 if (dp != NULL) 292 *dp = (tag >> 11) & 0x1f; 293 if (fp != NULL) 294 *fp = (tag >> 8) & 0x07; 295 } 296 297 pcireg_t 298 necpb_conf_read(pc, tag, reg) 299 pci_chipset_tag_t pc; 300 pcitag_t tag; 301 int reg; 302 { 303 pcireg_t data; 304 int s; 305 306 s = splhigh(); 307 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 308 data = in32(RD94_SYS_PCI_CONFDATA); 309 out32(RD94_SYS_PCI_CONFADDR, 0); 310 splx(s); 311 312 return (data); 313 } 314 315 void 316 necpb_conf_write(pc, tag, reg, data) 317 pci_chipset_tag_t pc; 318 pcitag_t tag; 319 int reg; 320 pcireg_t data; 321 { 322 int s; 323 324 s = splhigh(); 325 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 326 out32(RD94_SYS_PCI_CONFDATA, data); 327 out32(RD94_SYS_PCI_CONFADDR, 0); 328 splx(s); 329 } 330 331 int 332 necpb_intr_map(pc, intrtag, pin, line, ihp) 333 pci_chipset_tag_t pc; 334 pcitag_t intrtag; 335 int pin, line; 336 pci_intr_handle_t *ihp; 337 { 338 int bus, dev; 339 340 if (pin == 0) { 341 /* No IRQ used. */ 342 *ihp = -1; 343 return (1); 344 } 345 346 if (pin > 4) { 347 printf("necpb_intr_map: bad interrupt pin %d\n", pin); 348 *ihp = -1; 349 return (1); 350 } 351 352 necpb_decompose_tag(pc, intrtag, &bus, &dev, NULL); 353 if (bus != 0) { 354 *ihp = -1; 355 return (1); 356 } 357 358 switch (dev) { 359 case 3: 360 *ihp = (pin+2) % 4; 361 break; 362 case 4: 363 *ihp = (pin+1) % 4; 364 break; 365 case 5: 366 *ihp = (pin) % 4; 367 break; 368 default: 369 *ihp = -1; 370 return (1); 371 } 372 373 return (0); 374 } 375 376 const char * 377 necpb_intr_string(pc, ih) 378 pci_chipset_tag_t pc; 379 pci_intr_handle_t ih; 380 { 381 static char str[8]; 382 383 if (ih >= 4) 384 panic("necpb_intr_string: bogus handle %d", ih); 385 sprintf(str, "int %c", 'A' + (int)ih); 386 return (str); 387 } 388 389 void * 390 necpb_intr_establish(pc, ih, level, func, arg) 391 pci_chipset_tag_t pc; 392 pci_intr_handle_t ih; 393 int level, (*func) __P((void *)); 394 void *arg; 395 { 396 struct necpb_intrhand *n, *p; 397 u_int32_t mask; 398 399 if (ih >= 4) 400 panic("necpb_intr_establish: bogus handle"); 401 402 n = malloc(sizeof(struct necpb_intrhand), M_DEVBUF, M_NOWAIT); 403 if (n == NULL) 404 panic("necpb_intr_establish: can't malloc interrupt handle"); 405 406 n->ih_func = func; 407 n->ih_arg = arg; 408 n->ih_next = NULL; 409 n->ih_intn = ih; 410 411 if (necpb_inttbl[ih] == NULL) { 412 necpb_inttbl[ih] = n; 413 mask = in32(RD94_SYS_PCI_INTMASK); 414 mask |= 1 << ih; 415 out32(RD94_SYS_PCI_INTMASK, mask); 416 } else { 417 p = necpb_inttbl[ih]; 418 while (p->ih_next != NULL) 419 p = p->ih_next; 420 p->ih_next = n; 421 } 422 423 return n; 424 } 425 426 void 427 necpb_intr_disestablish(pc, cookie) 428 pci_chipset_tag_t pc; 429 void *cookie; 430 { 431 struct necpb_intrhand *n, *p, *q; 432 u_int32_t mask; 433 434 n = cookie; 435 436 q = NULL; 437 p = necpb_inttbl[n->ih_intn]; 438 while (p != n) { 439 if (p == NULL) 440 panic("necpb_intr_disestablish: broken intr table"); 441 q = p; 442 p = p->ih_next; 443 } 444 445 if (q == NULL) { 446 necpb_inttbl[n->ih_intn] = n->ih_next; 447 if (n->ih_next == NULL) { 448 mask = in32(RD94_SYS_PCI_INTMASK); 449 mask &= ~(1 << n->ih_intn); 450 out32(RD94_SYS_PCI_INTMASK, mask); 451 } 452 } else 453 q->ih_next = n->ih_next; 454 455 free(n, M_DEVBUF); 456 } 457 458 /* 459 * Handle PCI/EISA interrupt. 460 */ 461 int 462 necpb_intr(mask, cf) 463 unsigned mask; 464 struct clockframe *cf; 465 { 466 u_int32_t vector, stat; 467 struct necpb_intrhand *p; 468 int a; 469 470 vector = in32(RD94_SYS_INTSTAT2) & 0xffff; 471 472 if (vector == 0x4000) { 473 stat = in32(RD94_SYS_PCI_INTSTAT); 474 stat &= in32(RD94_SYS_PCI_INTMASK); 475 for (a=0; a<4; a++) { 476 if (stat & (1 << a)) { 477 #if 0 478 printf("pint %d\n", a); 479 #endif 480 p = necpb_inttbl[a]; 481 while (p != NULL) { 482 (*p->ih_func)(p->ih_arg); 483 p = p->ih_next; 484 } 485 } 486 } 487 } else if (vector == 0x8000) { 488 printf("eisa_nmi\n"); 489 } else { 490 printf("eint %d\n", vector & 0xff); 491 #if 0 492 eisa_intr(vector & 0xff); 493 #endif 494 } 495 496 return (~0); 497 } 498
Indexes created Wed Oct 22 13:09:56 GMT 2025