necpb.c revision 1.8
1 /* $NetBSD: necpb.c,v 1.8 2001/06/13 15:18:27 soda Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/types.h> 71 #include <sys/param.h> 72 #include <sys/time.h> 73 #include <sys/systm.h> 74 #include <sys/errno.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #include <sys/extent.h> 78 79 #include <uvm/uvm_extern.h> 80 81 #define _ARC_BUS_DMA_PRIVATE 82 #include <machine/bus.h> 83 84 #include <machine/pio.h> 85 86 #include <machine/autoconf.h> 87 #include <machine/cpu.h> 88 #include <machine/platform.h> 89 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcireg.h> 92 93 #include <arc/jazz/rd94.h> 94 #include <arc/pci/necpbvar.h> 95 96 int necpbmatch __P((struct device *, struct cfdata *, void *)); 97 void necpbattach __P((struct device *, struct device *, void *)); 98 99 static int necpbprint __P((void *, const char *)); 100 101 void necpb_attach_hook __P((struct device *, struct device *, 102 struct pcibus_attach_args *)); 103 int necpb_bus_maxdevs __P((pci_chipset_tag_t, int)); 104 pcitag_t necpb_make_tag __P((pci_chipset_tag_t, int, int, int)); 105 void necpb_decompose_tag __P((pci_chipset_tag_t, pcitag_t, int *, 106 int *, int *)); 107 pcireg_t necpb_conf_read __P((pci_chipset_tag_t, pcitag_t, int)); 108 void necpb_conf_write __P((pci_chipset_tag_t, pcitag_t, int, 109 pcireg_t)); 110 int necpb_intr_map __P((struct pci_attach_args *, 111 pci_intr_handle_t *)); 112 const char * necpb_intr_string __P((pci_chipset_tag_t, pci_intr_handle_t)); 113 void * necpb_intr_establish __P((pci_chipset_tag_t, pci_intr_handle_t, 114 int, int (*func)(void *), void *)); 115 void necpb_intr_disestablish __P((pci_chipset_tag_t, void *)); 116 117 int necpb_intr(unsigned, struct clockframe *); 118 119 120 struct cfattach necpb_ca = { 121 sizeof(struct necpb_softc), necpbmatch, necpbattach, 122 }; 123 124 extern struct cfdriver necpb_cd; 125 126 static struct necpb_intrhand *necpb_inttbl[4]; 127 128 /* There can be only one. */ 129 int necpbfound; 130 struct necpb_context necpb_main_context; 131 static long necpb_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 132 static long necpb_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 133 134 int 135 necpbmatch(parent, match, aux) 136 struct device *parent; 137 struct cfdata *match; 138 void *aux; 139 { 140 struct confargs *ca = aux; 141 142 if (strcmp(ca->ca_name, necpb_cd.cd_name) != 0) 143 return (0); 144 145 if (necpbfound) 146 return (0); 147 148 return (1); 149 } 150 151 /* 152 * Set up the chipset's function pointers. 153 */ 154 void 155 necpb_init(ncp) 156 struct necpb_context *ncp; 157 { 158 pcitag_t tag; 159 pcireg_t csr; 160 161 if (ncp->nc_initialized) 162 return; 163 164 arc_large_bus_space_init(&ncp->nc_memt, "necpcimem", 165 RD94_P_PCI_MEM, 0, RD94_S_PCI_MEM); 166 arc_bus_space_init_extent(&ncp->nc_memt, (caddr_t)necpb_mem_ex_storage, 167 sizeof(necpb_mem_ex_storage)); 168 169 arc_bus_space_init(&ncp->nc_iot, "necpciio", 170 RD94_P_PCI_IO, RD94_V_PCI_IO, 0, RD94_S_PCI_IO); 171 arc_bus_space_init_extent(&ncp->nc_iot, (caddr_t)necpb_io_ex_storage, 172 sizeof(necpb_io_ex_storage)); 173 174 jazz_bus_dma_tag_init(&ncp->nc_dmat); 175 176 ncp->nc_pc.pc_attach_hook = necpb_attach_hook; 177 ncp->nc_pc.pc_bus_maxdevs = necpb_bus_maxdevs; 178 ncp->nc_pc.pc_make_tag = necpb_make_tag; 179 ncp->nc_pc.pc_conf_read = necpb_conf_read; 180 ncp->nc_pc.pc_conf_write = necpb_conf_write; 181 ncp->nc_pc.pc_intr_map = necpb_intr_map; 182 ncp->nc_pc.pc_intr_string = necpb_intr_string; 183 ncp->nc_pc.pc_intr_establish = necpb_intr_establish; 184 ncp->nc_pc.pc_intr_disestablish = necpb_intr_disestablish; 185 186 /* XXX: enable all mem/io/busmaster */ 187 tag = necpb_make_tag(&ncp->nc_pc, 0, 3, 0); 188 csr = necpb_conf_read(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG); 189 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 190 PCI_COMMAND_MASTER_ENABLE; 191 necpb_conf_write(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 192 193 tag = necpb_make_tag(&ncp->nc_pc, 0, 4, 0); 194 csr = necpb_conf_read(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG); 195 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 196 PCI_COMMAND_MASTER_ENABLE; 197 necpb_conf_write(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 198 199 tag = necpb_make_tag(&ncp->nc_pc, 0, 5, 0); 200 csr = necpb_conf_read(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG); 201 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 202 PCI_COMMAND_MASTER_ENABLE; 203 necpb_conf_write(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 204 205 ncp->nc_initialized = 1; 206 } 207 208 void 209 necpbattach(parent, self, aux) 210 struct device *parent, *self; 211 void *aux; 212 { 213 struct necpb_softc *sc = (struct necpb_softc *)self; 214 struct pcibus_attach_args pba; 215 int i; 216 217 necpbfound = 1; 218 219 printf("\n"); 220 221 sc->sc_ncp = &necpb_main_context; 222 necpb_init(sc->sc_ncp); 223 224 out32(RD94_SYS_PCI_INTMASK, 0xf); 225 226 for (i = 0; i < 4; i++) 227 necpb_inttbl[i] = NULL; 228 229 (*platform->set_intr)(MIPS_INT_MASK_2, necpb_intr, 3); 230 231 pba.pba_busname = "pci"; 232 pba.pba_iot = &sc->sc_ncp->nc_iot; 233 pba.pba_memt = &sc->sc_ncp->nc_memt; 234 pba.pba_dmat = &sc->sc_ncp->nc_dmat; 235 pba.pba_pc = &sc->sc_ncp->nc_pc; 236 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 237 pba.pba_bus = 0; 238 239 config_found(self, &pba, necpbprint); 240 } 241 242 static int 243 necpbprint(aux, pnp) 244 void *aux; 245 const char *pnp; 246 { 247 struct pcibus_attach_args *pba = aux; 248 249 if (pnp) 250 printf("%s at %s", pba->pba_busname, pnp); 251 printf(" bus %d", pba->pba_bus); 252 return (UNCONF); 253 } 254 255 void 256 necpb_attach_hook(parent, self, pba) 257 struct device *parent, *self; 258 struct pcibus_attach_args *pba; 259 { 260 } 261 262 int 263 necpb_bus_maxdevs(pc, busno) 264 pci_chipset_tag_t pc; 265 int busno; 266 { 267 return (32); 268 } 269 270 pcitag_t 271 necpb_make_tag(pc, bus, device, function) 272 pci_chipset_tag_t pc; 273 int bus, device, function; 274 { 275 pcitag_t tag; 276 277 if (bus >= 256 || device >= 32 || function >= 8) 278 panic("necpb_make_tag: bad request"); 279 280 tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8); 281 return (tag); 282 } 283 284 void 285 necpb_decompose_tag(pc, tag, bp, dp, fp) 286 pci_chipset_tag_t pc; 287 pcitag_t tag; 288 int *bp, *dp, *fp; 289 { 290 if (bp != NULL) 291 *bp = (tag >> 16) & 0xff; 292 if (dp != NULL) 293 *dp = (tag >> 11) & 0x1f; 294 if (fp != NULL) 295 *fp = (tag >> 8) & 0x07; 296 } 297 298 pcireg_t 299 necpb_conf_read(pc, tag, reg) 300 pci_chipset_tag_t pc; 301 pcitag_t tag; 302 int reg; 303 { 304 pcireg_t data; 305 int s; 306 307 s = splhigh(); 308 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 309 data = in32(RD94_SYS_PCI_CONFDATA); 310 out32(RD94_SYS_PCI_CONFADDR, 0); 311 splx(s); 312 313 return (data); 314 } 315 316 void 317 necpb_conf_write(pc, tag, reg, data) 318 pci_chipset_tag_t pc; 319 pcitag_t tag; 320 int reg; 321 pcireg_t data; 322 { 323 int s; 324 325 s = splhigh(); 326 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 327 out32(RD94_SYS_PCI_CONFDATA, data); 328 out32(RD94_SYS_PCI_CONFADDR, 0); 329 splx(s); 330 } 331 332 int 333 necpb_intr_map(pa, ihp) 334 struct pci_attach_args *pa; 335 pci_intr_handle_t *ihp; 336 { 337 pci_chipset_tag_t pc = pa->pa_pc; 338 pcitag_t intrtag = pa->pa_intrtag; 339 int pin = pa->pa_intrpin; 340 int bus, dev; 341 342 if (pin == 0) { 343 /* No IRQ used. */ 344 *ihp = -1; 345 return (1); 346 } 347 348 if (pin > 4) { 349 printf("necpb_intr_map: bad interrupt pin %d\n", pin); 350 *ihp = -1; 351 return (1); 352 } 353 354 necpb_decompose_tag(pc, intrtag, &bus, &dev, NULL); 355 if (bus != 0) { 356 *ihp = -1; 357 return (1); 358 } 359 360 switch (dev) { 361 case 3: 362 *ihp = (pin+2) % 4; 363 break; 364 case 4: 365 *ihp = (pin+1) % 4; 366 break; 367 case 5: 368 *ihp = (pin) % 4; 369 break; 370 default: 371 *ihp = -1; 372 return (1); 373 } 374 375 return (0); 376 } 377 378 const char * 379 necpb_intr_string(pc, ih) 380 pci_chipset_tag_t pc; 381 pci_intr_handle_t ih; 382 { 383 static char str[8]; 384 385 if (ih >= 4) 386 panic("necpb_intr_string: bogus handle %ld", ih); 387 sprintf(str, "int %c", 'A' + (int)ih); 388 return (str); 389 } 390 391 void * 392 necpb_intr_establish(pc, ih, level, func, arg) 393 pci_chipset_tag_t pc; 394 pci_intr_handle_t ih; 395 int level, (*func) __P((void *)); 396 void *arg; 397 { 398 struct necpb_intrhand *n, *p; 399 u_int32_t mask; 400 401 if (ih >= 4) 402 panic("necpb_intr_establish: bogus handle"); 403 404 n = malloc(sizeof(struct necpb_intrhand), M_DEVBUF, M_NOWAIT); 405 if (n == NULL) 406 panic("necpb_intr_establish: can't malloc interrupt handle"); 407 408 n->ih_func = func; 409 n->ih_arg = arg; 410 n->ih_next = NULL; 411 n->ih_intn = ih; 412 413 if (necpb_inttbl[ih] == NULL) { 414 necpb_inttbl[ih] = n; 415 mask = in32(RD94_SYS_PCI_INTMASK); 416 mask |= 1 << ih; 417 out32(RD94_SYS_PCI_INTMASK, mask); 418 } else { 419 p = necpb_inttbl[ih]; 420 while (p->ih_next != NULL) 421 p = p->ih_next; 422 p->ih_next = n; 423 } 424 425 return n; 426 } 427 428 void 429 necpb_intr_disestablish(pc, cookie) 430 pci_chipset_tag_t pc; 431 void *cookie; 432 { 433 struct necpb_intrhand *n, *p, *q; 434 u_int32_t mask; 435 436 n = cookie; 437 438 q = NULL; 439 p = necpb_inttbl[n->ih_intn]; 440 while (p != n) { 441 if (p == NULL) 442 panic("necpb_intr_disestablish: broken intr table"); 443 q = p; 444 p = p->ih_next; 445 } 446 447 if (q == NULL) { 448 necpb_inttbl[n->ih_intn] = n->ih_next; 449 if (n->ih_next == NULL) { 450 mask = in32(RD94_SYS_PCI_INTMASK); 451 mask &= ~(1 << n->ih_intn); 452 out32(RD94_SYS_PCI_INTMASK, mask); 453 } 454 } else 455 q->ih_next = n->ih_next; 456 457 free(n, M_DEVBUF); 458 } 459 460 /* 461 * Handle PCI/EISA interrupt. 462 */ 463 int 464 necpb_intr(mask, cf) 465 unsigned mask; 466 struct clockframe *cf; 467 { 468 u_int32_t vector, stat; 469 struct necpb_intrhand *p; 470 int a; 471 472 vector = in32(RD94_SYS_INTSTAT2) & 0xffff; 473 474 if (vector == 0x4000) { 475 stat = in32(RD94_SYS_PCI_INTSTAT); 476 stat &= in32(RD94_SYS_PCI_INTMASK); 477 for (a=0; a<4; a++) { 478 if (stat & (1 << a)) { 479 #if 0 480 printf("pint %d\n", a); 481 #endif 482 p = necpb_inttbl[a]; 483 while (p != NULL) { 484 (*p->ih_func)(p->ih_arg); 485 p = p->ih_next; 486 } 487 } 488 } 489 } else if (vector == 0x8000) { 490 printf("eisa_nmi\n"); 491 } else { 492 printf("eint %d\n", vector & 0xff); 493 #if 0 494 eisa_intr(vector & 0xff); 495 #endif 496 } 497 498 return (~0); 499 } 500
Indexes created Wed Oct 22 13:09:56 GMT 2025