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cycv_platform.c revision 1.13 
      1 /* $NetBSD: cycv_platform.c,v 1.13 2020/07/10 12:25:08 skrll Exp $ */
      2 
      3 /* This file is in the public domain. */
      4 
      5 #include "arml2cc.h"
      6 #include "opt_console.h"
      7 #include "opt_multiprocessor.h"
      8 
      9 #include <sys/cdefs.h>
     10 __KERNEL_RCSID(0, "$NetBSD: cycv_platform.c,v 1.13 2020/07/10 12:25:08 skrll Exp $");
     11 
     12 #define	_ARM32_BUS_DMA_PRIVATE
     13 #include <sys/param.h>
     14 #include <sys/bus.h>
     15 #include <sys/cpu.h>
     16 #include <sys/device.h>
     17 
     18 #include <uvm/uvm_extern.h>
     19 
     20 #include <arm/arm32/machdep.h>
     21 
     22 #include <arm/altera/cycv_reg.h>
     23 #include <arm/altera/cycv_var.h>
     24 #include <arm/cortex/a9tmr_var.h>
     25 #include <arm/cortex/pl310_var.h>
     26 #include <arm/cortex/scu_reg.h>
     27 
     28 #include <arm/bootconfig.h>
     29 #include <arm/cpufunc.h>
     30 
     31 #include <arm/fdt/arm_fdtvar.h>
     32 #include <dev/fdt/fdtvar.h>
     33 #include <dev/ic/comreg.h>
     34 
     35 void cycv_platform_early_putchar(char);
     36 
     37 void __noasan
     38 cycv_platform_early_putchar(char c) {
     39 #ifdef CONSADDR
     40 #define CONSADDR_VA (CONSADDR - CYCV_PERIPHERAL_BASE + CYCV_PERIPHERAL_VBASE)
     41 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
     42 	    (volatile uint32_t *) CONSADDR_VA :
     43 	    (volatile uint32_t *) CONSADDR;
     44 
     45 	while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0)
     46 		;
     47 
     48 	uartaddr[com_data] = htole32(c);
     49 #endif
     50 }
     51 
     52 static const struct pmap_devmap *
     53 cycv_platform_devmap(void) {
     54 	static const struct pmap_devmap devmap[] = {
     55 		DEVMAP_ENTRY(CYCV_PERIPHERAL_VBASE,
     56 				CYCV_PERIPHERAL_BASE,
     57 				CYCV_PERIPHERAL_SIZE),
     58 		DEVMAP_ENTRY_END
     59 	};
     60 
     61 	return devmap;
     62 }
     63 
     64 static void
     65 cycv_platform_bootstrap(void)
     66 {
     67 	bus_space_tag_t bst = &armv7_generic_bs_tag;
     68 	bus_space_handle_t bsh_l2c;
     69 
     70 	bus_space_map(bst, CYCV_L2CACHE_BASE, CYCV_L2CACHE_SIZE, 0, &bsh_l2c);
     71 
     72 #if NARML2CC > 0
     73 	arml2cc_init(bst, bsh_l2c, 0);
     74 #endif
     75 
     76 	arm_fdt_cpu_bootstrap();
     77 }
     78 
     79 static int
     80 cycv_mpstart(void)
     81 {
     82 	bus_space_tag_t bst = &armv7_generic_bs_tag;
     83 	bus_space_handle_t bsh_rst;
     84 	bus_space_handle_t bsh_scu;
     85 	int ret = 0;
     86 
     87 	bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh_rst);
     88 	bus_space_map(bst, CYCV_SCU_BASE, CYCV_SCU_SIZE, 0, &bsh_scu);
     89 
     90 	/* Enable Snoop Control Unit */
     91 	bus_space_write_4(bst, bsh_scu, SCU_INV_ALL_REG, 0xff);
     92 	bus_space_write_4(bst, bsh_scu, SCU_CTL,
     93 		bus_space_read_4(bst, bsh_scu, SCU_CTL) | SCU_CTL_SCU_ENA);
     94 
     95 	const uint32_t startfunc =
     96 		(uint32_t) KERN_VTOPHYS((vaddr_t) cpu_mpstart);
     97 
     98 	/*
     99 	 * We place a "LDR PC, =cpu_mpstart" at address 0 in order to bootstrap
    100 	 * CPU 1. We can't use the similar feature of the Boot ROM because
    101 	 * it was unmapped by u-boot in favor of the SDRAM.
    102 	 */
    103 	pmap_map_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, CYCV_SDRAM_BASE,
    104 		L1_S_SIZE, VM_PROT_READ|VM_PROT_WRITE, PMAP_NOCACHE);
    105 
    106 	/* 0: LDR PC, [PC, #0x18] -> loads address at 0x20 into PC */
    107 	*(volatile uint32_t *) CYCV_SDRAM_VBASE = htole32(0xe59ff018);
    108 	*(volatile uint32_t *) (CYCV_SDRAM_VBASE + 0x20) = startfunc;
    109 
    110 	pmap_unmap_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, L1_S_SIZE);
    111 
    112 	bus_space_write_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST,
    113 		bus_space_read_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST) &
    114 			~CYCV_RSTMGR_MPUMODRST_CPU1);
    115 
    116 	/* Wait for secondary processor to start */
    117 	int i;
    118 	for (i = 0x10000000; i > 0; i--) {
    119 		membar_consumer();
    120 		if (cpu_hatched_p(1))
    121 			break;
    122 	}
    123 	if (i == 0) {
    124 		aprint_error("cpu%d: WARNING: AP failed to start\n", 1);
    125 		ret++;
    126 	}
    127 
    128 	return ret;
    129 }
    130 
    131 static void
    132 cycv_platform_init_attach_args(struct fdt_attach_args *faa) {
    133 	faa->faa_bst = &armv7_generic_bs_tag;
    134 	faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
    135 	faa->faa_dmat = &arm_generic_dma_tag;
    136 }
    137 
    138 static void
    139 cycv_platform_device_register(device_t dev, void *aux) {
    140 	prop_dictionary_t dict = device_properties(dev);
    141 
    142 	if (device_is_a(dev, "arma9tmr")) {
    143 		prop_dictionary_set_uint32(dict, "frequency",
    144 			cycv_clkmgr_early_get_mpu_clk() / 4);
    145 	}
    146 }
    147 
    148 static void
    149 cycv_platform_reset(void) {
    150 	bus_space_tag_t bst = &armv7_generic_bs_tag;
    151 	bus_space_handle_t bsh;
    152 	uint32_t val;
    153 
    154 	bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh);
    155 	val = bus_space_read_4(bst, bsh, CYCV_RSTMGR_CTRL);
    156 	bus_space_write_4(bst, bsh, CYCV_RSTMGR_CTRL,
    157 		val | CYCV_RSTMGR_CTRL_SWCOLDRSTREQ);
    158 }
    159 
    160 static u_int
    161 cycv_platform_uart_freq(void) {
    162 	return cycv_clkmgr_early_get_l4_sp_clk();
    163 }
    164 
    165 static const struct arm_platform cycv_platform = {
    166 	.ap_devmap = cycv_platform_devmap,
    167 	.ap_bootstrap = cycv_platform_bootstrap,
    168 	.ap_init_attach_args = cycv_platform_init_attach_args,
    169 	.ap_device_register = cycv_platform_device_register,
    170 	.ap_reset = cycv_platform_reset,
    171 	.ap_delay = a9tmr_delay,
    172 	.ap_uart_freq = cycv_platform_uart_freq,
    173 	.ap_mpstart = cycv_mpstart,
    174 };
    175 
    176 ARM_PLATFORM(cycv, "altr,socfpga-cyclone5", &cycv_platform);
    177