meson8b_clkc.c revision 1.2.2.2
1 /* $NetBSD: meson8b_clkc.c,v 1.2.2.2 2019/01/26 21:59:59 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: meson8b_clkc.c,v 1.2.2.2 2019/01/26 21:59:59 pgoyette Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/amlogic/meson_clk.h> 41 #include <arm/amlogic/meson8b_clkc.h> 42 43 /* 44 * The DT for amlogic,meson8b-clkc defines two reg resources. The first 45 * is not used by this driver. 46 */ 47 #define MESON8B_CLKC_REG_INDEX 1 48 49 #define CBUS_REG(x) ((x) << 2) 50 51 #define HHI_GCLK_MPEG0 CBUS_REG(0x50) 52 #define HHI_GCLK_MPEG1 CBUS_REG(0x51) 53 #define HHI_GCLK_MPEG2 CBUS_REG(0x52) 54 #define HHI_SYS_CPU_CLK_CNTL1 CBUS_REG(0x57) 55 #define HHI_MPEG_CLK_CNTL CBUS_REG(0x5d) 56 #define HHI_SYS_CPU_CLK_CNTL0 CBUS_REG(0x67) 57 #define HHI_SYS_CPU_CLK_CNTL0_CLKSEL __BIT(7) 58 #define HHI_SYS_CPU_CLK_CNTL0_SOUTSEL __BITS(3,2) 59 #define HHI_SYS_CPU_CLK_CNTL0_PLLSEL __BITS(1,0) 60 #define HHI_MPLL_CNTL CBUS_REG(0xa0) 61 #define HHI_MPLL_CNTL2 CBUS_REG(0xa1) 62 #define HHI_MPLL_CNTL5 CBUS_REG(0xa4) 63 #define HHI_MPLL_CNTL6 CBUS_REG(0xa5) 64 #define HHI_MPLL_CNTL7 CBUS_REG(0xa6) 65 #define HHI_MPLL_CNTL8 CBUS_REG(0xa7) 66 #define HHI_MPLL_CNTL9 CBUS_REG(0xa8) 67 #define HHI_SYS_PLL_CNTL CBUS_REG(0xc0) 68 #define HHI_SYS_PLL_CNTL_LOCK __BIT(31) 69 #define HHI_SYS_PLL_CNTL_OD __BITS(17,16) 70 #define HHI_SYS_PLL_CNTL_DIV __BITS(14,9) 71 #define HHI_SYS_PLL_CNTL_MUL __BITS(8,0) 72 73 static int meson8b_clkc_match(device_t, cfdata_t, void *); 74 static void meson8b_clkc_attach(device_t, device_t, void *); 75 76 static const char * const compatible[] = { 77 "amlogic,meson8b-clkc", 78 NULL 79 }; 80 81 CFATTACH_DECL_NEW(meson8b_clkc, sizeof(struct meson_clk_softc), 82 meson8b_clkc_match, meson8b_clkc_attach, NULL, NULL); 83 84 static struct meson_clk_reset meson8b_clkc_resets[] = { 85 MESON_CLK_RESET(MESON8B_RESET_CPU0_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 24), 86 MESON_CLK_RESET(MESON8B_RESET_CPU1_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 25), 87 MESON_CLK_RESET(MESON8B_RESET_CPU2_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 26), 88 MESON_CLK_RESET(MESON8B_RESET_CPU3_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 27), 89 }; 90 91 static const char *mpeg_sel_parents[] = { "xtal", NULL, "fclk_div7", "mpll_clkout1", "mpll_clkout2", "fclk_div4", "fclk_div3", "fclk_div5" }; 92 static const char *cpu_in_sel_parents[] = { "xtal", "sys_pll" }; 93 static const char *cpu_scale_out_sel_parents[] = { "cpu_in_sel", "cpu_in_div2", "cpu_in_div3", "cpu_scale_div" }; 94 static const char *cpu_clk_parents[] = { "xtal", "cpu_scale_out_sel" }; 95 static const char *periph_clk_sel_parents[] = { "cpu_clk_div2", "cpu_clk_div3", "cpu_clk_div4", "cpu_clk_div5", "cpu_clk_div6", "cpu_clk_div7", "cpu_clk_div8" }; 96 97 static int 98 meson8b_clkc_pll_sys_set_rate(struct meson_clk_softc *sc, 99 struct meson_clk_clk *clk, u_int rate) 100 { 101 struct clk *clkp, *clkp_parent; 102 103 KASSERT(clk->type == MESON_CLK_PLL); 104 105 clkp = &clk->base; 106 clkp_parent = clk_get_parent(clkp); 107 if (clkp_parent == NULL) 108 return ENXIO; 109 110 const u_int old_rate = clk_get_rate(clkp); 111 if (old_rate == rate) 112 return 0; 113 114 const u_int parent_rate = clk_get_rate(clkp_parent); 115 if (parent_rate == 0) 116 return EIO; 117 118 uint32_t cntl0 = CLK_READ(sc, HHI_SYS_CPU_CLK_CNTL0); 119 uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL); 120 121 u_int new_mul = rate / parent_rate; 122 u_int new_div = 1; 123 u_int new_od = 0; 124 125 if (rate < 600 * 1000000) { 126 new_od = 2; 127 new_mul *= 4; 128 } else if (rate < 1200 * 1000000) { 129 new_od = 1; 130 new_mul *= 2; 131 } 132 133 if ((cntl0 & HHI_SYS_CPU_CLK_CNTL0_CLKSEL) == 0) 134 return EIO; 135 if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_PLLSEL) != 1) 136 return EIO; 137 if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_SOUTSEL) != 0) 138 return EIO; 139 140 cntl &= ~HHI_SYS_PLL_CNTL_MUL; 141 cntl |= __SHIFTIN(new_mul, HHI_SYS_PLL_CNTL_MUL); 142 cntl &= ~HHI_SYS_PLL_CNTL_DIV; 143 cntl |= __SHIFTIN(new_div, HHI_SYS_PLL_CNTL_DIV); 144 cntl &= ~HHI_SYS_PLL_CNTL_OD; 145 cntl |= __SHIFTIN(new_od, HHI_SYS_PLL_CNTL_OD); 146 147 /* Switch CPU to XTAL clock */ 148 cntl0 &= ~HHI_SYS_CPU_CLK_CNTL0_CLKSEL; 149 CLK_WRITE(sc, HHI_SYS_CPU_CLK_CNTL0, cntl0); 150 151 delay((100 * old_rate) / parent_rate); 152 153 /* Update multiplier */ 154 do { 155 CLK_WRITE(sc, HHI_SYS_PLL_CNTL, cntl); 156 157 /* Switch CPU to sys pll */ 158 cntl0 |= HHI_SYS_CPU_CLK_CNTL0_CLKSEL; 159 CLK_WRITE(sc, HHI_SYS_CPU_CLK_CNTL0, cntl0); 160 } while ((CLK_READ(sc, HHI_SYS_PLL_CNTL) & HHI_SYS_PLL_CNTL_LOCK) == 0); 161 162 return 0; 163 } 164 165 static struct meson_clk_clk meson8b_clkc_clks[] = { 166 167 MESON_CLK_FIXED(MESON8B_CLOCK_XTAL, "xtal", 24000000), 168 169 MESON_CLK_PLL_RATE(MESON8B_CLOCK_PLL_SYS_DCO, "pll_sys_dco", "xtal", 170 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */ 171 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */ 172 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */ 173 MESON_CLK_PLL_REG_INVALID, /* frac */ 174 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */ 175 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */ 176 meson8b_clkc_pll_sys_set_rate, 177 0), 178 179 MESON_CLK_DIV(MESON8B_CLOCK_PLL_SYS, "sys_pll", "pll_sys_dco", 180 HHI_SYS_PLL_CNTL, /* reg */ 181 __BITS(17,16), /* div */ 182 MESON_CLK_DIV_POWER_OF_TWO | MESON_CLK_DIV_SET_RATE_PARENT), 183 184 MESON_CLK_MUX(MESON8B_CLOCK_CPU_IN_SEL, "cpu_in_sel", cpu_in_sel_parents, 185 HHI_SYS_CPU_CLK_CNTL0, /* reg */ 186 __BIT(0), /* sel */ 187 0), 188 189 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV2, "cpu_in_div2", "cpu_in_sel", 2, 1), 190 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV3, "cpu_in_div3", "cpu_in_sel", 3, 1), 191 192 MESON_CLK_DIV(MESON8B_CLOCK_CPU_SCALE_DIV, "cpu_scale_div", "cpu_in_sel", 193 HHI_SYS_CPU_CLK_CNTL1, /* reg */ 194 __BITS(29,20), /* div */ 195 MESON_CLK_DIV_CPU_SCALE_TABLE | MESON_CLK_DIV_SET_RATE_PARENT), 196 197 MESON_CLK_MUX(MESON8B_CLOCK_CPU_SCALE_OUT_SEL, "cpu_scale_out_sel", cpu_scale_out_sel_parents, 198 HHI_SYS_CPU_CLK_CNTL0, /* reg */ 199 __BITS(3,2), /* sel */ 200 0), 201 202 MESON_CLK_MUX(MESON8B_CLOCK_CPUCLK, "cpu_clk", cpu_clk_parents, 203 HHI_SYS_CPU_CLK_CNTL0, /* reg */ 204 __BIT(7), /* sel */ 205 0), 206 207 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV2, "cpu_clk_div2", "cpu_clk", 2, 1), 208 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV3, "cpu_clk_div3", "cpu_clk", 3, 1), 209 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV4, "cpu_clk_div4", "cpu_clk", 4, 1), 210 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV5, "cpu_clk_div5", "cpu_clk", 5, 1), 211 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV6, "cpu_clk_div6", "cpu_clk", 6, 1), 212 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV7, "cpu_clk_div7", "cpu_clk", 7, 1), 213 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV8, "cpu_clk_div8", "cpu_clk", 8, 1), 214 215 MESON_CLK_MUX(MESON8B_CLOCK_PERIPH_SEL, "periph_clk_sel", periph_clk_sel_parents, 216 HHI_SYS_CPU_CLK_CNTL1, /* reg */ 217 __BITS(8,6), /* sel */ 218 0), 219 MESON_CLK_GATE_FLAGS(MESON8B_CLOCK_PERIPH, "periph_clk_dis", "periph_clk_sel", 220 HHI_SYS_CPU_CLK_CNTL1, /* reg */ 221 17, /* bit */ 222 MESON_CLK_GATE_SET_TO_DISABLE), 223 224 MESON_CLK_PLL(MESON8B_CLOCK_PLL_FIXED_DCO, "pll_fixed_dco", "xtal", 225 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */ 226 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */ 227 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */ 228 MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */ 229 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */ 230 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */ 231 0), 232 233 MESON_CLK_DIV(MESON8B_CLOCK_PLL_FIXED, "pll_fixed", "pll_fixed_dco", 234 HHI_MPLL_CNTL, /* reg */ 235 __BITS(17,16), /* div */ 236 MESON_CLK_DIV_POWER_OF_TWO), 237 238 MESON_CLK_DIV(MESON8B_CLOCK_MPLL_PREDIV, "mpll_prediv", "pll_fixed", 239 HHI_MPLL_CNTL5, /* reg */ 240 __BIT(12), /* div */ 241 0), 242 243 MESON_CLK_MPLL(MESON8B_CLOCK_MPLL0_DIV, "mpll0_div", "mpll_prediv", 244 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */ 245 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */ 246 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */ 247 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */ 248 0), 249 MESON_CLK_MPLL(MESON8B_CLOCK_MPLL1_DIV, "mpll1_div", "mpll_prediv", 250 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */ 251 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */ 252 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */ 253 MESON_CLK_PLL_REG_INVALID, /* ssen */ 254 0), 255 MESON_CLK_MPLL(MESON8B_CLOCK_MPLL2_DIV, "mpll2_div", "mpll_prediv", 256 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */ 257 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */ 258 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */ 259 MESON_CLK_PLL_REG_INVALID, /* ssen */ 260 0), 261 262 MESON_CLK_GATE(MESON8B_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14), 263 MESON_CLK_GATE(MESON8B_CLOCK_MPLL1, "mpll1", "mpll1_div", HHI_MPLL_CNTL8, 14), 264 MESON_CLK_GATE(MESON8B_CLOCK_MPLL2, "mpll2", "mpll2_div", HHI_MPLL_CNTL9, 14), 265 266 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV2_DIV, "fclk_div2_div", "pll_fixed", 2, 1), 267 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV3_DIV, "fclk_div3_div", "pll_fixed", 3, 1), 268 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV4_DIV, "fclk_div4_div", "pll_fixed", 4, 1), 269 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV5_DIV, "fclk_div5_div", "pll_fixed", 5, 1), 270 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV7_DIV, "fclk_div7_div", "pll_fixed", 7, 1), 271 272 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV2, "fclk_div2", "fclk_div2_div", HHI_MPLL_CNTL6, 27), 273 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV3, "fclk_div3", "fclk_div3_div", HHI_MPLL_CNTL6, 28), 274 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV4, "fclk_div4", "fclk_div4_div", HHI_MPLL_CNTL6, 29), 275 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV5, "fclk_div5", "fclk_div5_div", HHI_MPLL_CNTL6, 30), 276 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV7, "fclk_div7", "fclk_div7_div", HHI_MPLL_CNTL6, 31), 277 278 MESON_CLK_MUX(MESON8B_CLOCK_MPEG_SEL, "mpeg_sel", mpeg_sel_parents, 279 HHI_MPEG_CLK_CNTL, /* reg */ 280 __BITS(14,12), /* sel */ 281 0), 282 283 MESON_CLK_DIV(MESON8B_CLOCK_MPEG_DIV, "mpeg_div", "mpeg_sel", 284 HHI_MPEG_CLK_CNTL, /* reg */ 285 __BITS(6,0), /* div */ 286 0), 287 288 MESON_CLK_GATE(MESON8B_CLOCK_CLK81, "clk81", "mpeg_div", HHI_MPEG_CLK_CNTL, 7), 289 290 MESON_CLK_GATE(MESON8B_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9), 291 MESON_CLK_GATE(MESON8B_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10), 292 MESON_CLK_GATE(MESON8B_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12), 293 MESON_CLK_GATE(MESON8B_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13), 294 MESON_CLK_GATE(MESON8B_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14), 295 MESON_CLK_GATE(MESON8B_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17), 296 297 MESON_CLK_GATE(MESON8B_CLOCK_ETH, "eth", "clk81", HHI_GCLK_MPEG1, 3), 298 MESON_CLK_GATE(MESON8B_CLOCK_UART1, "uart1", "clk81", HHI_GCLK_MPEG1, 16), 299 MESON_CLK_GATE(MESON8B_CLOCK_USB0, "usb0", "clk81", HHI_GCLK_MPEG1, 21), 300 MESON_CLK_GATE(MESON8B_CLOCK_USB1, "usb1", "clk81", HHI_GCLK_MPEG1, 22), 301 MESON_CLK_GATE(MESON8B_CLOCK_USB, "usb", "clk81", HHI_GCLK_MPEG1, 26), 302 MESON_CLK_GATE(MESON8B_CLOCK_EFUSE, "efuse", "clk81", HHI_GCLK_MPEG1, 30), 303 304 MESON_CLK_GATE(MESON8B_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 8), 305 MESON_CLK_GATE(MESON8B_CLOCK_USB0_DDR_BRIDGE, "usb0_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 9), 306 MESON_CLK_GATE(MESON8B_CLOCK_UART2, "uart2", "clk81", HHI_GCLK_MPEG2, 15), 307 }; 308 309 static int 310 meson8b_clkc_match(device_t parent, cfdata_t cf, void *aux) 311 { 312 struct fdt_attach_args * const faa = aux; 313 314 return of_match_compatible(faa->faa_phandle, compatible); 315 } 316 317 static void 318 meson8b_clkc_attach(device_t parent, device_t self, void *aux) 319 { 320 struct meson_clk_softc * const sc = device_private(self); 321 struct fdt_attach_args * const faa = aux; 322 323 sc->sc_dev = self; 324 sc->sc_phandle = faa->faa_phandle; 325 sc->sc_bst = faa->faa_bst; 326 327 sc->sc_resets = meson8b_clkc_resets; 328 sc->sc_nresets = __arraycount(meson8b_clkc_resets); 329 330 sc->sc_clks = meson8b_clkc_clks; 331 sc->sc_nclks = __arraycount(meson8b_clkc_clks); 332 333 if (meson_clk_attach(sc, MESON8B_CLKC_REG_INDEX) != 0) 334 return; 335 336 aprint_naive("\n"); 337 aprint_normal(": Meson8b clock controller\n"); 338 339 meson_clk_print(sc); 340 } 341
Indexes created Tue Sep 30 20:09:53 GMT 2025