meson8b_clkc.c revision 1.3.4.2
1 /* $NetBSD: meson8b_clkc.c,v 1.3.4.2 2019/06/10 22:05:51 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: meson8b_clkc.c,v 1.3.4.2 2019/06/10 22:05:51 christos Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/amlogic/meson_clk.h> 41 #include <arm/amlogic/meson8b_clkc.h> 42 43 /* 44 * The DT for amlogic,meson8b-clkc defines two reg resources. The first 45 * is not used by this driver. 46 */ 47 #define MESON8B_CLKC_REG_INDEX 1 48 49 #define CBUS_REG(x) ((x) << 2) 50 51 #define HHI_GCLK_MPEG0 CBUS_REG(0x50) 52 #define HHI_GCLK_MPEG1 CBUS_REG(0x51) 53 #define HHI_GCLK_MPEG2 CBUS_REG(0x52) 54 #define HHI_SYS_CPU_CLK_CNTL1 CBUS_REG(0x57) 55 #define HHI_MPEG_CLK_CNTL CBUS_REG(0x5d) 56 #define HHI_SYS_CPU_CLK_CNTL0 CBUS_REG(0x67) 57 #define HHI_SYS_CPU_CLK_CNTL0_CLKSEL __BIT(7) 58 #define HHI_SYS_CPU_CLK_CNTL0_SOUTSEL __BITS(3,2) 59 #define HHI_SYS_CPU_CLK_CNTL0_PLLSEL __BITS(1,0) 60 #define HHI_MPLL_CNTL CBUS_REG(0xa0) 61 #define HHI_MPLL_CNTL2 CBUS_REG(0xa1) 62 #define HHI_MPLL_CNTL5 CBUS_REG(0xa4) 63 #define HHI_MPLL_CNTL6 CBUS_REG(0xa5) 64 #define HHI_MPLL_CNTL7 CBUS_REG(0xa6) 65 #define HHI_MPLL_CNTL8 CBUS_REG(0xa7) 66 #define HHI_MPLL_CNTL9 CBUS_REG(0xa8) 67 #define HHI_SYS_PLL_CNTL CBUS_REG(0xc0) 68 #define HHI_SYS_PLL_CNTL_LOCK __BIT(31) 69 #define HHI_SYS_PLL_CNTL_OD __BITS(17,16) 70 #define HHI_SYS_PLL_CNTL_DIV __BITS(14,9) 71 #define HHI_SYS_PLL_CNTL_MUL __BITS(8,0) 72 73 static int meson8b_clkc_match(device_t, cfdata_t, void *); 74 static void meson8b_clkc_attach(device_t, device_t, void *); 75 76 static const char * const compatible[] = { 77 "amlogic,meson8b-clkc", 78 NULL 79 }; 80 81 CFATTACH_DECL_NEW(meson8b_clkc, sizeof(struct meson_clk_softc), 82 meson8b_clkc_match, meson8b_clkc_attach, NULL, NULL); 83 84 static struct meson_clk_reset meson8b_clkc_resets[] = { 85 MESON_CLK_RESET(MESON8B_RESET_CPU0_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 24), 86 MESON_CLK_RESET(MESON8B_RESET_CPU1_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 25), 87 MESON_CLK_RESET(MESON8B_RESET_CPU2_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 26), 88 MESON_CLK_RESET(MESON8B_RESET_CPU3_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 27), 89 }; 90 91 static const char *mpeg_sel_parents[] = { "xtal", NULL, "fclk_div7", "mpll_clkout1", "mpll_clkout2", "fclk_div4", "fclk_div3", "fclk_div5" }; 92 static const char *cpu_in_sel_parents[] = { "xtal", "sys_pll" }; 93 static const char *cpu_scale_out_sel_parents[] = { "cpu_in_sel", "cpu_in_div2", "cpu_in_div3", "cpu_scale_div" }; 94 static const char *cpu_clk_parents[] = { "xtal", "cpu_scale_out_sel" }; 95 static const char *periph_clk_sel_parents[] = { "cpu_clk_div2", "cpu_clk_div3", "cpu_clk_div4", "cpu_clk_div5", "cpu_clk_div6", "cpu_clk_div7", "cpu_clk_div8" }; 96 97 static int 98 meson8b_clkc_pll_sys_set_rate(struct meson_clk_softc *sc, 99 struct meson_clk_clk *clk, u_int rate) 100 { 101 struct clk *clkp, *clkp_parent; 102 int error; 103 104 KASSERT(clk->type == MESON_CLK_PLL); 105 106 clkp = &clk->base; 107 clkp_parent = clk_get_parent(clkp); 108 if (clkp_parent == NULL) 109 return ENXIO; 110 111 const u_int old_rate = clk_get_rate(clkp); 112 if (old_rate == rate) 113 return 0; 114 115 const u_int parent_rate = clk_get_rate(clkp_parent); 116 if (parent_rate == 0) 117 return EIO; 118 119 CLK_LOCK(sc); 120 121 uint32_t cntl0 = CLK_READ(sc, HHI_SYS_CPU_CLK_CNTL0); 122 uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL); 123 124 u_int new_mul = rate / parent_rate; 125 u_int new_div = 1; 126 u_int new_od = 0; 127 128 if (rate < 600 * 1000000) { 129 new_od = 2; 130 new_mul *= 4; 131 } else if (rate < 1200 * 1000000) { 132 new_od = 1; 133 new_mul *= 2; 134 } 135 136 if ((cntl0 & HHI_SYS_CPU_CLK_CNTL0_CLKSEL) == 0) { 137 error = EIO; 138 goto done; 139 } 140 if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_PLLSEL) != 1) { 141 error = EIO; 142 goto done; 143 } 144 if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_SOUTSEL) != 0) { 145 error = EIO; 146 goto done; 147 } 148 149 cntl &= ~HHI_SYS_PLL_CNTL_MUL; 150 cntl |= __SHIFTIN(new_mul, HHI_SYS_PLL_CNTL_MUL); 151 cntl &= ~HHI_SYS_PLL_CNTL_DIV; 152 cntl |= __SHIFTIN(new_div, HHI_SYS_PLL_CNTL_DIV); 153 cntl &= ~HHI_SYS_PLL_CNTL_OD; 154 cntl |= __SHIFTIN(new_od, HHI_SYS_PLL_CNTL_OD); 155 156 /* Switch CPU to XTAL clock */ 157 cntl0 &= ~HHI_SYS_CPU_CLK_CNTL0_CLKSEL; 158 CLK_WRITE(sc, HHI_SYS_CPU_CLK_CNTL0, cntl0); 159 160 delay((100 * old_rate) / parent_rate); 161 162 /* Update multiplier */ 163 do { 164 CLK_WRITE(sc, HHI_SYS_PLL_CNTL, cntl); 165 166 /* Switch CPU to sys pll */ 167 cntl0 |= HHI_SYS_CPU_CLK_CNTL0_CLKSEL; 168 CLK_WRITE(sc, HHI_SYS_CPU_CLK_CNTL0, cntl0); 169 } while ((CLK_READ(sc, HHI_SYS_PLL_CNTL) & HHI_SYS_PLL_CNTL_LOCK) == 0); 170 171 error = 0; 172 173 done: 174 CLK_UNLOCK(sc); 175 176 return error; 177 } 178 179 static struct meson_clk_clk meson8b_clkc_clks[] = { 180 181 MESON_CLK_FIXED(MESON8B_CLOCK_XTAL, "xtal", 24000000), 182 183 MESON_CLK_PLL_RATE(MESON8B_CLOCK_PLL_SYS_DCO, "pll_sys_dco", "xtal", 184 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */ 185 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */ 186 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */ 187 MESON_CLK_PLL_REG_INVALID, /* frac */ 188 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */ 189 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */ 190 meson8b_clkc_pll_sys_set_rate, 191 0), 192 193 MESON_CLK_DIV(MESON8B_CLOCK_PLL_SYS, "sys_pll", "pll_sys_dco", 194 HHI_SYS_PLL_CNTL, /* reg */ 195 __BITS(17,16), /* div */ 196 MESON_CLK_DIV_POWER_OF_TWO | MESON_CLK_DIV_SET_RATE_PARENT), 197 198 MESON_CLK_MUX(MESON8B_CLOCK_CPU_IN_SEL, "cpu_in_sel", cpu_in_sel_parents, 199 HHI_SYS_CPU_CLK_CNTL0, /* reg */ 200 __BIT(0), /* sel */ 201 0), 202 203 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV2, "cpu_in_div2", "cpu_in_sel", 2, 1), 204 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV3, "cpu_in_div3", "cpu_in_sel", 3, 1), 205 206 MESON_CLK_DIV(MESON8B_CLOCK_CPU_SCALE_DIV, "cpu_scale_div", "cpu_in_sel", 207 HHI_SYS_CPU_CLK_CNTL1, /* reg */ 208 __BITS(29,20), /* div */ 209 MESON_CLK_DIV_CPU_SCALE_TABLE | MESON_CLK_DIV_SET_RATE_PARENT), 210 211 MESON_CLK_MUX(MESON8B_CLOCK_CPU_SCALE_OUT_SEL, "cpu_scale_out_sel", cpu_scale_out_sel_parents, 212 HHI_SYS_CPU_CLK_CNTL0, /* reg */ 213 __BITS(3,2), /* sel */ 214 0), 215 216 MESON_CLK_MUX(MESON8B_CLOCK_CPUCLK, "cpu_clk", cpu_clk_parents, 217 HHI_SYS_CPU_CLK_CNTL0, /* reg */ 218 __BIT(7), /* sel */ 219 0), 220 221 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV2, "cpu_clk_div2", "cpu_clk", 2, 1), 222 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV3, "cpu_clk_div3", "cpu_clk", 3, 1), 223 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV4, "cpu_clk_div4", "cpu_clk", 4, 1), 224 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV5, "cpu_clk_div5", "cpu_clk", 5, 1), 225 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV6, "cpu_clk_div6", "cpu_clk", 6, 1), 226 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV7, "cpu_clk_div7", "cpu_clk", 7, 1), 227 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV8, "cpu_clk_div8", "cpu_clk", 8, 1), 228 229 MESON_CLK_MUX(MESON8B_CLOCK_PERIPH_SEL, "periph_clk_sel", periph_clk_sel_parents, 230 HHI_SYS_CPU_CLK_CNTL1, /* reg */ 231 __BITS(8,6), /* sel */ 232 0), 233 MESON_CLK_GATE_FLAGS(MESON8B_CLOCK_PERIPH, "periph_clk_dis", "periph_clk_sel", 234 HHI_SYS_CPU_CLK_CNTL1, /* reg */ 235 17, /* bit */ 236 MESON_CLK_GATE_SET_TO_DISABLE), 237 238 MESON_CLK_PLL(MESON8B_CLOCK_PLL_FIXED_DCO, "pll_fixed_dco", "xtal", 239 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */ 240 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */ 241 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */ 242 MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */ 243 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */ 244 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */ 245 0), 246 247 MESON_CLK_DIV(MESON8B_CLOCK_PLL_FIXED, "pll_fixed", "pll_fixed_dco", 248 HHI_MPLL_CNTL, /* reg */ 249 __BITS(17,16), /* div */ 250 MESON_CLK_DIV_POWER_OF_TWO), 251 252 MESON_CLK_DIV(MESON8B_CLOCK_MPLL_PREDIV, "mpll_prediv", "pll_fixed", 253 HHI_MPLL_CNTL5, /* reg */ 254 __BIT(12), /* div */ 255 0), 256 257 MESON_CLK_MPLL(MESON8B_CLOCK_MPLL0_DIV, "mpll0_div", "mpll_prediv", 258 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */ 259 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */ 260 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */ 261 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */ 262 0), 263 MESON_CLK_MPLL(MESON8B_CLOCK_MPLL1_DIV, "mpll1_div", "mpll_prediv", 264 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */ 265 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */ 266 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */ 267 MESON_CLK_PLL_REG_INVALID, /* ssen */ 268 0), 269 MESON_CLK_MPLL(MESON8B_CLOCK_MPLL2_DIV, "mpll2_div", "mpll_prediv", 270 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */ 271 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */ 272 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */ 273 MESON_CLK_PLL_REG_INVALID, /* ssen */ 274 0), 275 276 MESON_CLK_GATE(MESON8B_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14), 277 MESON_CLK_GATE(MESON8B_CLOCK_MPLL1, "mpll1", "mpll1_div", HHI_MPLL_CNTL8, 14), 278 MESON_CLK_GATE(MESON8B_CLOCK_MPLL2, "mpll2", "mpll2_div", HHI_MPLL_CNTL9, 14), 279 280 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV2_DIV, "fclk_div2_div", "pll_fixed", 2, 1), 281 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV3_DIV, "fclk_div3_div", "pll_fixed", 3, 1), 282 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV4_DIV, "fclk_div4_div", "pll_fixed", 4, 1), 283 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV5_DIV, "fclk_div5_div", "pll_fixed", 5, 1), 284 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV7_DIV, "fclk_div7_div", "pll_fixed", 7, 1), 285 286 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV2, "fclk_div2", "fclk_div2_div", HHI_MPLL_CNTL6, 27), 287 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV3, "fclk_div3", "fclk_div3_div", HHI_MPLL_CNTL6, 28), 288 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV4, "fclk_div4", "fclk_div4_div", HHI_MPLL_CNTL6, 29), 289 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV5, "fclk_div5", "fclk_div5_div", HHI_MPLL_CNTL6, 30), 290 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV7, "fclk_div7", "fclk_div7_div", HHI_MPLL_CNTL6, 31), 291 292 MESON_CLK_MUX(MESON8B_CLOCK_MPEG_SEL, "mpeg_sel", mpeg_sel_parents, 293 HHI_MPEG_CLK_CNTL, /* reg */ 294 __BITS(14,12), /* sel */ 295 0), 296 297 MESON_CLK_DIV(MESON8B_CLOCK_MPEG_DIV, "mpeg_div", "mpeg_sel", 298 HHI_MPEG_CLK_CNTL, /* reg */ 299 __BITS(6,0), /* div */ 300 0), 301 302 MESON_CLK_GATE(MESON8B_CLOCK_CLK81, "clk81", "mpeg_div", HHI_MPEG_CLK_CNTL, 7), 303 304 MESON_CLK_GATE(MESON8B_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9), 305 MESON_CLK_GATE(MESON8B_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10), 306 MESON_CLK_GATE(MESON8B_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12), 307 MESON_CLK_GATE(MESON8B_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13), 308 MESON_CLK_GATE(MESON8B_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14), 309 MESON_CLK_GATE(MESON8B_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17), 310 311 MESON_CLK_GATE(MESON8B_CLOCK_ETH, "eth", "clk81", HHI_GCLK_MPEG1, 3), 312 MESON_CLK_GATE(MESON8B_CLOCK_UART1, "uart1", "clk81", HHI_GCLK_MPEG1, 16), 313 MESON_CLK_GATE(MESON8B_CLOCK_USB0, "usb0", "clk81", HHI_GCLK_MPEG1, 21), 314 MESON_CLK_GATE(MESON8B_CLOCK_USB1, "usb1", "clk81", HHI_GCLK_MPEG1, 22), 315 MESON_CLK_GATE(MESON8B_CLOCK_USB, "usb", "clk81", HHI_GCLK_MPEG1, 26), 316 MESON_CLK_GATE(MESON8B_CLOCK_EFUSE, "efuse", "clk81", HHI_GCLK_MPEG1, 30), 317 318 MESON_CLK_GATE(MESON8B_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 8), 319 MESON_CLK_GATE(MESON8B_CLOCK_USB0_DDR_BRIDGE, "usb0_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 9), 320 MESON_CLK_GATE(MESON8B_CLOCK_UART2, "uart2", "clk81", HHI_GCLK_MPEG2, 15), 321 }; 322 323 static int 324 meson8b_clkc_match(device_t parent, cfdata_t cf, void *aux) 325 { 326 struct fdt_attach_args * const faa = aux; 327 328 return of_match_compatible(faa->faa_phandle, compatible); 329 } 330 331 static void 332 meson8b_clkc_attach(device_t parent, device_t self, void *aux) 333 { 334 struct meson_clk_softc * const sc = device_private(self); 335 struct fdt_attach_args * const faa = aux; 336 bus_addr_t addr; 337 bus_size_t size; 338 339 sc->sc_dev = self; 340 sc->sc_phandle = faa->faa_phandle; 341 sc->sc_bst = faa->faa_bst; 342 if (fdtbus_get_reg(sc->sc_phandle, MESON8B_CLKC_REG_INDEX, &addr, &size) != 0) { 343 aprint_error(": couldn't get registers\n"); 344 return; 345 } 346 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 347 aprint_error(": couldn't map registers\n"); 348 return; 349 } 350 351 sc->sc_resets = meson8b_clkc_resets; 352 sc->sc_nresets = __arraycount(meson8b_clkc_resets); 353 354 sc->sc_clks = meson8b_clkc_clks; 355 sc->sc_nclks = __arraycount(meson8b_clkc_clks); 356 357 meson_clk_attach(sc); 358 359 aprint_naive("\n"); 360 aprint_normal(": Meson8b clock controller\n"); 361 362 meson_clk_print(sc); 363 } 364
Indexes created Tue Sep 30 20:09:53 GMT 2025