meson_dwmac.c revision 1.13
1 /* $NetBSD: meson_dwmac.c,v 1.13 2021/11/17 11:57:27 jdc Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.13 2021/11/17 11:57:27 jdc Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #define PRG_ETHERNET_ADDR0 0x00 53 #define CLKGEN_ENABLE __BIT(12) 54 #define RMII_CLK_I_INVERTED __BIT(11) 55 #define PHY_CLK_ENABLE __BIT(10) 56 #define MP2_CLK_OUT_DIV __BITS(9,7) 57 #define TX_CLK_DELAY __BITS(6,5) 58 #define PHY_INTERFACE_SEL __BIT(0) 59 60 static const struct device_compatible_entry compat_data[] = { 61 { .compat = "amlogic,meson8b-dwmac" }, 62 { .compat = "amlogic,meson-gx-dwmac" }, 63 { .compat = "amlogic,meson-gxbb-dwmac" }, 64 { .compat = "amlogic,meson-axg-dwmac" }, 65 DEVICE_COMPAT_EOL 66 }; 67 68 static int 69 meson_dwmac_reset(const int phandle) 70 { 71 struct fdtbus_gpio_pin *pin_reset; 72 const u_int *reset_delay_us; 73 const u_int *reset_assert_us, *reset_deassert_us, *reset_gpios; 74 bool reset_active_low; 75 int len, val; 76 77 /* 78 * Depending on the DTS, we need to check either the "snps,...", 79 * or the "reset-..." properties for the MAC reset information. 80 */ 81 82 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", 83 GPIO_PIN_OUTPUT); 84 if (pin_reset != NULL) { 85 86 reset_delay_us = fdtbus_get_prop(phandle, 87 "snps,reset-delays-us", &len); 88 if (reset_delay_us == NULL || len != 12) 89 return ENXIO; 90 91 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 92 93 val = reset_active_low ? 1 : 0; 94 95 fdtbus_gpio_write(pin_reset, val); 96 delay(be32toh(reset_delay_us[0])); 97 fdtbus_gpio_write(pin_reset, !val); 98 delay(be32toh(reset_delay_us[1])); 99 fdtbus_gpio_write(pin_reset, val); 100 delay(be32toh(reset_delay_us[2])); 101 102 return 0; 103 } 104 105 pin_reset = fdtbus_gpio_acquire(phandle, "reset-gpios", 106 GPIO_PIN_OUTPUT); 107 if (pin_reset != NULL) { 108 reset_assert_us = fdtbus_get_prop(phandle, 109 "reset-assert-us", &len); 110 if (reset_assert_us == NULL || len != 4) 111 return ENXIO; 112 reset_deassert_us = fdtbus_get_prop(phandle, 113 "reset-deassert-us", &len); 114 if (reset_deassert_us == NULL || len != 4) 115 return ENXIO; 116 reset_gpios = fdtbus_get_prop(phandle, 117 "reset-gpios", &len); 118 if (reset_gpios == NULL || len != 12) 119 return ENXIO; 120 121 reset_active_low = be32toh(reset_gpios[2]); 122 123 val = reset_active_low ? 1 : 0; 124 125 126 fdtbus_gpio_write(pin_reset, val); 127 delay(be32toh(reset_assert_us[0])); 128 fdtbus_gpio_write(pin_reset, !val); 129 delay(be32toh(reset_deassert_us[0])); 130 131 return 0; 132 } 133 134 return ENXIO; 135 } 136 137 static void 138 meson_dwmac_set_mode_rgmii(int phandle, bus_space_tag_t bst, 139 bus_space_handle_t bsh, struct clk *clkin) 140 { 141 u_int tx_delay; 142 uint32_t val; 143 144 #define DIV_ROUND_OFF(x, y) (((x) + (y) / 2) / (y)) 145 const u_int div = DIV_ROUND_OFF(clk_get_rate(clkin), 250000000); 146 147 if (of_getprop_uint32(phandle, "amlogic,tx-delay-ns", &tx_delay) != 0) 148 tx_delay = 2; 149 150 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 151 val |= PHY_INTERFACE_SEL; 152 val &= ~TX_CLK_DELAY; 153 val |= __SHIFTIN((tx_delay >> 1), TX_CLK_DELAY); 154 val &= ~MP2_CLK_OUT_DIV; 155 val |= __SHIFTIN(div, MP2_CLK_OUT_DIV); 156 val |= PHY_CLK_ENABLE; 157 val |= CLKGEN_ENABLE; 158 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 159 } 160 161 static void 162 meson_dwmac_set_mode_rmii(int phandle, bus_space_tag_t bst, 163 bus_space_handle_t bsh) 164 { 165 uint32_t val; 166 167 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 168 val &= ~PHY_INTERFACE_SEL; 169 val |= RMII_CLK_I_INVERTED; 170 val &= ~TX_CLK_DELAY; 171 val |= CLKGEN_ENABLE; 172 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 173 } 174 175 static int 176 meson_dwmac_intr(void *arg) 177 { 178 struct dwc_gmac_softc * const sc = arg; 179 180 return dwc_gmac_intr(sc); 181 } 182 183 static int 184 meson_dwmac_match(device_t parent, cfdata_t cf, void *aux) 185 { 186 struct fdt_attach_args * const faa = aux; 187 188 return of_compatible_match(faa->faa_phandle, compat_data); 189 } 190 191 static void 192 meson_dwmac_attach(device_t parent, device_t self, void *aux) 193 { 194 struct dwc_gmac_softc * const sc = device_private(self); 195 struct fdt_attach_args * const faa = aux; 196 const int phandle = faa->faa_phandle; 197 int miiclk, phandle_phy, phy = MII_PHY_ANY; 198 u_int miiclk_rate; 199 bus_space_handle_t prgeth_bsh; 200 struct fdtbus_reset *rst_gmac; 201 struct clk *clk_gmac, *clk_in[2]; 202 const char *phy_mode; 203 char intrstr[128]; 204 bus_addr_t addr[2]; 205 bus_size_t size[2]; 206 207 if (fdtbus_get_reg(phandle, 0, &addr[0], &size[0]) != 0 || 208 fdtbus_get_reg(phandle, 1, &addr[1], &size[1]) != 0) { 209 aprint_error(": couldn't get registers\n"); 210 return; 211 } 212 213 sc->sc_dev = self; 214 sc->sc_bst = faa->faa_bst; 215 if (bus_space_map(sc->sc_bst, addr[0], size[0], 0, &sc->sc_bsh) != 0 || 216 bus_space_map(sc->sc_bst, addr[1], size[1], 0, &prgeth_bsh) != 0) { 217 aprint_error(": couldn't map registers\n"); 218 return; 219 } 220 sc->sc_dmat = faa->faa_dmat; 221 222 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 223 aprint_error(": failed to decode interrupt\n"); 224 return; 225 } 226 227 clk_gmac = fdtbus_clock_get(phandle, "stmmaceth"); 228 clk_in[0] = fdtbus_clock_get(phandle, "clkin0"); 229 clk_in[1] = fdtbus_clock_get(phandle, "clkin1"); 230 if (clk_gmac == NULL || clk_in[0] == NULL || clk_in[1] == NULL) { 231 aprint_error(": couldn't get clocks\n"); 232 return; 233 } 234 235 rst_gmac = fdtbus_reset_get(phandle, "stmmaceth"); 236 237 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 238 if (phy_mode == NULL) { 239 aprint_error(": missing 'phy-mode' property\n"); 240 return; 241 } 242 phandle_phy = fdtbus_get_phandle(phandle, "phy-handle"); 243 if (phandle_phy > 0) { 244 of_getprop_uint32(phandle_phy, "reg", &phy); 245 } else { 246 phandle_phy = phandle; 247 } 248 249 if (strncmp(phy_mode, "rgmii", 5) == 0) { 250 meson_dwmac_set_mode_rgmii(phandle, sc->sc_bst, prgeth_bsh, clk_in[0]); 251 } else if (strcmp(phy_mode, "rmii") == 0) { 252 meson_dwmac_set_mode_rmii(phandle, sc->sc_bst, prgeth_bsh); 253 } else { 254 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 255 return; 256 } 257 258 if (clk_enable(clk_gmac) != 0) { 259 aprint_error(": couldn't enable clock\n"); 260 return; 261 } 262 263 if (rst_gmac != NULL && fdtbus_reset_deassert(rst_gmac) != 0) { 264 aprint_error(": couldn't de-assert reset\n"); 265 return; 266 } 267 268 aprint_naive("\n"); 269 aprint_normal(": Gigabit Ethernet Controller\n"); 270 271 if (fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 272 DWCGMAC_FDT_INTR_MPSAFE, meson_dwmac_intr, sc, 273 device_xname(sc->sc_dev)) == NULL) { 274 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 275 return; 276 } 277 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 278 279 if (meson_dwmac_reset(phandle_phy) != 0) 280 aprint_error_dev(self, "PHY reset failed\n"); 281 282 miiclk_rate = clk_get_rate(clk_gmac); 283 if (miiclk_rate > 250 * 1000 * 1000) 284 miiclk = GMAC_MII_CLK_250_300M_DIV124; 285 else if (miiclk_rate > 150 * 1000 * 1000) 286 miiclk = GMAC_MII_CLK_150_250M_DIV102; 287 else if (miiclk_rate > 100 * 1000 * 1000) 288 miiclk = GMAC_MII_CLK_100_150M_DIV62; 289 else if (miiclk_rate > 60 * 1000 * 1000) 290 miiclk = GMAC_MII_CLK_60_100M_DIV42; 291 else if (miiclk_rate > 35 * 1000 * 1000) 292 miiclk = GMAC_MII_CLK_35_60M_DIV26; 293 else 294 miiclk = GMAC_MII_CLK_25_35M_DIV16; 295 296 dwc_gmac_attach(sc, phy, miiclk); 297 } 298 299 CFATTACH_DECL_NEW(meson_dwmac, sizeof(struct dwc_gmac_softc), 300 meson_dwmac_match, meson_dwmac_attach, NULL, NULL); 301
Indexes created Wed Oct 01 18:09:54 GMT 2025