meson_dwmac.c revision 1.5.4.2
1 /* $NetBSD: meson_dwmac.c,v 1.5.4.2 2019/06/10 22:05:51 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.5.4.2 2019/06/10 22:05:51 christos Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 40 #include <net/if.h> 41 #include <net/if_ether.h> 42 #include <net/if_media.h> 43 44 #include <dev/mii/miivar.h> 45 46 #include <dev/ic/dwc_gmac_var.h> 47 #include <dev/ic/dwc_gmac_reg.h> 48 49 #include <dev/fdt/fdtvar.h> 50 51 #define PRG_ETHERNET_ADDR0 0x00 52 #define CLKGEN_ENABLE __BIT(12) 53 #define RMII_CLK_I_INVERTED __BIT(11) 54 #define PHY_CLK_ENABLE __BIT(10) 55 #define MP2_CLK_OUT_DIV __BITS(9,7) 56 #define TX_CLK_DELAY __BITS(6,5) 57 #define PHY_INTERFACE_SEL __BIT(0) 58 59 static const char * compatible[] = { 60 "amlogic,meson8b-dwmac", 61 "amlogic,meson-gx-dwmac", 62 NULL 63 }; 64 65 static int 66 meson_dwmac_reset(const int phandle) 67 { 68 struct fdtbus_gpio_pin *pin_reset; 69 const u_int *reset_delay_us; 70 bool reset_active_low; 71 int len, val; 72 73 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 74 if (pin_reset == NULL) 75 return 0; 76 77 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 78 if (reset_delay_us == NULL || len != 12) 79 return ENXIO; 80 81 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 82 83 val = reset_active_low ? 1 : 0; 84 85 fdtbus_gpio_write(pin_reset, val); 86 delay(be32toh(reset_delay_us[0])); 87 fdtbus_gpio_write(pin_reset, !val); 88 delay(be32toh(reset_delay_us[1])); 89 fdtbus_gpio_write(pin_reset, val); 90 delay(be32toh(reset_delay_us[2])); 91 92 return 0; 93 } 94 95 static void 96 meson_dwmac_set_mode_rgmii(int phandle, bus_space_tag_t bst, 97 bus_space_handle_t bsh, struct clk *clkin) 98 { 99 u_int tx_delay; 100 uint32_t val; 101 102 const u_int div = clk_get_rate(clkin) / 250000000; 103 104 if (of_getprop_uint32(phandle, "amlogic,tx-delay-ns", &tx_delay) != 0) 105 tx_delay = 2; 106 107 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 108 val |= PHY_INTERFACE_SEL; 109 val &= ~TX_CLK_DELAY; 110 val |= __SHIFTIN((tx_delay >> 1), TX_CLK_DELAY); 111 val &= ~MP2_CLK_OUT_DIV; 112 val |= __SHIFTIN(div, MP2_CLK_OUT_DIV); 113 val |= PHY_CLK_ENABLE; 114 val |= CLKGEN_ENABLE; 115 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 116 } 117 118 static void 119 meson_dwmac_set_mode_rmii(int phandle, bus_space_tag_t bst, 120 bus_space_handle_t bsh) 121 { 122 uint32_t val; 123 124 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 125 val &= ~PHY_INTERFACE_SEL; 126 val |= RMII_CLK_I_INVERTED; 127 val &= ~TX_CLK_DELAY; 128 val |= CLKGEN_ENABLE; 129 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 130 } 131 132 static int 133 meson_dwmac_intr(void *arg) 134 { 135 struct dwc_gmac_softc * const sc = arg; 136 137 return dwc_gmac_intr(sc); 138 } 139 140 static int 141 meson_dwmac_match(device_t parent, cfdata_t cf, void *aux) 142 { 143 struct fdt_attach_args * const faa = aux; 144 145 return of_match_compatible(faa->faa_phandle, compatible); 146 } 147 148 static void 149 meson_dwmac_attach(device_t parent, device_t self, void *aux) 150 { 151 struct dwc_gmac_softc * const sc = device_private(self); 152 struct fdt_attach_args * const faa = aux; 153 const int phandle = faa->faa_phandle; 154 bus_space_handle_t prgeth_bsh; 155 struct fdtbus_reset *rst_gmac; 156 struct clk *clk_gmac, *clk_in[2]; 157 const char *phy_mode; 158 char intrstr[128]; 159 bus_addr_t addr[2]; 160 bus_size_t size[2]; 161 162 if (fdtbus_get_reg(phandle, 0, &addr[0], &size[0]) != 0 || 163 fdtbus_get_reg(phandle, 1, &addr[1], &size[1]) != 0) { 164 aprint_error(": couldn't get registers\n"); 165 return; 166 } 167 168 sc->sc_dev = self; 169 sc->sc_bst = faa->faa_bst; 170 if (bus_space_map(sc->sc_bst, addr[0], size[0], 0, &sc->sc_bsh) != 0 || 171 bus_space_map(sc->sc_bst, addr[1], size[1], 0, &prgeth_bsh) != 0) { 172 aprint_error(": couldn't map registers\n"); 173 return; 174 } 175 sc->sc_dmat = faa->faa_dmat; 176 177 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 178 aprint_error(": failed to decode interrupt\n"); 179 return; 180 } 181 182 clk_gmac = fdtbus_clock_get(phandle, "stmmaceth"); 183 clk_in[0] = fdtbus_clock_get(phandle, "clkin0"); 184 clk_in[1] = fdtbus_clock_get(phandle, "clkin1"); 185 if (clk_gmac == NULL || clk_in[0] == NULL || clk_in[1] == NULL) { 186 aprint_error(": couldn't get clocks\n"); 187 return; 188 } 189 190 rst_gmac = fdtbus_reset_get(phandle, "stmmaceth"); 191 192 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 193 if (phy_mode == NULL) { 194 aprint_error(": missing 'phy-mode' property\n"); 195 return; 196 } 197 198 if (strcmp(phy_mode, "rgmii") == 0) { 199 meson_dwmac_set_mode_rgmii(phandle, sc->sc_bst, prgeth_bsh, clk_in[0]); 200 } else if (strcmp(phy_mode, "rmii") == 0) { 201 meson_dwmac_set_mode_rmii(phandle, sc->sc_bst, prgeth_bsh); 202 } else { 203 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 204 return; 205 } 206 207 if (clk_enable(clk_gmac) != 0) { 208 aprint_error(": couldn't enable clock\n"); 209 return; 210 } 211 212 if (rst_gmac != NULL && fdtbus_reset_deassert(rst_gmac) != 0) { 213 aprint_error(": couldn't de-assert reset\n"); 214 return; 215 } 216 217 aprint_naive("\n"); 218 aprint_normal(": Gigabit Ethernet Controller\n"); 219 220 if (fdtbus_intr_establish(phandle, 0, IPL_NET, 0, meson_dwmac_intr, sc) == NULL) { 221 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 222 return; 223 } 224 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 225 226 if (meson_dwmac_reset(phandle) != 0) 227 aprint_error_dev(self, "PHY reset failed\n"); 228 229 dwc_gmac_attach(sc, MII_PHY_ANY, GMAC_MII_CLK_100_150M_DIV62); 230 } 231 232 CFATTACH_DECL_NEW(meson_dwmac, sizeof(struct dwc_gmac_softc), 233 meson_dwmac_match, meson_dwmac_attach, NULL, NULL); 234
Indexes created Fri Oct 03 02:09:57 GMT 2025