meson_dwmac.c revision 1.6
1 /* $NetBSD: meson_dwmac.c,v 1.6 2019/07/08 03:22:38 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.6 2019/07/08 03:22:38 msaitoh Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #define PRG_ETHERNET_ADDR0 0x00 53 #define CLKGEN_ENABLE __BIT(12) 54 #define RMII_CLK_I_INVERTED __BIT(11) 55 #define PHY_CLK_ENABLE __BIT(10) 56 #define MP2_CLK_OUT_DIV __BITS(9,7) 57 #define TX_CLK_DELAY __BITS(6,5) 58 #define PHY_INTERFACE_SEL __BIT(0) 59 60 static const char * compatible[] = { 61 "amlogic,meson8b-dwmac", 62 "amlogic,meson-gx-dwmac", 63 NULL 64 }; 65 66 static int 67 meson_dwmac_reset(const int phandle) 68 { 69 struct fdtbus_gpio_pin *pin_reset; 70 const u_int *reset_delay_us; 71 bool reset_active_low; 72 int len, val; 73 74 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 75 if (pin_reset == NULL) 76 return 0; 77 78 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 79 if (reset_delay_us == NULL || len != 12) 80 return ENXIO; 81 82 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 83 84 val = reset_active_low ? 1 : 0; 85 86 fdtbus_gpio_write(pin_reset, val); 87 delay(be32toh(reset_delay_us[0])); 88 fdtbus_gpio_write(pin_reset, !val); 89 delay(be32toh(reset_delay_us[1])); 90 fdtbus_gpio_write(pin_reset, val); 91 delay(be32toh(reset_delay_us[2])); 92 93 return 0; 94 } 95 96 static void 97 meson_dwmac_set_mode_rgmii(int phandle, bus_space_tag_t bst, 98 bus_space_handle_t bsh, struct clk *clkin) 99 { 100 u_int tx_delay; 101 uint32_t val; 102 103 const u_int div = clk_get_rate(clkin) / 250000000; 104 105 if (of_getprop_uint32(phandle, "amlogic,tx-delay-ns", &tx_delay) != 0) 106 tx_delay = 2; 107 108 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 109 val |= PHY_INTERFACE_SEL; 110 val &= ~TX_CLK_DELAY; 111 val |= __SHIFTIN((tx_delay >> 1), TX_CLK_DELAY); 112 val &= ~MP2_CLK_OUT_DIV; 113 val |= __SHIFTIN(div, MP2_CLK_OUT_DIV); 114 val |= PHY_CLK_ENABLE; 115 val |= CLKGEN_ENABLE; 116 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 117 } 118 119 static void 120 meson_dwmac_set_mode_rmii(int phandle, bus_space_tag_t bst, 121 bus_space_handle_t bsh) 122 { 123 uint32_t val; 124 125 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 126 val &= ~PHY_INTERFACE_SEL; 127 val |= RMII_CLK_I_INVERTED; 128 val &= ~TX_CLK_DELAY; 129 val |= CLKGEN_ENABLE; 130 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 131 } 132 133 static int 134 meson_dwmac_intr(void *arg) 135 { 136 struct dwc_gmac_softc * const sc = arg; 137 138 return dwc_gmac_intr(sc); 139 } 140 141 static int 142 meson_dwmac_match(device_t parent, cfdata_t cf, void *aux) 143 { 144 struct fdt_attach_args * const faa = aux; 145 146 return of_match_compatible(faa->faa_phandle, compatible); 147 } 148 149 static void 150 meson_dwmac_attach(device_t parent, device_t self, void *aux) 151 { 152 struct dwc_gmac_softc * const sc = device_private(self); 153 struct fdt_attach_args * const faa = aux; 154 const int phandle = faa->faa_phandle; 155 bus_space_handle_t prgeth_bsh; 156 struct fdtbus_reset *rst_gmac; 157 struct clk *clk_gmac, *clk_in[2]; 158 const char *phy_mode; 159 char intrstr[128]; 160 bus_addr_t addr[2]; 161 bus_size_t size[2]; 162 163 if (fdtbus_get_reg(phandle, 0, &addr[0], &size[0]) != 0 || 164 fdtbus_get_reg(phandle, 1, &addr[1], &size[1]) != 0) { 165 aprint_error(": couldn't get registers\n"); 166 return; 167 } 168 169 sc->sc_dev = self; 170 sc->sc_bst = faa->faa_bst; 171 if (bus_space_map(sc->sc_bst, addr[0], size[0], 0, &sc->sc_bsh) != 0 || 172 bus_space_map(sc->sc_bst, addr[1], size[1], 0, &prgeth_bsh) != 0) { 173 aprint_error(": couldn't map registers\n"); 174 return; 175 } 176 sc->sc_dmat = faa->faa_dmat; 177 178 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 179 aprint_error(": failed to decode interrupt\n"); 180 return; 181 } 182 183 clk_gmac = fdtbus_clock_get(phandle, "stmmaceth"); 184 clk_in[0] = fdtbus_clock_get(phandle, "clkin0"); 185 clk_in[1] = fdtbus_clock_get(phandle, "clkin1"); 186 if (clk_gmac == NULL || clk_in[0] == NULL || clk_in[1] == NULL) { 187 aprint_error(": couldn't get clocks\n"); 188 return; 189 } 190 191 rst_gmac = fdtbus_reset_get(phandle, "stmmaceth"); 192 193 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 194 if (phy_mode == NULL) { 195 aprint_error(": missing 'phy-mode' property\n"); 196 return; 197 } 198 199 if (strcmp(phy_mode, "rgmii") == 0) { 200 meson_dwmac_set_mode_rgmii(phandle, sc->sc_bst, prgeth_bsh, clk_in[0]); 201 } else if (strcmp(phy_mode, "rmii") == 0) { 202 meson_dwmac_set_mode_rmii(phandle, sc->sc_bst, prgeth_bsh); 203 } else { 204 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 205 return; 206 } 207 208 if (clk_enable(clk_gmac) != 0) { 209 aprint_error(": couldn't enable clock\n"); 210 return; 211 } 212 213 if (rst_gmac != NULL && fdtbus_reset_deassert(rst_gmac) != 0) { 214 aprint_error(": couldn't de-assert reset\n"); 215 return; 216 } 217 218 aprint_naive("\n"); 219 aprint_normal(": Gigabit Ethernet Controller\n"); 220 221 if (fdtbus_intr_establish(phandle, 0, IPL_NET, 0, meson_dwmac_intr, sc) == NULL) { 222 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 223 return; 224 } 225 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 226 227 if (meson_dwmac_reset(phandle) != 0) 228 aprint_error_dev(self, "PHY reset failed\n"); 229 230 dwc_gmac_attach(sc, MII_PHY_ANY, GMAC_MII_CLK_100_150M_DIV62); 231 } 232 233 CFATTACH_DECL_NEW(meson_dwmac, sizeof(struct dwc_gmac_softc), 234 meson_dwmac_match, meson_dwmac_attach, NULL, NULL); 235
Indexes created Wed Oct 01 18:09:54 GMT 2025