meson_platform.c revision 1.3.2.2
1 1.3.2.2 pgoyette /* $NetBSD: meson_platform.c,v 1.3.2.2 2019/01/26 21:59:59 pgoyette Exp $ */ 2 1.3.2.2 pgoyette 3 1.3.2.2 pgoyette /*- 4 1.3.2.2 pgoyette * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 1.3.2.2 pgoyette * All rights reserved. 6 1.3.2.2 pgoyette * 7 1.3.2.2 pgoyette * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 pgoyette * modification, are permitted provided that the following conditions 9 1.3.2.2 pgoyette * are met: 10 1.3.2.2 pgoyette * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 pgoyette * notice, this list of conditions and the following disclaimer. 12 1.3.2.2 pgoyette * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 pgoyette * notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 pgoyette * documentation and/or other materials provided with the distribution. 15 1.3.2.2 pgoyette * 16 1.3.2.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.3.2.2 pgoyette * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.3.2.2 pgoyette * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.3.2.2 pgoyette * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.3.2.2 pgoyette * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.3.2.2 pgoyette * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.3.2.2 pgoyette * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.3.2.2 pgoyette * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.3.2.2 pgoyette * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.3.2.2 pgoyette * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.3.2.2 pgoyette * SUCH DAMAGE. 27 1.3.2.2 pgoyette */ 28 1.3.2.2 pgoyette 29 1.3.2.2 pgoyette #include "opt_soc.h" 30 1.3.2.2 pgoyette #include "opt_multiprocessor.h" 31 1.3.2.2 pgoyette #include "opt_console.h" 32 1.3.2.2 pgoyette 33 1.3.2.2 pgoyette #include "arml2cc.h" 34 1.3.2.2 pgoyette 35 1.3.2.2 pgoyette #include <sys/cdefs.h> 36 1.3.2.2 pgoyette __KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.3.2.2 2019/01/26 21:59:59 pgoyette Exp $"); 37 1.3.2.2 pgoyette 38 1.3.2.2 pgoyette #include <sys/param.h> 39 1.3.2.2 pgoyette #include <sys/bus.h> 40 1.3.2.2 pgoyette #include <sys/cpu.h> 41 1.3.2.2 pgoyette #include <sys/device.h> 42 1.3.2.2 pgoyette #include <sys/termios.h> 43 1.3.2.2 pgoyette 44 1.3.2.2 pgoyette #include <dev/fdt/fdtvar.h> 45 1.3.2.2 pgoyette #include <arm/fdt/arm_fdtvar.h> 46 1.3.2.2 pgoyette 47 1.3.2.2 pgoyette #include <uvm/uvm_extern.h> 48 1.3.2.2 pgoyette 49 1.3.2.2 pgoyette #include <machine/bootconfig.h> 50 1.3.2.2 pgoyette #include <arm/cpufunc.h> 51 1.3.2.2 pgoyette 52 1.3.2.2 pgoyette #include <arm/cortex/a9tmr_var.h> 53 1.3.2.2 pgoyette #include <arm/cortex/pl310_var.h> 54 1.3.2.2 pgoyette #include <arm/cortex/scu_reg.h> 55 1.3.2.2 pgoyette 56 1.3.2.2 pgoyette #include <arm/amlogic/meson_uart.h> 57 1.3.2.2 pgoyette 58 1.3.2.2 pgoyette #include <evbarm/fdt/platform.h> 59 1.3.2.2 pgoyette #include <evbarm/fdt/machdep.h> 60 1.3.2.2 pgoyette 61 1.3.2.2 pgoyette #include <net/if_ether.h> 62 1.3.2.2 pgoyette 63 1.3.2.2 pgoyette #include <libfdt.h> 64 1.3.2.2 pgoyette 65 1.3.2.2 pgoyette #define MESON_CORE_APB3_VBASE KERNEL_IO_VBASE 66 1.3.2.2 pgoyette #define MESON_CORE_APB3_PBASE 0xc0000000 67 1.3.2.2 pgoyette #define MESON_CORE_APB3_SIZE 0x01300000 68 1.3.2.2 pgoyette 69 1.3.2.2 pgoyette #define MESON_CBUS_OFFSET 0x01100000 70 1.3.2.2 pgoyette 71 1.3.2.2 pgoyette #define MESON_WATCHDOG_BASE 0xc1109900 72 1.3.2.2 pgoyette #define MESON_WATCHDOG_SIZE 0x8 73 1.3.2.2 pgoyette #define MESON_WATCHDOG_TC 0x00 74 1.3.2.2 pgoyette #define WATCHDOG_TC_CPUS __BITS(27,24) 75 1.3.2.2 pgoyette #define WATCHDOG_TC_ENABLE __BIT(19) 76 1.3.2.2 pgoyette #define WATCHDOG_TC_TCNT __BITS(15,0) 77 1.3.2.2 pgoyette #define MESON_WATCHDOG_RESET 0x04 78 1.3.2.2 pgoyette #define WATCHDOG_RESET_COUNT __BITS(15,0) 79 1.3.2.2 pgoyette 80 1.3.2.2 pgoyette #define MESON8B_ARM_VBASE (MESON_CORE_APB3_VBASE + MESON_CORE_APB3_SIZE) 81 1.3.2.2 pgoyette #define MESON8B_ARM_PBASE 0xc4200000 82 1.3.2.2 pgoyette #define MESON8B_ARM_SIZE 0x00200000 83 1.3.2.2 pgoyette #define MESON8B_ARM_PL310_BASE 0x00000000 84 1.3.2.2 pgoyette #define MESON8B_ARM_SCU_BASE 0x00100000 85 1.3.2.2 pgoyette 86 1.3.2.2 pgoyette #define MESON8B_AOBUS_VBASE (MESON8B_ARM_VBASE + MESON8B_ARM_SIZE) 87 1.3.2.2 pgoyette #define MESON8B_AOBUS_PBASE 0xc8100000 88 1.3.2.2 pgoyette #define MESON8B_AOBUS_SIZE 0x00100000 89 1.3.2.2 pgoyette 90 1.3.2.2 pgoyette #define MESON_AOBUS_PWR_CTRL0_REG 0xe0 91 1.3.2.2 pgoyette #define MESON_AOBUS_PWR_CTRL1_REG 0xe4 92 1.3.2.2 pgoyette #define MESON_AOBUS_PWR_MEM_PD0_REG 0xf4 93 1.3.2.2 pgoyette 94 1.3.2.2 pgoyette #define MESON_CBUS_CPU_CLK_CNTL_REG 0x419c 95 1.3.2.2 pgoyette 96 1.3.2.2 pgoyette 97 1.3.2.2 pgoyette #define MESON8B_SRAM_VBASE (MESON8B_AOBUS_VBASE + MESON8B_AOBUS_SIZE) 98 1.3.2.2 pgoyette #define MESON8B_SRAM_PBASE 0xd9000000 99 1.3.2.2 pgoyette #define MESON8B_SRAM_SIZE 0x00010000 /* 0x10000 rounded up */ 100 1.3.2.2 pgoyette 101 1.3.2.2 pgoyette #define MESON8B_SRAM_CPUCONF_OFFSET 0x1ff80 102 1.3.2.2 pgoyette #define MESON8B_SRAM_CPUCONF_CTRL_REG 0x00 103 1.3.2.2 pgoyette #define MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(n) (0x04 * (n)) 104 1.3.2.2 pgoyette 105 1.3.2.2 pgoyette 106 1.3.2.2 pgoyette extern struct arm32_bus_dma_tag arm_generic_dma_tag; 107 1.3.2.2 pgoyette extern struct bus_space arm_generic_bs_tag; 108 1.3.2.2 pgoyette extern struct bus_space arm_generic_a4x_bs_tag; 109 1.3.2.2 pgoyette 110 1.3.2.2 pgoyette #define meson_dma_tag arm_generic_dma_tag 111 1.3.2.2 pgoyette #define meson_bs_tag arm_generic_bs_tag 112 1.3.2.2 pgoyette #define meson_a4x_bs_tag arm_generic_a4x_bs_tag 113 1.3.2.2 pgoyette 114 1.3.2.2 pgoyette static const struct pmap_devmap * 115 1.3.2.2 pgoyette meson_platform_devmap(void) 116 1.3.2.2 pgoyette { 117 1.3.2.2 pgoyette static const struct pmap_devmap devmap[] = { 118 1.3.2.2 pgoyette DEVMAP_ENTRY(MESON_CORE_APB3_VBASE, 119 1.3.2.2 pgoyette MESON_CORE_APB3_PBASE, 120 1.3.2.2 pgoyette MESON_CORE_APB3_SIZE), 121 1.3.2.2 pgoyette DEVMAP_ENTRY(MESON8B_ARM_VBASE, 122 1.3.2.2 pgoyette MESON8B_ARM_PBASE, 123 1.3.2.2 pgoyette MESON8B_ARM_SIZE), 124 1.3.2.2 pgoyette DEVMAP_ENTRY(MESON8B_AOBUS_VBASE, 125 1.3.2.2 pgoyette MESON8B_AOBUS_PBASE, 126 1.3.2.2 pgoyette MESON8B_AOBUS_SIZE), 127 1.3.2.2 pgoyette DEVMAP_ENTRY(MESON8B_SRAM_VBASE, 128 1.3.2.2 pgoyette MESON8B_SRAM_PBASE, 129 1.3.2.2 pgoyette MESON8B_SRAM_SIZE), 130 1.3.2.2 pgoyette DEVMAP_ENTRY_END 131 1.3.2.2 pgoyette }; 132 1.3.2.2 pgoyette 133 1.3.2.2 pgoyette return devmap; 134 1.3.2.2 pgoyette } 135 1.3.2.2 pgoyette 136 1.3.2.2 pgoyette static void 137 1.3.2.2 pgoyette meson_platform_init_attach_args(struct fdt_attach_args *faa) 138 1.3.2.2 pgoyette { 139 1.3.2.2 pgoyette faa->faa_bst = &meson_bs_tag; 140 1.3.2.2 pgoyette faa->faa_a4x_bst = &meson_a4x_bs_tag; 141 1.3.2.2 pgoyette faa->faa_dmat = &meson_dma_tag; 142 1.3.2.2 pgoyette } 143 1.3.2.2 pgoyette 144 1.3.2.2 pgoyette void meson_platform_early_putchar(char); 145 1.3.2.2 pgoyette 146 1.3.2.2 pgoyette void 147 1.3.2.2 pgoyette meson_platform_early_putchar(char c) 148 1.3.2.2 pgoyette { 149 1.3.2.2 pgoyette #ifdef CONSADDR 150 1.3.2.2 pgoyette #define CONSADDR_VA ((CONSADDR - MESON8B_AOBUS_PBASE) + MESON8B_AOBUS_VBASE) 151 1.3.2.2 pgoyette volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 152 1.3.2.2 pgoyette (volatile uint32_t *)CONSADDR_VA : 153 1.3.2.2 pgoyette (volatile uint32_t *)CONSADDR; 154 1.3.2.2 pgoyette int timo = 150000; 155 1.3.2.2 pgoyette 156 1.3.2.2 pgoyette while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 157 1.3.2.2 pgoyette if (--timo == 0) 158 1.3.2.2 pgoyette break; 159 1.3.2.2 pgoyette } 160 1.3.2.2 pgoyette 161 1.3.2.2 pgoyette uartaddr[UART_WFIFO_REG/4] = c; 162 1.3.2.2 pgoyette 163 1.3.2.2 pgoyette while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 164 1.3.2.2 pgoyette if (--timo == 0) 165 1.3.2.2 pgoyette break; 166 1.3.2.2 pgoyette } 167 1.3.2.2 pgoyette #endif 168 1.3.2.2 pgoyette } 169 1.3.2.2 pgoyette 170 1.3.2.2 pgoyette static void 171 1.3.2.2 pgoyette meson_platform_device_register(device_t self, void *aux) 172 1.3.2.2 pgoyette { 173 1.3.2.2 pgoyette prop_dictionary_t dict = device_properties(self); 174 1.3.2.2 pgoyette 175 1.3.2.2 pgoyette if (device_is_a(self, "awge") && device_unit(self) == 0) { 176 1.3.2.2 pgoyette uint8_t enaddr[ETHER_ADDR_LEN]; 177 1.3.2.2 pgoyette if (get_bootconf_option(boot_args, "awge0.mac-address", 178 1.3.2.2 pgoyette BOOTOPT_TYPE_MACADDR, enaddr)) { 179 1.3.2.2 pgoyette prop_data_t pd = prop_data_create_data(enaddr, 180 1.3.2.2 pgoyette sizeof(enaddr)); 181 1.3.2.2 pgoyette prop_dictionary_set(dict, "mac-address", pd); 182 1.3.2.2 pgoyette prop_object_release(pd); 183 1.3.2.2 pgoyette } 184 1.3.2.2 pgoyette } 185 1.3.2.2 pgoyette 186 1.3.2.2 pgoyette if (device_is_a(self, "genfb")) { 187 1.3.2.2 pgoyette int scale, depth; 188 1.3.2.2 pgoyette 189 1.3.2.2 pgoyette if (get_bootconf_option(boot_args, "fb.scale", 190 1.3.2.2 pgoyette BOOTOPT_TYPE_INT, &scale) && scale > 0) { 191 1.3.2.2 pgoyette prop_dictionary_set_uint32(dict, "scale", scale); 192 1.3.2.2 pgoyette } 193 1.3.2.2 pgoyette if (get_bootconf_option(boot_args, "fb.depth", 194 1.3.2.2 pgoyette BOOTOPT_TYPE_INT, &depth)) { 195 1.3.2.2 pgoyette prop_dictionary_set_uint32(dict, "depth", depth); 196 1.3.2.2 pgoyette } 197 1.3.2.2 pgoyette } 198 1.3.2.2 pgoyette } 199 1.3.2.2 pgoyette 200 1.3.2.2 pgoyette #if defined(SOC_MESON8B) 201 1.3.2.2 pgoyette #define MESON8B_BOOTINFO_REG 0xd901ff04 202 1.3.2.2 pgoyette static int 203 1.3.2.2 pgoyette meson8b_get_boot_id(void) 204 1.3.2.2 pgoyette { 205 1.3.2.2 pgoyette static int boot_id = -1; 206 1.3.2.2 pgoyette bus_space_tag_t bst = &arm_generic_bs_tag; 207 1.3.2.2 pgoyette bus_space_handle_t bsh; 208 1.3.2.2 pgoyette 209 1.3.2.2 pgoyette if (boot_id == -1) { 210 1.3.2.2 pgoyette if (bus_space_map(bst, MESON8B_BOOTINFO_REG, 4, 0, &bsh) != 0) 211 1.3.2.2 pgoyette return -1; 212 1.3.2.2 pgoyette 213 1.3.2.2 pgoyette boot_id = (int)bus_space_read_4(bst, bsh, 0); 214 1.3.2.2 pgoyette 215 1.3.2.2 pgoyette bus_space_unmap(bst, bsh, 4); 216 1.3.2.2 pgoyette } 217 1.3.2.2 pgoyette 218 1.3.2.2 pgoyette return boot_id; 219 1.3.2.2 pgoyette } 220 1.3.2.2 pgoyette 221 1.3.2.2 pgoyette static void 222 1.3.2.2 pgoyette meson8b_platform_device_register(device_t self, void *aux) 223 1.3.2.2 pgoyette { 224 1.3.2.2 pgoyette device_t parent = device_parent(self); 225 1.3.2.2 pgoyette char *ptr; 226 1.3.2.2 pgoyette 227 1.3.2.2 pgoyette if (device_is_a(self, "ld") && 228 1.3.2.2 pgoyette device_is_a(parent, "sdmmc") && 229 1.3.2.2 pgoyette (device_is_a(device_parent(parent), "mesonsdhc") || 230 1.3.2.2 pgoyette device_is_a(device_parent(parent), "mesonsdio"))) { 231 1.3.2.2 pgoyette 232 1.3.2.2 pgoyette const int boot_id = meson8b_get_boot_id(); 233 1.3.2.2 pgoyette const bool has_rootdev = get_bootconf_option(boot_args, "root", BOOTOPT_TYPE_STRING, &ptr) != 0; 234 1.3.2.2 pgoyette 235 1.3.2.2 pgoyette if (!has_rootdev) { 236 1.3.2.2 pgoyette char rootarg[64]; 237 1.3.2.2 pgoyette snprintf(rootarg, sizeof(rootarg), " root=%sa", device_xname(self)); 238 1.3.2.2 pgoyette 239 1.3.2.2 pgoyette /* Assume that SDIO is used for SD cards and SDHC is used for eMMC */ 240 1.3.2.2 pgoyette if (device_is_a(device_parent(parent), "mesonsdhc") && boot_id == 0) 241 1.3.2.2 pgoyette strcat(boot_args, rootarg); 242 1.3.2.2 pgoyette else if (device_is_a(device_parent(parent), "mesonsdio") && boot_id != 0) 243 1.3.2.2 pgoyette strcat(boot_args, rootarg); 244 1.3.2.2 pgoyette } 245 1.3.2.2 pgoyette } 246 1.3.2.2 pgoyette 247 1.3.2.2 pgoyette meson_platform_device_register(self, aux); 248 1.3.2.2 pgoyette } 249 1.3.2.2 pgoyette #endif 250 1.3.2.2 pgoyette 251 1.3.2.2 pgoyette static u_int 252 1.3.2.2 pgoyette meson_platform_uart_freq(void) 253 1.3.2.2 pgoyette { 254 1.3.2.2 pgoyette return 0; 255 1.3.2.2 pgoyette } 256 1.3.2.2 pgoyette 257 1.3.2.2 pgoyette static void 258 1.3.2.2 pgoyette meson_platform_bootstrap(void) 259 1.3.2.2 pgoyette { 260 1.3.2.2 pgoyette arm_fdt_cpu_bootstrap(); 261 1.3.2.2 pgoyette 262 1.3.2.2 pgoyette void *fdt_data = __UNCONST(fdtbus_get_data()); 263 1.3.2.2 pgoyette const int chosen_off = fdt_path_offset(fdt_data, "/chosen"); 264 1.3.2.2 pgoyette if (chosen_off < 0) 265 1.3.2.2 pgoyette return; 266 1.3.2.2 pgoyette 267 1.3.2.2 pgoyette if (match_bootconf_option(boot_args, "console", "fb")) { 268 1.3.2.2 pgoyette const int framebuffer_off = 269 1.3.2.2 pgoyette fdt_path_offset(fdt_data, "/chosen/framebuffer"); 270 1.3.2.2 pgoyette if (framebuffer_off >= 0) { 271 1.3.2.2 pgoyette const char *status = fdt_getprop(fdt_data, 272 1.3.2.2 pgoyette framebuffer_off, "status", NULL); 273 1.3.2.2 pgoyette if (status == NULL || strncmp(status, "ok", 2) == 0) { 274 1.3.2.2 pgoyette fdt_setprop_string(fdt_data, chosen_off, 275 1.3.2.2 pgoyette "stdout-path", "/chosen/framebuffer"); 276 1.3.2.2 pgoyette } 277 1.3.2.2 pgoyette } 278 1.3.2.2 pgoyette } else if (match_bootconf_option(boot_args, "console", "serial")) { 279 1.3.2.2 pgoyette fdt_setprop_string(fdt_data, chosen_off, 280 1.3.2.2 pgoyette "stdout-path", "serial0:115200n8"); 281 1.3.2.2 pgoyette } 282 1.3.2.2 pgoyette } 283 1.3.2.2 pgoyette 284 1.3.2.2 pgoyette #if defined(SOC_MESON8B) 285 1.3.2.2 pgoyette static void 286 1.3.2.2 pgoyette meson8b_platform_bootstrap(void) 287 1.3.2.2 pgoyette { 288 1.3.2.2 pgoyette 289 1.3.2.2 pgoyette #if NARML2CC > 0 290 1.3.2.2 pgoyette const bus_space_handle_t pl310_bh = MESON8B_ARM_VBASE + MESON8B_ARM_PL310_BASE; 291 1.3.2.2 pgoyette arml2cc_init(&arm_generic_bs_tag, pl310_bh, 0); 292 1.3.2.2 pgoyette #endif 293 1.3.2.2 pgoyette 294 1.3.2.2 pgoyette meson_platform_bootstrap(); 295 1.3.2.2 pgoyette } 296 1.3.2.2 pgoyette #endif 297 1.3.2.2 pgoyette 298 1.3.2.2 pgoyette static void 299 1.3.2.2 pgoyette meson_platform_reset(void) 300 1.3.2.2 pgoyette { 301 1.3.2.2 pgoyette bus_space_tag_t bst = &meson_bs_tag; 302 1.3.2.2 pgoyette bus_space_handle_t bsh; 303 1.3.2.2 pgoyette 304 1.3.2.2 pgoyette bus_space_map(bst, MESON_WATCHDOG_BASE, MESON_WATCHDOG_SIZE, 0, &bsh); 305 1.3.2.2 pgoyette 306 1.3.2.2 pgoyette bus_space_write_4(bst, bsh, MESON_WATCHDOG_TC, 307 1.3.2.2 pgoyette WATCHDOG_TC_CPUS | WATCHDOG_TC_ENABLE | __SHIFTIN(0xfff, WATCHDOG_TC_TCNT)); 308 1.3.2.2 pgoyette bus_space_write_4(bst, bsh, MESON_WATCHDOG_RESET, 0); 309 1.3.2.2 pgoyette 310 1.3.2.2 pgoyette for (;;) { 311 1.3.2.2 pgoyette __asm("wfi"); 312 1.3.2.2 pgoyette } 313 1.3.2.2 pgoyette } 314 1.3.2.2 pgoyette 315 1.3.2.2 pgoyette #if defined(MULTIPROCESSOR) 316 1.3.2.2 pgoyette static void 317 1.3.2.2 pgoyette meson8b_mpinit_delay(u_int n) 318 1.3.2.2 pgoyette { 319 1.3.2.2 pgoyette for (volatile int i = 0; i < n; i++) 320 1.3.2.2 pgoyette ; 321 1.3.2.2 pgoyette } 322 1.3.2.2 pgoyette 323 1.3.2.2 pgoyette static int 324 1.3.2.2 pgoyette cpu_enable_meson8b(int phandle) 325 1.3.2.2 pgoyette { 326 1.3.2.2 pgoyette const bus_addr_t cbar = armreg_cbar_read(); 327 1.3.2.2 pgoyette bus_space_tag_t bst = &arm_generic_bs_tag; 328 1.3.2.2 pgoyette 329 1.3.2.2 pgoyette const bus_space_handle_t scu_bsh = 330 1.3.2.2 pgoyette cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 331 1.3.2.2 pgoyette const bus_space_handle_t cpuconf_bsh = 332 1.3.2.2 pgoyette MESON8B_SRAM_VBASE + MESON8B_SRAM_CPUCONF_OFFSET; 333 1.3.2.2 pgoyette const bus_space_handle_t ao_bsh = 334 1.3.2.2 pgoyette MESON8B_AOBUS_VBASE; 335 1.3.2.2 pgoyette const bus_space_handle_t cbus_bsh = 336 1.3.2.2 pgoyette MESON_CORE_APB3_VBASE + MESON_CBUS_OFFSET; 337 1.3.2.2 pgoyette uint32_t pwr_sts, pwr_cntl0, pwr_cntl1, cpuclk, mempd0; 338 1.3.2.2 pgoyette uint64_t mpidr; 339 1.3.2.2 pgoyette 340 1.3.2.2 pgoyette fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 341 1.3.2.2 pgoyette 342 1.3.2.2 pgoyette const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0); 343 1.3.2.2 pgoyette 344 1.3.2.2 pgoyette bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 345 1.3.2.2 pgoyette KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 346 1.3.2.2 pgoyette 347 1.3.2.2 pgoyette pwr_sts = bus_space_read_4(bst, scu_bsh, SCU_CPU_PWR_STS); 348 1.3.2.2 pgoyette pwr_sts &= ~(3 << (8 * cpuno)); 349 1.3.2.2 pgoyette bus_space_write_4(bst, scu_bsh, SCU_CPU_PWR_STS, pwr_sts); 350 1.3.2.2 pgoyette 351 1.3.2.2 pgoyette pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 352 1.3.2.2 pgoyette pwr_cntl0 &= ~((3 << 18) << ((cpuno - 1) * 2)); 353 1.3.2.2 pgoyette bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 354 1.3.2.2 pgoyette 355 1.3.2.2 pgoyette meson8b_mpinit_delay(5000); 356 1.3.2.2 pgoyette 357 1.3.2.2 pgoyette cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 358 1.3.2.2 pgoyette cpuclk |= (1 << (24 + cpuno)); 359 1.3.2.2 pgoyette bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 360 1.3.2.2 pgoyette 361 1.3.2.2 pgoyette mempd0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG); 362 1.3.2.2 pgoyette mempd0 &= ~((uint32_t)(0xf << 28) >> ((cpuno - 1) * 4)); 363 1.3.2.2 pgoyette bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG, mempd0); 364 1.3.2.2 pgoyette 365 1.3.2.2 pgoyette pwr_cntl1 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG); 366 1.3.2.2 pgoyette pwr_cntl1 &= ~((3 << 4) << ((cpuno - 1) * 2)); 367 1.3.2.2 pgoyette bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG, pwr_cntl1); 368 1.3.2.2 pgoyette 369 1.3.2.2 pgoyette meson8b_mpinit_delay(10000); 370 1.3.2.2 pgoyette 371 1.3.2.2 pgoyette for (;;) { 372 1.3.2.2 pgoyette pwr_cntl1 = bus_space_read_4(bst, ao_bsh, 373 1.3.2.2 pgoyette MESON_AOBUS_PWR_CTRL1_REG) & ((1 << 17) << (cpuno - 1)); 374 1.3.2.2 pgoyette if (pwr_cntl1) 375 1.3.2.2 pgoyette break; 376 1.3.2.2 pgoyette meson8b_mpinit_delay(10000); 377 1.3.2.2 pgoyette } 378 1.3.2.2 pgoyette 379 1.3.2.2 pgoyette pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 380 1.3.2.2 pgoyette pwr_cntl0 &= ~(1 << cpuno); 381 1.3.2.2 pgoyette bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 382 1.3.2.2 pgoyette 383 1.3.2.2 pgoyette cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 384 1.3.2.2 pgoyette cpuclk &= ~(1 << (24 + cpuno)); 385 1.3.2.2 pgoyette bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 386 1.3.2.2 pgoyette 387 1.3.2.2 pgoyette bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 388 1.3.2.2 pgoyette KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 389 1.3.2.2 pgoyette 390 1.3.2.2 pgoyette uint32_t ctrl = bus_space_read_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG); 391 1.3.2.2 pgoyette ctrl |= __BITS(cpuno,0); 392 1.3.2.2 pgoyette bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG, ctrl); 393 1.3.2.2 pgoyette 394 1.3.2.2 pgoyette return 0; 395 1.3.2.2 pgoyette } 396 1.3.2.2 pgoyette 397 1.3.2.2 pgoyette ARM_CPU_METHOD(meson8b, "amlogic,meson8b-smp", cpu_enable_meson8b); 398 1.3.2.2 pgoyette #endif 399 1.3.2.2 pgoyette 400 1.3.2.2 pgoyette static void 401 1.3.2.2 pgoyette meson_mpstart(void) 402 1.3.2.2 pgoyette { 403 1.3.2.2 pgoyette #ifdef MULTIPROCESSOR 404 1.3.2.2 pgoyette const bus_addr_t cbar = armreg_cbar_read(); 405 1.3.2.2 pgoyette bus_space_tag_t bst = &arm_generic_bs_tag; 406 1.3.2.2 pgoyette 407 1.3.2.2 pgoyette if (cbar == 0) 408 1.3.2.2 pgoyette return; 409 1.3.2.2 pgoyette 410 1.3.2.2 pgoyette const bus_space_handle_t scu_bsh = 411 1.3.2.2 pgoyette cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 412 1.3.2.2 pgoyette 413 1.3.2.2 pgoyette const uint32_t scu_cfg = bus_space_read_4(bst, scu_bsh, SCU_CFG); 414 1.3.2.2 pgoyette const u_int ncpus = (scu_cfg & SCU_CFG_CPUMAX) + 1; 415 1.3.2.2 pgoyette 416 1.3.2.2 pgoyette if (ncpus < 2) 417 1.3.2.2 pgoyette return; 418 1.3.2.2 pgoyette 419 1.3.2.2 pgoyette /* 420 1.3.2.2 pgoyette * Invalidate all SCU cache tags. That is, for all cores (0-3) 421 1.3.2.2 pgoyette */ 422 1.3.2.2 pgoyette bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff); 423 1.3.2.2 pgoyette 424 1.3.2.2 pgoyette uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL); 425 1.3.2.2 pgoyette scu_ctl |= SCU_CTL_SCU_ENA; 426 1.3.2.2 pgoyette bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl); 427 1.3.2.2 pgoyette 428 1.3.2.2 pgoyette armv7_dcache_wbinv_all(); 429 1.3.2.2 pgoyette 430 1.3.2.2 pgoyette arm_fdt_cpu_mpstart(); 431 1.3.2.2 pgoyette #endif 432 1.3.2.2 pgoyette } 433 1.3.2.2 pgoyette 434 1.3.2.2 pgoyette 435 1.3.2.2 pgoyette #if defined(SOC_MESON8B) 436 1.3.2.2 pgoyette static const struct arm_platform meson8b_platform = { 437 1.3.2.2 pgoyette .ap_devmap = meson_platform_devmap, 438 1.3.2.2 pgoyette .ap_bootstrap = meson8b_platform_bootstrap, 439 1.3.2.2 pgoyette .ap_init_attach_args = meson_platform_init_attach_args, 440 1.3.2.2 pgoyette .ap_device_register = meson8b_platform_device_register, 441 1.3.2.2 pgoyette .ap_reset = meson_platform_reset, 442 1.3.2.2 pgoyette .ap_delay = a9tmr_delay, 443 1.3.2.2 pgoyette .ap_uart_freq = meson_platform_uart_freq, 444 1.3.2.2 pgoyette .ap_mpstart = meson_mpstart, 445 1.3.2.2 pgoyette }; 446 1.3.2.2 pgoyette 447 1.3.2.2 pgoyette ARM_PLATFORM(meson8b, "amlogic,meson8b", &meson8b_platform); 448 1.3.2.2 pgoyette #endif 449
Indexes created Tue Sep 30 20:09:53 GMT 2025