meson_platform.c revision 1.14
1 /* $NetBSD: meson_platform.c,v 1.14 2020/06/20 15:48:19 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 #include "opt_multiprocessor.h" 31 #include "opt_console.h" 32 33 #include "arml2cc.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.14 2020/06/20 15:48:19 skrll Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 #include <sys/termios.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <arm/fdt/arm_fdtvar.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bootconfig.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/cortex/a9tmr_var.h> 53 #include <arm/cortex/gtmr_var.h> 54 #include <arm/cortex/pl310_var.h> 55 #include <arm/cortex/scu_reg.h> 56 57 #include <arm/amlogic/meson_uart.h> 58 59 #include <evbarm/fdt/platform.h> 60 #include <evbarm/fdt/machdep.h> 61 62 #include <net/if_ether.h> 63 64 #include <libfdt.h> 65 66 #define MESON_CORE_APB3_VBASE KERNEL_IO_VBASE 67 #define MESON_CORE_APB3_PBASE 0xc0000000 68 #define MESON_CORE_APB3_SIZE 0x01400000 69 70 #define MESON_CBUS_OFFSET 0x01100000 71 72 #define MESON8B_WATCHDOG_BASE 0xc1109900 73 #define MESON8B_WATCHDOG_SIZE 0x8 74 #define MESON8B_WATCHDOG_TC 0x00 75 #define MESON8B_WATCHDOG_TC_CPUS __BITS(27,24) 76 #define MESON8B_WATCHDOG_TC_ENABLE __BIT(19) 77 #define MESON8B_WATCHDOG_TC_TCNT __BITS(15,0) 78 #define MESON8B_WATCHDOG_RESET 0x04 79 #define MESON8B_WATCHDOG_RESET_COUNT __BITS(15,0) 80 81 #define MESONGX_WATCHDOG_BASE 0xc11098d0 82 #define MESONGX_WATCHDOG_SIZE 0x10 83 #define MESONGX_WATCHDOG_CNTL 0x00 84 #define MESONGX_WATCHDOG_CNTL_CLK_EN __BIT(24) 85 #define MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN __BIT(21) 86 #define MESONGX_WATCHDOG_CNTL_WDOG_EN __BIT(18) 87 #define MESONGX_WATCHDOG_CNTL1 0x04 88 #define MESONGX_WATCHDOG_TCNT 0x08 89 #define MESONGX_WATCHDOG_TCNT_COUNT __BITS(15,0) 90 #define MESONGX_WATCHDOG_RESET 0x0c 91 92 #define MESON8B_ARM_VBASE (MESON_CORE_APB3_VBASE + MESON_CORE_APB3_SIZE) 93 #define MESON8B_ARM_PBASE 0xc4200000 94 #define MESON8B_ARM_SIZE 0x00200000 95 #define MESON8B_ARM_PL310_BASE 0x00000000 96 #define MESON8B_ARM_SCU_BASE 0x00100000 97 98 #define MESON8B_AOBUS_VBASE (MESON8B_ARM_VBASE + MESON8B_ARM_SIZE) 99 #define MESON8B_AOBUS_PBASE 0xc8000000 100 #define MESON8B_AOBUS_SIZE 0x00200000 101 #define MESON8B_AOBUS_RTI_OFFSET 0x00100000 102 103 #define MESON_AOBUS_PWR_CTRL0_REG 0xe0 104 #define MESON_AOBUS_PWR_CTRL1_REG 0xe4 105 #define MESON_AOBUS_PWR_MEM_PD0_REG 0xf4 106 107 #define MESON_CBUS_CPU_CLK_CNTL_REG 0x419c 108 109 110 #define MESON8B_SRAM_VBASE (MESON8B_AOBUS_VBASE + MESON8B_AOBUS_SIZE) 111 #define MESON8B_SRAM_PBASE 0xd9000000 112 #define MESON8B_SRAM_SIZE 0x00200000 /* 0x10000 rounded up */ 113 114 #define MESON8B_SRAM_CPUCONF_OFFSET 0x1ff80 115 #define MESON8B_SRAM_CPUCONF_CTRL_REG 0x00 116 #define MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(n) (0x04 * (n)) 117 118 119 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 120 extern struct bus_space arm_generic_bs_tag; 121 extern struct bus_space arm_generic_a4x_bs_tag; 122 123 #define meson_dma_tag arm_generic_dma_tag 124 #define meson_bs_tag arm_generic_bs_tag 125 #define meson_a4x_bs_tag arm_generic_a4x_bs_tag 126 127 static const struct pmap_devmap * 128 meson_platform_devmap(void) 129 { 130 static const struct pmap_devmap devmap[] = { 131 DEVMAP_ENTRY(MESON_CORE_APB3_VBASE, 132 MESON_CORE_APB3_PBASE, 133 MESON_CORE_APB3_SIZE), 134 DEVMAP_ENTRY(MESON8B_ARM_VBASE, 135 MESON8B_ARM_PBASE, 136 MESON8B_ARM_SIZE), 137 DEVMAP_ENTRY(MESON8B_AOBUS_VBASE, 138 MESON8B_AOBUS_PBASE, 139 MESON8B_AOBUS_SIZE), 140 DEVMAP_ENTRY(MESON8B_SRAM_VBASE, 141 MESON8B_SRAM_PBASE, 142 MESON8B_SRAM_SIZE), 143 DEVMAP_ENTRY_END 144 }; 145 146 return devmap; 147 } 148 149 static void 150 meson_platform_init_attach_args(struct fdt_attach_args *faa) 151 { 152 faa->faa_bst = &meson_bs_tag; 153 faa->faa_a4x_bst = &meson_a4x_bs_tag; 154 faa->faa_dmat = &meson_dma_tag; 155 } 156 157 void meson_platform_early_putchar(char); 158 159 void 160 meson_platform_early_putchar(char c) 161 { 162 #ifdef CONSADDR 163 #define CONSADDR_VA ((CONSADDR - MESON8B_AOBUS_PBASE) + MESON8B_AOBUS_VBASE) 164 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 165 (volatile uint32_t *)CONSADDR_VA : 166 (volatile uint32_t *)CONSADDR; 167 int timo = 150000; 168 169 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 170 if (--timo == 0) 171 break; 172 } 173 174 uartaddr[UART_WFIFO_REG/4] = c; 175 176 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 177 if (--timo == 0) 178 break; 179 } 180 #endif 181 } 182 183 static void 184 meson_platform_device_register(device_t self, void *aux) 185 { 186 prop_dictionary_t dict = device_properties(self); 187 188 if (device_is_a(self, "awge") && device_unit(self) == 0) { 189 uint8_t enaddr[ETHER_ADDR_LEN]; 190 if (get_bootconf_option(boot_args, "awge0.mac-address", 191 BOOTOPT_TYPE_MACADDR, enaddr)) { 192 prop_dictionary_set_data(dict, "mac-address", enaddr, 193 sizeof(enaddr)); 194 } 195 } 196 197 if (device_is_a(self, "mesonfb")) { 198 int scale, depth; 199 200 if (get_bootconf_option(boot_args, "fb.scale", 201 BOOTOPT_TYPE_INT, &scale) && scale > 0) { 202 prop_dictionary_set_uint32(dict, "scale", scale); 203 } 204 if (get_bootconf_option(boot_args, "fb.depth", 205 BOOTOPT_TYPE_INT, &depth)) { 206 prop_dictionary_set_uint32(dict, "depth", depth); 207 } 208 } 209 } 210 211 #if defined(SOC_MESON8B) 212 #define MESON8B_BOOTINFO_REG 0xd901ff04 213 static int 214 meson8b_get_boot_id(void) 215 { 216 static int boot_id = -1; 217 bus_space_tag_t bst = &arm_generic_bs_tag; 218 bus_space_handle_t bsh; 219 220 if (boot_id == -1) { 221 if (bus_space_map(bst, MESON8B_BOOTINFO_REG, 4, 0, &bsh) != 0) 222 return -1; 223 224 boot_id = (int)bus_space_read_4(bst, bsh, 0); 225 226 bus_space_unmap(bst, bsh, 4); 227 } 228 229 return boot_id; 230 } 231 232 static void 233 meson8b_platform_device_register(device_t self, void *aux) 234 { 235 device_t parent = device_parent(self); 236 char *ptr; 237 238 if (device_is_a(self, "ld") && 239 device_is_a(parent, "sdmmc") && 240 (device_is_a(device_parent(parent), "mesonsdhc") || 241 device_is_a(device_parent(parent), "mesonsdio"))) { 242 243 const int boot_id = meson8b_get_boot_id(); 244 const bool has_rootdev = get_bootconf_option(boot_args, "root", BOOTOPT_TYPE_STRING, &ptr) != 0; 245 246 if (!has_rootdev) { 247 char rootarg[64]; 248 snprintf(rootarg, sizeof(rootarg), " root=%sa", device_xname(self)); 249 250 /* Assume that SDIO is used for SD cards and SDHC is used for eMMC */ 251 if (device_is_a(device_parent(parent), "mesonsdhc") && boot_id == 0) 252 strcat(boot_args, rootarg); 253 else if (device_is_a(device_parent(parent), "mesonsdio") && boot_id != 0) 254 strcat(boot_args, rootarg); 255 } 256 } 257 258 meson_platform_device_register(self, aux); 259 } 260 #endif 261 262 static u_int 263 meson_platform_uart_freq(void) 264 { 265 return 0; 266 } 267 268 static void 269 meson_platform_bootstrap(void) 270 { 271 arm_fdt_cpu_bootstrap(); 272 273 void *fdt_data = __UNCONST(fdtbus_get_data()); 274 const int chosen_off = fdt_path_offset(fdt_data, "/chosen"); 275 if (chosen_off < 0) 276 return; 277 278 if (match_bootconf_option(boot_args, "console", "fb")) { 279 const int framebuffer_off = 280 fdt_path_offset(fdt_data, "/chosen/framebuffer"); 281 if (framebuffer_off >= 0) { 282 const char *status = fdt_getprop(fdt_data, 283 framebuffer_off, "status", NULL); 284 if (status == NULL || strncmp(status, "ok", 2) == 0) { 285 fdt_setprop_string(fdt_data, chosen_off, 286 "stdout-path", "/chosen/framebuffer"); 287 } 288 } 289 } else if (match_bootconf_option(boot_args, "console", "serial")) { 290 fdt_setprop_string(fdt_data, chosen_off, 291 "stdout-path", "serial0:115200n8"); 292 } 293 } 294 295 #if defined(SOC_MESON8B) 296 static void 297 meson8b_platform_bootstrap(void) 298 { 299 300 #if NARML2CC > 0 301 const bus_space_handle_t pl310_bh = MESON8B_ARM_VBASE + MESON8B_ARM_PL310_BASE; 302 arml2cc_init(&arm_generic_bs_tag, pl310_bh, 0); 303 #endif 304 305 meson_platform_bootstrap(); 306 } 307 308 static void 309 meson8b_platform_reset(void) 310 { 311 bus_space_tag_t bst = &meson_bs_tag; 312 bus_space_handle_t bsh; 313 314 bus_space_map(bst, MESON8B_WATCHDOG_BASE, MESON8B_WATCHDOG_SIZE, 0, &bsh); 315 316 bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_TC, 317 MESON8B_WATCHDOG_TC_CPUS | MESON8B_WATCHDOG_TC_ENABLE | __SHIFTIN(0xfff, MESON8B_WATCHDOG_TC_TCNT)); 318 bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_RESET, 0); 319 320 for (;;) { 321 __asm("wfi"); 322 } 323 } 324 325 static void 326 meson8b_mpinit_delay(u_int n) 327 { 328 for (volatile int i = 0; i < n; i++) 329 ; 330 } 331 332 static int 333 cpu_enable_meson8b(int phandle) 334 { 335 const bus_addr_t cbar = armreg_cbar_read(); 336 bus_space_tag_t bst = &arm_generic_bs_tag; 337 338 const bus_space_handle_t scu_bsh = 339 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 340 const bus_space_handle_t cpuconf_bsh = 341 MESON8B_SRAM_VBASE + MESON8B_SRAM_CPUCONF_OFFSET; 342 const bus_space_handle_t ao_bsh = 343 MESON8B_AOBUS_VBASE + MESON8B_AOBUS_RTI_OFFSET; 344 const bus_space_handle_t cbus_bsh = 345 MESON_CORE_APB3_VBASE + MESON_CBUS_OFFSET; 346 uint32_t pwr_sts, pwr_cntl0, pwr_cntl1, cpuclk, mempd0; 347 uint64_t mpidr; 348 349 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 350 351 const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0); 352 353 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 354 KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 355 356 pwr_sts = bus_space_read_4(bst, scu_bsh, SCU_CPU_PWR_STS); 357 pwr_sts &= ~(3 << (8 * cpuno)); 358 bus_space_write_4(bst, scu_bsh, SCU_CPU_PWR_STS, pwr_sts); 359 360 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 361 pwr_cntl0 &= ~((3 << 18) << ((cpuno - 1) * 2)); 362 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 363 364 meson8b_mpinit_delay(5000); 365 366 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 367 cpuclk |= (1 << (24 + cpuno)); 368 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 369 370 mempd0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG); 371 mempd0 &= ~((uint32_t)(0xf << 28) >> ((cpuno - 1) * 4)); 372 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG, mempd0); 373 374 pwr_cntl1 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG); 375 pwr_cntl1 &= ~((3 << 4) << ((cpuno - 1) * 2)); 376 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG, pwr_cntl1); 377 378 meson8b_mpinit_delay(10000); 379 380 for (;;) { 381 pwr_cntl1 = bus_space_read_4(bst, ao_bsh, 382 MESON_AOBUS_PWR_CTRL1_REG) & ((1 << 17) << (cpuno - 1)); 383 if (pwr_cntl1) 384 break; 385 meson8b_mpinit_delay(10000); 386 } 387 388 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 389 pwr_cntl0 &= ~(1 << cpuno); 390 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 391 392 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 393 cpuclk &= ~(1 << (24 + cpuno)); 394 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 395 396 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 397 KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 398 399 uint32_t ctrl = bus_space_read_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG); 400 ctrl |= __BITS(cpuno,0); 401 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG, ctrl); 402 403 return 0; 404 } 405 406 ARM_CPU_METHOD(meson8b, "amlogic,meson8b-smp", cpu_enable_meson8b); 407 408 static int 409 meson8b_mpstart(void) 410 { 411 int ret = 0; 412 const bus_addr_t cbar = armreg_cbar_read(); 413 bus_space_tag_t bst = &arm_generic_bs_tag; 414 415 if (cbar == 0) 416 return ret; 417 418 const bus_space_handle_t scu_bsh = 419 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 420 421 const uint32_t scu_cfg = bus_space_read_4(bst, scu_bsh, SCU_CFG); 422 const u_int ncpus = (scu_cfg & SCU_CFG_CPUMAX) + 1; 423 424 if (ncpus < 2) 425 return ret; 426 427 /* 428 * Invalidate all SCU cache tags. That is, for all cores (0-3) 429 */ 430 bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff); 431 432 uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL); 433 scu_ctl |= SCU_CTL_SCU_ENA; 434 bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl); 435 436 armv7_dcache_wbinv_all(); 437 438 ret = arm_fdt_cpu_mpstart(); 439 return ret; 440 } 441 442 static const struct arm_platform meson8b_platform = { 443 .ap_devmap = meson_platform_devmap, 444 .ap_bootstrap = meson8b_platform_bootstrap, 445 .ap_init_attach_args = meson_platform_init_attach_args, 446 .ap_device_register = meson8b_platform_device_register, 447 .ap_reset = meson8b_platform_reset, 448 .ap_delay = a9ptmr_delay, 449 .ap_uart_freq = meson_platform_uart_freq, 450 .ap_mpstart = meson8b_mpstart, 451 }; 452 453 ARM_PLATFORM(meson8b, "amlogic,meson8b", &meson8b_platform); 454 #endif /* SOC_MESON8B */ 455 456 #if defined(SOC_MESONGX) 457 static void 458 mesongx_platform_reset(void) 459 { 460 bus_space_tag_t bst = &meson_bs_tag; 461 bus_space_handle_t bsh; 462 uint32_t val; 463 464 bus_space_map(bst, MESONGX_WATCHDOG_BASE, MESONGX_WATCHDOG_SIZE, 0, &bsh); 465 466 val = MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN | 467 MESONGX_WATCHDOG_CNTL_WDOG_EN | 468 MESONGX_WATCHDOG_CNTL_CLK_EN; 469 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_CNTL, val); 470 471 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_TCNT, 1); 472 473 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_RESET, 0); 474 475 for (;;) { 476 __asm("wfi"); 477 } 478 } 479 480 static const struct arm_platform mesongx_platform = { 481 .ap_devmap = meson_platform_devmap, 482 .ap_bootstrap = meson_platform_bootstrap, 483 .ap_init_attach_args = meson_platform_init_attach_args, 484 .ap_device_register = meson_platform_device_register, 485 .ap_reset = mesongx_platform_reset, 486 .ap_delay = gtmr_delay, 487 .ap_uart_freq = meson_platform_uart_freq, 488 .ap_mpstart = arm_fdt_cpu_mpstart, 489 }; 490 491 #if defined(SOC_MESONGXBB) 492 ARM_PLATFORM(mesongxbb, "amlogic,meson-gxbb", &mesongx_platform); 493 #endif /* SOC_MESONGXBB */ 494 #if defined(SOC_MESONGXL) 495 ARM_PLATFORM(mesongxl, "amlogic,meson-gxl", &mesongx_platform); 496 #endif /* SOC_MESONGXL */ 497 #endif /* SOC_MESONGX */ 498
Indexes created Tue Sep 23 14:10:03 GMT 2025