meson_platform.c revision 1.19
1 /* $NetBSD: meson_platform.c,v 1.19 2021/02/05 08:07:14 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 #include "opt_multiprocessor.h" 31 #include "opt_console.h" 32 33 #include "arml2cc.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.19 2021/02/05 08:07:14 skrll Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 #include <sys/termios.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <arm/fdt/arm_fdtvar.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bootconfig.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/cortex/a9tmr_var.h> 53 #include <arm/cortex/gtmr_var.h> 54 #include <arm/cortex/pl310_var.h> 55 #include <arm/cortex/scu_reg.h> 56 57 #include <arm/amlogic/meson_uart.h> 58 59 #include <evbarm/fdt/platform.h> 60 #include <evbarm/fdt/machdep.h> 61 62 #include <net/if_ether.h> 63 64 #include <libfdt.h> 65 66 #define MESON_CORE_APB3_VBASE KERNEL_IO_VBASE 67 #define MESON_CORE_APB3_PBASE 0xc0000000 68 #define MESON_CORE_APB3_SIZE 0x01400000 69 70 #define MESON_CBUS_OFFSET 0x01100000 71 72 #define MESON8B_WATCHDOG_BASE 0xc1109900 73 #define MESON8B_WATCHDOG_SIZE 0x8 74 #define MESON8B_WATCHDOG_TC 0x00 75 #define MESON8B_WATCHDOG_TC_CPUS __BITS(27,24) 76 #define MESON8B_WATCHDOG_TC_ENABLE __BIT(19) 77 #define MESON8B_WATCHDOG_TC_TCNT __BITS(15,0) 78 #define MESON8B_WATCHDOG_RESET 0x04 79 #define MESON8B_WATCHDOG_RESET_COUNT __BITS(15,0) 80 81 #define MESONGX_WATCHDOG_BASE 0xc11098d0 82 #define MESONGX_WATCHDOG_SIZE 0x10 83 #define MESONGX_WATCHDOG_CNTL 0x00 84 #define MESONGX_WATCHDOG_CNTL_CLK_EN __BIT(24) 85 #define MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN __BIT(21) 86 #define MESONGX_WATCHDOG_CNTL_WDOG_EN __BIT(18) 87 #define MESONGX_WATCHDOG_CNTL1 0x04 88 #define MESONGX_WATCHDOG_TCNT 0x08 89 #define MESONGX_WATCHDOG_TCNT_COUNT __BITS(15,0) 90 #define MESONGX_WATCHDOG_RESET 0x0c 91 92 #define MESON8B_ARM_VBASE (MESON_CORE_APB3_VBASE + MESON_CORE_APB3_SIZE) 93 #define MESON8B_ARM_PBASE 0xc4200000 94 #define MESON8B_ARM_SIZE 0x00200000 95 #define MESON8B_ARM_PL310_BASE 0x00000000 96 #define MESON8B_ARM_SCU_BASE 0x00100000 97 98 #define MESON8B_AOBUS_VBASE (MESON8B_ARM_VBASE + MESON8B_ARM_SIZE) 99 #define MESON8B_AOBUS_PBASE 0xc8000000 100 #define MESON8B_AOBUS_SIZE 0x00200000 101 #define MESON8B_AOBUS_RTI_OFFSET 0x00100000 102 103 #define MESON_AOBUS_PWR_CTRL0_REG 0xe0 104 #define MESON_AOBUS_PWR_CTRL1_REG 0xe4 105 #define MESON_AOBUS_PWR_MEM_PD0_REG 0xf4 106 107 #define MESON_CBUS_CPU_CLK_CNTL_REG 0x419c 108 109 110 #define MESON8B_SRAM_VBASE (MESON8B_AOBUS_VBASE + MESON8B_AOBUS_SIZE) 111 #define MESON8B_SRAM_PBASE 0xd9000000 112 #define MESON8B_SRAM_SIZE 0x00200000 /* 0x10000 rounded up */ 113 114 #define MESON8B_SRAM_CPUCONF_OFFSET 0x1ff80 115 #define MESON8B_SRAM_CPUCONF_CTRL_REG 0x00 116 #define MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(n) (0x04 * (n)) 117 118 119 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 120 extern struct bus_space arm_generic_bs_tag; 121 122 #define meson_dma_tag arm_generic_dma_tag 123 #define meson_bs_tag arm_generic_bs_tag 124 125 static const struct pmap_devmap * 126 meson_platform_devmap(void) 127 { 128 static const struct pmap_devmap devmap[] = { 129 DEVMAP_ENTRY(MESON_CORE_APB3_VBASE, 130 MESON_CORE_APB3_PBASE, 131 MESON_CORE_APB3_SIZE), 132 DEVMAP_ENTRY(MESON8B_ARM_VBASE, 133 MESON8B_ARM_PBASE, 134 MESON8B_ARM_SIZE), 135 DEVMAP_ENTRY(MESON8B_AOBUS_VBASE, 136 MESON8B_AOBUS_PBASE, 137 MESON8B_AOBUS_SIZE), 138 DEVMAP_ENTRY(MESON8B_SRAM_VBASE, 139 MESON8B_SRAM_PBASE, 140 MESON8B_SRAM_SIZE), 141 DEVMAP_ENTRY_END 142 }; 143 144 return devmap; 145 } 146 147 static void 148 meson_platform_init_attach_args(struct fdt_attach_args *faa) 149 { 150 faa->faa_bst = &meson_bs_tag; 151 faa->faa_dmat = &meson_dma_tag; 152 } 153 154 void meson_platform_early_putchar(char); 155 156 void __noasan 157 meson_platform_early_putchar(char c) 158 { 159 #ifdef CONSADDR 160 #define CONSADDR_VA ((CONSADDR - MESON8B_AOBUS_PBASE) + MESON8B_AOBUS_VBASE) 161 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 162 (volatile uint32_t *)CONSADDR_VA : 163 (volatile uint32_t *)CONSADDR; 164 int timo = 150000; 165 166 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 167 if (--timo == 0) 168 break; 169 } 170 171 uartaddr[UART_WFIFO_REG/4] = c; 172 173 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 174 if (--timo == 0) 175 break; 176 } 177 #endif 178 } 179 180 static void 181 meson_platform_device_register(device_t self, void *aux) 182 { 183 prop_dictionary_t dict = device_properties(self); 184 185 fdtbus_device_register(self, aux); 186 187 if (device_is_a(self, "awge") && device_unit(self) == 0) { 188 uint8_t enaddr[ETHER_ADDR_LEN]; 189 if (get_bootconf_option(boot_args, "awge0.mac-address", 190 BOOTOPT_TYPE_MACADDR, enaddr)) { 191 prop_dictionary_set_data(dict, "mac-address", enaddr, 192 sizeof(enaddr)); 193 } 194 } 195 196 if (device_is_a(self, "mesonfb")) { 197 int scale, depth; 198 199 if (get_bootconf_option(boot_args, "fb.scale", 200 BOOTOPT_TYPE_INT, &scale) && scale > 0) { 201 prop_dictionary_set_uint32(dict, "scale", scale); 202 } 203 if (get_bootconf_option(boot_args, "fb.depth", 204 BOOTOPT_TYPE_INT, &depth)) { 205 prop_dictionary_set_uint32(dict, "depth", depth); 206 } 207 } 208 } 209 210 #if defined(SOC_MESON8B) 211 #define MESON8B_BOOTINFO_REG 0xd901ff04 212 static int 213 meson8b_get_boot_id(void) 214 { 215 static int boot_id = -1; 216 bus_space_tag_t bst = &arm_generic_bs_tag; 217 bus_space_handle_t bsh; 218 219 if (boot_id == -1) { 220 if (bus_space_map(bst, MESON8B_BOOTINFO_REG, 4, 0, &bsh) != 0) 221 return -1; 222 223 boot_id = (int)bus_space_read_4(bst, bsh, 0); 224 225 bus_space_unmap(bst, bsh, 4); 226 } 227 228 return boot_id; 229 } 230 231 static void 232 meson8b_platform_device_register(device_t self, void *aux) 233 { 234 device_t parent = device_parent(self); 235 char *ptr; 236 237 fdtbus_device_register(self, aux); 238 239 if (device_is_a(self, "ld") && 240 device_is_a(parent, "sdmmc") && 241 (device_is_a(device_parent(parent), "mesonsdhc") || 242 device_is_a(device_parent(parent), "mesonsdio"))) { 243 244 const int boot_id = meson8b_get_boot_id(); 245 const bool has_rootdev = get_bootconf_option(boot_args, "root", BOOTOPT_TYPE_STRING, &ptr) != 0; 246 247 if (!has_rootdev) { 248 char rootarg[64]; 249 snprintf(rootarg, sizeof(rootarg), " root=%sa", device_xname(self)); 250 251 /* Assume that SDIO is used for SD cards and SDHC is used for eMMC */ 252 if (device_is_a(device_parent(parent), "mesonsdhc") && boot_id == 0) 253 strcat(boot_args, rootarg); 254 else if (device_is_a(device_parent(parent), "mesonsdio") && boot_id != 0) 255 strcat(boot_args, rootarg); 256 } 257 } 258 259 meson_platform_device_register(self, aux); 260 } 261 #endif 262 263 static u_int 264 meson_platform_uart_freq(void) 265 { 266 return 0; 267 } 268 269 static void 270 meson_platform_bootstrap(void) 271 { 272 arm_fdt_cpu_bootstrap(); 273 274 void *fdt_data = __UNCONST(fdtbus_get_data()); 275 const int chosen_off = fdt_path_offset(fdt_data, "/chosen"); 276 if (chosen_off < 0) 277 return; 278 279 if (match_bootconf_option(boot_args, "console", "fb")) { 280 const int framebuffer_off = 281 fdt_path_offset(fdt_data, "/chosen/framebuffer"); 282 if (framebuffer_off >= 0) { 283 const char *status = fdt_getprop(fdt_data, 284 framebuffer_off, "status", NULL); 285 if (status == NULL || strncmp(status, "ok", 2) == 0) { 286 fdt_setprop_string(fdt_data, chosen_off, 287 "stdout-path", "/chosen/framebuffer"); 288 } 289 } 290 } else if (match_bootconf_option(boot_args, "console", "serial")) { 291 fdt_setprop_string(fdt_data, chosen_off, 292 "stdout-path", "serial0:115200n8"); 293 } 294 } 295 296 #if defined(SOC_MESON8B) 297 static void 298 meson8b_platform_bootstrap(void) 299 { 300 301 #if NARML2CC > 0 302 const bus_space_handle_t pl310_bh = MESON8B_ARM_VBASE + MESON8B_ARM_PL310_BASE; 303 arml2cc_init(&arm_generic_bs_tag, pl310_bh, 0); 304 #endif 305 306 meson_platform_bootstrap(); 307 } 308 309 static void 310 meson8b_platform_reset(void) 311 { 312 bus_space_tag_t bst = &meson_bs_tag; 313 bus_space_handle_t bsh; 314 315 bus_space_map(bst, MESON8B_WATCHDOG_BASE, MESON8B_WATCHDOG_SIZE, 0, &bsh); 316 317 bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_TC, 318 MESON8B_WATCHDOG_TC_CPUS | MESON8B_WATCHDOG_TC_ENABLE | __SHIFTIN(0xfff, MESON8B_WATCHDOG_TC_TCNT)); 319 bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_RESET, 0); 320 321 for (;;) { 322 __asm("wfi"); 323 } 324 } 325 326 #ifdef MULTIPROCESSOR 327 static void 328 meson8b_mpinit_delay(u_int n) 329 { 330 for (volatile int i = 0; i < n; i++) 331 ; 332 } 333 #endif 334 335 static int 336 cpu_enable_meson8b(int phandle) 337 { 338 #ifdef MULTIPROCESSOR 339 const bus_addr_t cbar = armreg_cbar_read(); 340 bus_space_tag_t bst = &arm_generic_bs_tag; 341 342 const bus_space_handle_t scu_bsh = 343 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 344 const bus_space_handle_t cpuconf_bsh = 345 MESON8B_SRAM_VBASE + MESON8B_SRAM_CPUCONF_OFFSET; 346 const bus_space_handle_t ao_bsh = 347 MESON8B_AOBUS_VBASE + MESON8B_AOBUS_RTI_OFFSET; 348 const bus_space_handle_t cbus_bsh = 349 MESON_CORE_APB3_VBASE + MESON_CBUS_OFFSET; 350 uint32_t pwr_sts, pwr_cntl0, pwr_cntl1, cpuclk, mempd0; 351 uint64_t mpidr; 352 353 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 354 355 const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0); 356 357 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 358 KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 359 360 pwr_sts = bus_space_read_4(bst, scu_bsh, SCU_CPU_PWR_STS); 361 pwr_sts &= ~(3 << (8 * cpuno)); 362 bus_space_write_4(bst, scu_bsh, SCU_CPU_PWR_STS, pwr_sts); 363 364 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 365 pwr_cntl0 &= ~((3 << 18) << ((cpuno - 1) * 2)); 366 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 367 368 meson8b_mpinit_delay(5000); 369 370 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 371 cpuclk |= (1 << (24 + cpuno)); 372 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 373 374 mempd0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG); 375 mempd0 &= ~((uint32_t)(0xf << 28) >> ((cpuno - 1) * 4)); 376 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG, mempd0); 377 378 pwr_cntl1 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG); 379 pwr_cntl1 &= ~((3 << 4) << ((cpuno - 1) * 2)); 380 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG, pwr_cntl1); 381 382 meson8b_mpinit_delay(10000); 383 384 for (;;) { 385 pwr_cntl1 = bus_space_read_4(bst, ao_bsh, 386 MESON_AOBUS_PWR_CTRL1_REG) & ((1 << 17) << (cpuno - 1)); 387 if (pwr_cntl1) 388 break; 389 meson8b_mpinit_delay(10000); 390 } 391 392 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 393 pwr_cntl0 &= ~(1 << cpuno); 394 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 395 396 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 397 cpuclk &= ~(1 << (24 + cpuno)); 398 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 399 400 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 401 KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 402 403 uint32_t ctrl = bus_space_read_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG); 404 ctrl |= __BITS(cpuno,0); 405 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG, ctrl); 406 #endif 407 408 return 0; 409 } 410 411 ARM_CPU_METHOD(meson8b, "amlogic,meson8b-smp", cpu_enable_meson8b); 412 413 static int 414 meson8b_mpstart(void) 415 { 416 int ret = 0; 417 const bus_addr_t cbar = armreg_cbar_read(); 418 bus_space_tag_t bst = &arm_generic_bs_tag; 419 420 if (cbar == 0) 421 return ret; 422 423 const bus_space_handle_t scu_bsh = 424 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 425 426 const uint32_t scu_cfg = bus_space_read_4(bst, scu_bsh, SCU_CFG); 427 const u_int ncpus = (scu_cfg & SCU_CFG_CPUMAX) + 1; 428 429 if (ncpus < 2) 430 return ret; 431 432 /* 433 * Invalidate all SCU cache tags. That is, for all cores (0-3) 434 */ 435 bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff); 436 437 uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL); 438 scu_ctl |= SCU_CTL_SCU_ENA; 439 bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl); 440 441 armv7_dcache_wbinv_all(); 442 443 ret = arm_fdt_cpu_mpstart(); 444 return ret; 445 } 446 447 static const struct arm_platform meson8b_platform = { 448 .ap_devmap = meson_platform_devmap, 449 .ap_bootstrap = meson8b_platform_bootstrap, 450 .ap_init_attach_args = meson_platform_init_attach_args, 451 .ap_device_register = meson8b_platform_device_register, 452 .ap_reset = meson8b_platform_reset, 453 .ap_delay = a9ptmr_delay, 454 .ap_uart_freq = meson_platform_uart_freq, 455 .ap_mpstart = meson8b_mpstart, 456 }; 457 458 ARM_PLATFORM(meson8b, "amlogic,meson8b", &meson8b_platform); 459 #endif /* SOC_MESON8B */ 460 461 #if defined(SOC_MESONGX) 462 static void 463 mesongx_platform_reset(void) 464 { 465 bus_space_tag_t bst = &meson_bs_tag; 466 bus_space_handle_t bsh; 467 uint32_t val; 468 469 bus_space_map(bst, MESONGX_WATCHDOG_BASE, MESONGX_WATCHDOG_SIZE, 0, &bsh); 470 471 val = MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN | 472 MESONGX_WATCHDOG_CNTL_WDOG_EN | 473 MESONGX_WATCHDOG_CNTL_CLK_EN; 474 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_CNTL, val); 475 476 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_TCNT, 1); 477 478 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_RESET, 0); 479 480 for (;;) { 481 __asm("wfi"); 482 } 483 } 484 485 static const struct arm_platform mesongx_platform = { 486 .ap_devmap = meson_platform_devmap, 487 .ap_bootstrap = meson_platform_bootstrap, 488 .ap_init_attach_args = meson_platform_init_attach_args, 489 .ap_device_register = meson_platform_device_register, 490 .ap_reset = mesongx_platform_reset, 491 .ap_delay = gtmr_delay, 492 .ap_uart_freq = meson_platform_uart_freq, 493 .ap_mpstart = arm_fdt_cpu_mpstart, 494 }; 495 496 #if defined(SOC_MESONGXBB) 497 ARM_PLATFORM(mesongxbb, "amlogic,meson-gxbb", &mesongx_platform); 498 #endif /* SOC_MESONGXBB */ 499 #if defined(SOC_MESONGXL) 500 ARM_PLATFORM(mesongxl, "amlogic,meson-gxl", &mesongx_platform); 501 #endif /* SOC_MESONGXL */ 502 #endif /* SOC_MESONGX */ 503
Indexes created Tue Sep 30 20:09:53 GMT 2025