meson_platform.c revision 1.22
1 /* $NetBSD: meson_platform.c,v 1.22 2025/09/06 21:02:40 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 #include "opt_multiprocessor.h" 31 #include "opt_console.h" 32 33 #include "arml2cc.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.22 2025/09/06 21:02:40 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 #include <sys/termios.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <dev/fdt/fdt_platform.h> 46 47 #include <arm/fdt/arm_fdtvar.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/bootconfig.h> 52 #include <arm/cpufunc.h> 53 54 #include <arm/cortex/a9tmr_var.h> 55 #include <arm/cortex/gtmr_var.h> 56 #include <arm/cortex/pl310_var.h> 57 #include <arm/cortex/scu_reg.h> 58 59 #include <arm/amlogic/meson_uart.h> 60 61 #include <evbarm/fdt/platform.h> 62 #include <evbarm/fdt/machdep.h> 63 64 #include <net/if_ether.h> 65 66 #include <libfdt.h> 67 68 #define MESON_CORE_APB3_VBASE KERNEL_IO_VBASE 69 #define MESON_CORE_APB3_PBASE 0xc0000000 70 #define MESON_CORE_APB3_SIZE 0x01400000 71 72 #define MESON_CBUS_OFFSET 0x01100000 73 74 #define MESON8B_WATCHDOG_BASE 0xc1109900 75 #define MESON8B_WATCHDOG_SIZE 0x8 76 #define MESON8B_WATCHDOG_TC 0x00 77 #define MESON8B_WATCHDOG_TC_CPUS __BITS(27,24) 78 #define MESON8B_WATCHDOG_TC_ENABLE __BIT(19) 79 #define MESON8B_WATCHDOG_TC_TCNT __BITS(15,0) 80 #define MESON8B_WATCHDOG_RESET 0x04 81 #define MESON8B_WATCHDOG_RESET_COUNT __BITS(15,0) 82 83 #define MESONGX_WATCHDOG_BASE 0xc11098d0 84 #define MESONGX_WATCHDOG_SIZE 0x10 85 #define MESONGX_WATCHDOG_CNTL 0x00 86 #define MESONGX_WATCHDOG_CNTL_CLK_EN __BIT(24) 87 #define MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN __BIT(21) 88 #define MESONGX_WATCHDOG_CNTL_WDOG_EN __BIT(18) 89 #define MESONGX_WATCHDOG_CNTL1 0x04 90 #define MESONGX_WATCHDOG_TCNT 0x08 91 #define MESONGX_WATCHDOG_TCNT_COUNT __BITS(15,0) 92 #define MESONGX_WATCHDOG_RESET 0x0c 93 94 #define MESON8B_ARM_VBASE (MESON_CORE_APB3_VBASE + MESON_CORE_APB3_SIZE) 95 #define MESON8B_ARM_PBASE 0xc4200000 96 #define MESON8B_ARM_SIZE 0x00200000 97 #define MESON8B_ARM_PL310_BASE 0x00000000 98 #define MESON8B_ARM_SCU_BASE 0x00100000 99 100 #define MESON8B_AOBUS_VBASE (MESON8B_ARM_VBASE + MESON8B_ARM_SIZE) 101 #define MESON8B_AOBUS_PBASE 0xc8000000 102 #define MESON8B_AOBUS_SIZE 0x00200000 103 #define MESON8B_AOBUS_RTI_OFFSET 0x00100000 104 105 #define MESON_AOBUS_PWR_CTRL0_REG 0xe0 106 #define MESON_AOBUS_PWR_CTRL1_REG 0xe4 107 #define MESON_AOBUS_PWR_MEM_PD0_REG 0xf4 108 109 #define MESON_CBUS_CPU_CLK_CNTL_REG 0x419c 110 111 112 #define MESON8B_SRAM_VBASE (MESON8B_AOBUS_VBASE + MESON8B_AOBUS_SIZE) 113 #define MESON8B_SRAM_PBASE 0xd9000000 114 #define MESON8B_SRAM_SIZE 0x00200000 /* 0x10000 rounded up */ 115 116 #define MESON8B_SRAM_CPUCONF_OFFSET 0x1ff80 117 #define MESON8B_SRAM_CPUCONF_CTRL_REG 0x00 118 #define MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(n) (0x04 * (n)) 119 120 121 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 122 extern struct bus_space arm_generic_bs_tag; 123 124 #define meson_dma_tag arm_generic_dma_tag 125 #define meson_bs_tag arm_generic_bs_tag 126 127 static const struct pmap_devmap * 128 meson_platform_devmap(void) 129 { 130 static const struct pmap_devmap devmap[] = { 131 DEVMAP_ENTRY(MESON_CORE_APB3_VBASE, 132 MESON_CORE_APB3_PBASE, 133 MESON_CORE_APB3_SIZE), 134 DEVMAP_ENTRY(MESON8B_ARM_VBASE, 135 MESON8B_ARM_PBASE, 136 MESON8B_ARM_SIZE), 137 DEVMAP_ENTRY(MESON8B_AOBUS_VBASE, 138 MESON8B_AOBUS_PBASE, 139 MESON8B_AOBUS_SIZE), 140 DEVMAP_ENTRY(MESON8B_SRAM_VBASE, 141 MESON8B_SRAM_PBASE, 142 MESON8B_SRAM_SIZE), 143 DEVMAP_ENTRY_END 144 }; 145 146 return devmap; 147 } 148 149 static void 150 meson_platform_init_attach_args(struct fdt_attach_args *faa) 151 { 152 faa->faa_bst = &meson_bs_tag; 153 faa->faa_dmat = &meson_dma_tag; 154 } 155 156 void meson_platform_early_putchar(char); 157 158 void __noasan 159 meson_platform_early_putchar(char c) 160 { 161 #ifdef CONSADDR 162 #define CONSADDR_VA ((CONSADDR - MESON8B_AOBUS_PBASE) + MESON8B_AOBUS_VBASE) 163 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 164 (volatile uint32_t *)CONSADDR_VA : 165 (volatile uint32_t *)CONSADDR; 166 int timo = 150000; 167 168 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 169 if (--timo == 0) 170 break; 171 } 172 173 uartaddr[UART_WFIFO_REG/4] = c; 174 175 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 176 if (--timo == 0) 177 break; 178 } 179 #endif 180 } 181 182 static void 183 meson_platform_device_register(device_t self, void *aux) 184 { 185 prop_dictionary_t dict = device_properties(self); 186 187 if (device_is_a(self, "awge") && device_unit(self) == 0) { 188 uint8_t enaddr[ETHER_ADDR_LEN]; 189 if (get_bootconf_option(boot_args, "awge0.mac-address", 190 BOOTOPT_TYPE_MACADDR, enaddr)) { 191 prop_dictionary_set_data(dict, "mac-address", enaddr, 192 sizeof(enaddr)); 193 } 194 } 195 196 if (device_is_a(self, "mesonfb")) { 197 int scale, depth; 198 199 if (get_bootconf_option(boot_args, "fb.scale", 200 BOOTOPT_TYPE_INT, &scale) && scale > 0) { 201 prop_dictionary_set_uint32(dict, "scale", scale); 202 } 203 if (get_bootconf_option(boot_args, "fb.depth", 204 BOOTOPT_TYPE_INT, &depth)) { 205 prop_dictionary_set_uint32(dict, "depth", depth); 206 } 207 } 208 } 209 210 #if defined(SOC_MESON8B) 211 #define MESON8B_BOOTINFO_REG 0xd901ff04 212 static int 213 meson8b_get_boot_id(void) 214 { 215 static int boot_id = -1; 216 bus_space_tag_t bst = &arm_generic_bs_tag; 217 bus_space_handle_t bsh; 218 219 if (boot_id == -1) { 220 if (bus_space_map(bst, MESON8B_BOOTINFO_REG, 4, 0, &bsh) != 0) 221 return -1; 222 223 boot_id = (int)bus_space_read_4(bst, bsh, 0); 224 225 bus_space_unmap(bst, bsh, 4); 226 } 227 228 return boot_id; 229 } 230 231 static void 232 meson8b_platform_device_register(device_t self, void *aux) 233 { 234 device_t parent = device_parent(self); 235 char *ptr; 236 237 if (device_is_a(self, "ld") && 238 device_is_a(parent, "sdmmc") && 239 (device_is_a(device_parent(parent), "mesonsdhc") || 240 device_is_a(device_parent(parent), "mesonsdio"))) { 241 242 const int boot_id = meson8b_get_boot_id(); 243 const bool has_rootdev = get_bootconf_option(boot_args, "root", BOOTOPT_TYPE_STRING, &ptr) != 0; 244 245 if (!has_rootdev) { 246 char rootarg[64]; 247 snprintf(rootarg, sizeof(rootarg), " root=%sa", device_xname(self)); 248 249 /* Assume that SDIO is used for SD cards and SDHC is used for eMMC */ 250 if (device_is_a(device_parent(parent), "mesonsdhc") && boot_id == 0) 251 strcat(boot_args, rootarg); 252 else if (device_is_a(device_parent(parent), "mesonsdio") && boot_id != 0) 253 strcat(boot_args, rootarg); 254 } 255 } 256 257 meson_platform_device_register(self, aux); 258 } 259 #endif 260 261 static u_int 262 meson_platform_uart_freq(void) 263 { 264 return 0; 265 } 266 267 static void 268 meson_platform_bootstrap(void) 269 { 270 arm_fdt_cpu_bootstrap(); 271 272 void *fdt_data = __UNCONST(fdtbus_get_data()); 273 const int chosen_off = fdt_path_offset(fdt_data, "/chosen"); 274 if (chosen_off < 0) 275 return; 276 277 if (match_bootconf_option(boot_args, "console", "fb")) { 278 const int framebuffer_off = 279 fdt_path_offset(fdt_data, "/chosen/framebuffer"); 280 if (framebuffer_off >= 0) { 281 const char *status = fdt_getprop(fdt_data, 282 framebuffer_off, "status", NULL); 283 if (status == NULL || strncmp(status, "ok", 2) == 0) { 284 fdt_setprop_string(fdt_data, chosen_off, 285 "stdout-path", "/chosen/framebuffer"); 286 } 287 } 288 } else if (match_bootconf_option(boot_args, "console", "serial")) { 289 fdt_setprop_string(fdt_data, chosen_off, 290 "stdout-path", "serial0:115200n8"); 291 } 292 } 293 294 #if defined(SOC_MESON8B) 295 static void 296 meson8b_platform_bootstrap(void) 297 { 298 299 #if NARML2CC > 0 300 const bus_space_handle_t pl310_bh = MESON8B_ARM_VBASE + MESON8B_ARM_PL310_BASE; 301 arml2cc_init(&arm_generic_bs_tag, pl310_bh, 0); 302 #endif 303 304 meson_platform_bootstrap(); 305 } 306 307 static void 308 meson8b_platform_reset(void) 309 { 310 bus_space_tag_t bst = &meson_bs_tag; 311 bus_space_handle_t bsh; 312 313 bus_space_map(bst, MESON8B_WATCHDOG_BASE, MESON8B_WATCHDOG_SIZE, 0, &bsh); 314 315 bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_TC, 316 MESON8B_WATCHDOG_TC_CPUS | MESON8B_WATCHDOG_TC_ENABLE | __SHIFTIN(0xfff, MESON8B_WATCHDOG_TC_TCNT)); 317 bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_RESET, 0); 318 319 for (;;) { 320 __asm("wfi"); 321 } 322 } 323 324 #ifdef MULTIPROCESSOR 325 static void 326 meson8b_mpinit_delay(u_int n) 327 { 328 for (volatile int i = 0; i < n; i++) 329 ; 330 } 331 #endif 332 333 static int 334 cpu_enable_meson8b(int phandle) 335 { 336 #ifdef MULTIPROCESSOR 337 const bus_addr_t cbar = armreg_cbar_read(); 338 bus_space_tag_t bst = &arm_generic_bs_tag; 339 340 const bus_space_handle_t scu_bsh = 341 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 342 const bus_space_handle_t cpuconf_bsh = 343 MESON8B_SRAM_VBASE + MESON8B_SRAM_CPUCONF_OFFSET; 344 const bus_space_handle_t ao_bsh = 345 MESON8B_AOBUS_VBASE + MESON8B_AOBUS_RTI_OFFSET; 346 const bus_space_handle_t cbus_bsh = 347 MESON_CORE_APB3_VBASE + MESON_CBUS_OFFSET; 348 uint32_t pwr_sts, pwr_cntl0, pwr_cntl1, cpuclk, mempd0; 349 uint64_t mpidr; 350 351 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 352 353 const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0); 354 355 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 356 KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 357 358 pwr_sts = bus_space_read_4(bst, scu_bsh, SCU_CPU_PWR_STS); 359 pwr_sts &= ~(3 << (8 * cpuno)); 360 bus_space_write_4(bst, scu_bsh, SCU_CPU_PWR_STS, pwr_sts); 361 362 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 363 pwr_cntl0 &= ~((3 << 18) << ((cpuno - 1) * 2)); 364 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 365 366 meson8b_mpinit_delay(5000); 367 368 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 369 cpuclk |= (1 << (24 + cpuno)); 370 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 371 372 mempd0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG); 373 mempd0 &= ~((uint32_t)(0xf << 28) >> ((cpuno - 1) * 4)); 374 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG, mempd0); 375 376 pwr_cntl1 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG); 377 pwr_cntl1 &= ~((3 << 4) << ((cpuno - 1) * 2)); 378 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG, pwr_cntl1); 379 380 meson8b_mpinit_delay(10000); 381 382 for (;;) { 383 pwr_cntl1 = bus_space_read_4(bst, ao_bsh, 384 MESON_AOBUS_PWR_CTRL1_REG) & ((1 << 17) << (cpuno - 1)); 385 if (pwr_cntl1) 386 break; 387 meson8b_mpinit_delay(10000); 388 } 389 390 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 391 pwr_cntl0 &= ~(1 << cpuno); 392 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 393 394 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 395 cpuclk &= ~(1 << (24 + cpuno)); 396 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 397 398 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 399 KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 400 401 uint32_t ctrl = bus_space_read_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG); 402 ctrl |= __BITS(cpuno,0); 403 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG, ctrl); 404 #endif 405 406 return 0; 407 } 408 409 ARM_CPU_METHOD(meson8b, "amlogic,meson8b-smp", cpu_enable_meson8b); 410 411 static int 412 meson8b_mpstart(void) 413 { 414 int ret = 0; 415 const bus_addr_t cbar = armreg_cbar_read(); 416 bus_space_tag_t bst = &arm_generic_bs_tag; 417 418 if (cbar == 0) 419 return ret; 420 421 const bus_space_handle_t scu_bsh = 422 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 423 424 const uint32_t scu_cfg = bus_space_read_4(bst, scu_bsh, SCU_CFG); 425 const u_int ncpus = (scu_cfg & SCU_CFG_CPUMAX) + 1; 426 427 if (ncpus < 2) 428 return ret; 429 430 /* 431 * Invalidate all SCU cache tags. That is, for all cores (0-3) 432 */ 433 bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff); 434 435 uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL); 436 scu_ctl |= SCU_CTL_SCU_ENA; 437 bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl); 438 439 armv7_dcache_wbinv_all(); 440 441 ret = arm_fdt_cpu_mpstart(); 442 return ret; 443 } 444 445 static const struct fdt_platform meson8b_platform = { 446 .fp_devmap = meson_platform_devmap, 447 .fp_bootstrap = meson8b_platform_bootstrap, 448 .fp_init_attach_args = meson_platform_init_attach_args, 449 .fp_device_register = meson8b_platform_device_register, 450 .fp_reset = meson8b_platform_reset, 451 .fp_delay = a9ptmr_delay, 452 .fp_uart_freq = meson_platform_uart_freq, 453 .fp_mpstart = meson8b_mpstart, 454 }; 455 456 FDT_PLATFORM(meson8b, "amlogic,meson8b", &meson8b_platform); 457 #endif /* SOC_MESON8B */ 458 459 #if defined(SOC_MESONGX) 460 static void 461 mesongx_platform_reset(void) 462 { 463 bus_space_tag_t bst = &meson_bs_tag; 464 bus_space_handle_t bsh; 465 uint32_t val; 466 467 bus_space_map(bst, MESONGX_WATCHDOG_BASE, MESONGX_WATCHDOG_SIZE, 0, &bsh); 468 469 val = MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN | 470 MESONGX_WATCHDOG_CNTL_WDOG_EN | 471 MESONGX_WATCHDOG_CNTL_CLK_EN; 472 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_CNTL, val); 473 474 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_TCNT, 1); 475 476 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_RESET, 0); 477 478 for (;;) { 479 __asm("wfi"); 480 } 481 } 482 483 static const struct fdt_platform mesongx_platform = { 484 .fp_devmap = meson_platform_devmap, 485 .fp_bootstrap = meson_platform_bootstrap, 486 .fp_init_attach_args = meson_platform_init_attach_args, 487 .fp_device_register = meson_platform_device_register, 488 .fp_reset = mesongx_platform_reset, 489 .fp_delay = gtmr_delay, 490 .fp_uart_freq = meson_platform_uart_freq, 491 .fp_mpstart = arm_fdt_cpu_mpstart, 492 }; 493 494 #if defined(SOC_MESONGXBB) 495 FDT_PLATFORM(mesongxbb, "amlogic,meson-gxbb", &mesongx_platform); 496 #endif /* SOC_MESONGXBB */ 497 #if defined(SOC_MESONGXL) 498 FDT_PLATFORM(mesongxl, "amlogic,meson-gxl", &mesongx_platform); 499 #endif /* SOC_MESONGXL */ 500 #endif /* SOC_MESONGX */ 501
Indexes created Tue Sep 23 23:09:58 GMT 2025