meson_platform.c revision 1.3.2.2
1 /* $NetBSD: meson_platform.c,v 1.3.2.2 2019/01/26 21:59:59 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 #include "opt_multiprocessor.h" 31 #include "opt_console.h" 32 33 #include "arml2cc.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.3.2.2 2019/01/26 21:59:59 pgoyette Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 #include <sys/termios.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <arm/fdt/arm_fdtvar.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bootconfig.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/cortex/a9tmr_var.h> 53 #include <arm/cortex/pl310_var.h> 54 #include <arm/cortex/scu_reg.h> 55 56 #include <arm/amlogic/meson_uart.h> 57 58 #include <evbarm/fdt/platform.h> 59 #include <evbarm/fdt/machdep.h> 60 61 #include <net/if_ether.h> 62 63 #include <libfdt.h> 64 65 #define MESON_CORE_APB3_VBASE KERNEL_IO_VBASE 66 #define MESON_CORE_APB3_PBASE 0xc0000000 67 #define MESON_CORE_APB3_SIZE 0x01300000 68 69 #define MESON_CBUS_OFFSET 0x01100000 70 71 #define MESON_WATCHDOG_BASE 0xc1109900 72 #define MESON_WATCHDOG_SIZE 0x8 73 #define MESON_WATCHDOG_TC 0x00 74 #define WATCHDOG_TC_CPUS __BITS(27,24) 75 #define WATCHDOG_TC_ENABLE __BIT(19) 76 #define WATCHDOG_TC_TCNT __BITS(15,0) 77 #define MESON_WATCHDOG_RESET 0x04 78 #define WATCHDOG_RESET_COUNT __BITS(15,0) 79 80 #define MESON8B_ARM_VBASE (MESON_CORE_APB3_VBASE + MESON_CORE_APB3_SIZE) 81 #define MESON8B_ARM_PBASE 0xc4200000 82 #define MESON8B_ARM_SIZE 0x00200000 83 #define MESON8B_ARM_PL310_BASE 0x00000000 84 #define MESON8B_ARM_SCU_BASE 0x00100000 85 86 #define MESON8B_AOBUS_VBASE (MESON8B_ARM_VBASE + MESON8B_ARM_SIZE) 87 #define MESON8B_AOBUS_PBASE 0xc8100000 88 #define MESON8B_AOBUS_SIZE 0x00100000 89 90 #define MESON_AOBUS_PWR_CTRL0_REG 0xe0 91 #define MESON_AOBUS_PWR_CTRL1_REG 0xe4 92 #define MESON_AOBUS_PWR_MEM_PD0_REG 0xf4 93 94 #define MESON_CBUS_CPU_CLK_CNTL_REG 0x419c 95 96 97 #define MESON8B_SRAM_VBASE (MESON8B_AOBUS_VBASE + MESON8B_AOBUS_SIZE) 98 #define MESON8B_SRAM_PBASE 0xd9000000 99 #define MESON8B_SRAM_SIZE 0x00010000 /* 0x10000 rounded up */ 100 101 #define MESON8B_SRAM_CPUCONF_OFFSET 0x1ff80 102 #define MESON8B_SRAM_CPUCONF_CTRL_REG 0x00 103 #define MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(n) (0x04 * (n)) 104 105 106 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 107 extern struct bus_space arm_generic_bs_tag; 108 extern struct bus_space arm_generic_a4x_bs_tag; 109 110 #define meson_dma_tag arm_generic_dma_tag 111 #define meson_bs_tag arm_generic_bs_tag 112 #define meson_a4x_bs_tag arm_generic_a4x_bs_tag 113 114 static const struct pmap_devmap * 115 meson_platform_devmap(void) 116 { 117 static const struct pmap_devmap devmap[] = { 118 DEVMAP_ENTRY(MESON_CORE_APB3_VBASE, 119 MESON_CORE_APB3_PBASE, 120 MESON_CORE_APB3_SIZE), 121 DEVMAP_ENTRY(MESON8B_ARM_VBASE, 122 MESON8B_ARM_PBASE, 123 MESON8B_ARM_SIZE), 124 DEVMAP_ENTRY(MESON8B_AOBUS_VBASE, 125 MESON8B_AOBUS_PBASE, 126 MESON8B_AOBUS_SIZE), 127 DEVMAP_ENTRY(MESON8B_SRAM_VBASE, 128 MESON8B_SRAM_PBASE, 129 MESON8B_SRAM_SIZE), 130 DEVMAP_ENTRY_END 131 }; 132 133 return devmap; 134 } 135 136 static void 137 meson_platform_init_attach_args(struct fdt_attach_args *faa) 138 { 139 faa->faa_bst = &meson_bs_tag; 140 faa->faa_a4x_bst = &meson_a4x_bs_tag; 141 faa->faa_dmat = &meson_dma_tag; 142 } 143 144 void meson_platform_early_putchar(char); 145 146 void 147 meson_platform_early_putchar(char c) 148 { 149 #ifdef CONSADDR 150 #define CONSADDR_VA ((CONSADDR - MESON8B_AOBUS_PBASE) + MESON8B_AOBUS_VBASE) 151 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 152 (volatile uint32_t *)CONSADDR_VA : 153 (volatile uint32_t *)CONSADDR; 154 int timo = 150000; 155 156 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 157 if (--timo == 0) 158 break; 159 } 160 161 uartaddr[UART_WFIFO_REG/4] = c; 162 163 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) { 164 if (--timo == 0) 165 break; 166 } 167 #endif 168 } 169 170 static void 171 meson_platform_device_register(device_t self, void *aux) 172 { 173 prop_dictionary_t dict = device_properties(self); 174 175 if (device_is_a(self, "awge") && device_unit(self) == 0) { 176 uint8_t enaddr[ETHER_ADDR_LEN]; 177 if (get_bootconf_option(boot_args, "awge0.mac-address", 178 BOOTOPT_TYPE_MACADDR, enaddr)) { 179 prop_data_t pd = prop_data_create_data(enaddr, 180 sizeof(enaddr)); 181 prop_dictionary_set(dict, "mac-address", pd); 182 prop_object_release(pd); 183 } 184 } 185 186 if (device_is_a(self, "genfb")) { 187 int scale, depth; 188 189 if (get_bootconf_option(boot_args, "fb.scale", 190 BOOTOPT_TYPE_INT, &scale) && scale > 0) { 191 prop_dictionary_set_uint32(dict, "scale", scale); 192 } 193 if (get_bootconf_option(boot_args, "fb.depth", 194 BOOTOPT_TYPE_INT, &depth)) { 195 prop_dictionary_set_uint32(dict, "depth", depth); 196 } 197 } 198 } 199 200 #if defined(SOC_MESON8B) 201 #define MESON8B_BOOTINFO_REG 0xd901ff04 202 static int 203 meson8b_get_boot_id(void) 204 { 205 static int boot_id = -1; 206 bus_space_tag_t bst = &arm_generic_bs_tag; 207 bus_space_handle_t bsh; 208 209 if (boot_id == -1) { 210 if (bus_space_map(bst, MESON8B_BOOTINFO_REG, 4, 0, &bsh) != 0) 211 return -1; 212 213 boot_id = (int)bus_space_read_4(bst, bsh, 0); 214 215 bus_space_unmap(bst, bsh, 4); 216 } 217 218 return boot_id; 219 } 220 221 static void 222 meson8b_platform_device_register(device_t self, void *aux) 223 { 224 device_t parent = device_parent(self); 225 char *ptr; 226 227 if (device_is_a(self, "ld") && 228 device_is_a(parent, "sdmmc") && 229 (device_is_a(device_parent(parent), "mesonsdhc") || 230 device_is_a(device_parent(parent), "mesonsdio"))) { 231 232 const int boot_id = meson8b_get_boot_id(); 233 const bool has_rootdev = get_bootconf_option(boot_args, "root", BOOTOPT_TYPE_STRING, &ptr) != 0; 234 235 if (!has_rootdev) { 236 char rootarg[64]; 237 snprintf(rootarg, sizeof(rootarg), " root=%sa", device_xname(self)); 238 239 /* Assume that SDIO is used for SD cards and SDHC is used for eMMC */ 240 if (device_is_a(device_parent(parent), "mesonsdhc") && boot_id == 0) 241 strcat(boot_args, rootarg); 242 else if (device_is_a(device_parent(parent), "mesonsdio") && boot_id != 0) 243 strcat(boot_args, rootarg); 244 } 245 } 246 247 meson_platform_device_register(self, aux); 248 } 249 #endif 250 251 static u_int 252 meson_platform_uart_freq(void) 253 { 254 return 0; 255 } 256 257 static void 258 meson_platform_bootstrap(void) 259 { 260 arm_fdt_cpu_bootstrap(); 261 262 void *fdt_data = __UNCONST(fdtbus_get_data()); 263 const int chosen_off = fdt_path_offset(fdt_data, "/chosen"); 264 if (chosen_off < 0) 265 return; 266 267 if (match_bootconf_option(boot_args, "console", "fb")) { 268 const int framebuffer_off = 269 fdt_path_offset(fdt_data, "/chosen/framebuffer"); 270 if (framebuffer_off >= 0) { 271 const char *status = fdt_getprop(fdt_data, 272 framebuffer_off, "status", NULL); 273 if (status == NULL || strncmp(status, "ok", 2) == 0) { 274 fdt_setprop_string(fdt_data, chosen_off, 275 "stdout-path", "/chosen/framebuffer"); 276 } 277 } 278 } else if (match_bootconf_option(boot_args, "console", "serial")) { 279 fdt_setprop_string(fdt_data, chosen_off, 280 "stdout-path", "serial0:115200n8"); 281 } 282 } 283 284 #if defined(SOC_MESON8B) 285 static void 286 meson8b_platform_bootstrap(void) 287 { 288 289 #if NARML2CC > 0 290 const bus_space_handle_t pl310_bh = MESON8B_ARM_VBASE + MESON8B_ARM_PL310_BASE; 291 arml2cc_init(&arm_generic_bs_tag, pl310_bh, 0); 292 #endif 293 294 meson_platform_bootstrap(); 295 } 296 #endif 297 298 static void 299 meson_platform_reset(void) 300 { 301 bus_space_tag_t bst = &meson_bs_tag; 302 bus_space_handle_t bsh; 303 304 bus_space_map(bst, MESON_WATCHDOG_BASE, MESON_WATCHDOG_SIZE, 0, &bsh); 305 306 bus_space_write_4(bst, bsh, MESON_WATCHDOG_TC, 307 WATCHDOG_TC_CPUS | WATCHDOG_TC_ENABLE | __SHIFTIN(0xfff, WATCHDOG_TC_TCNT)); 308 bus_space_write_4(bst, bsh, MESON_WATCHDOG_RESET, 0); 309 310 for (;;) { 311 __asm("wfi"); 312 } 313 } 314 315 #if defined(MULTIPROCESSOR) 316 static void 317 meson8b_mpinit_delay(u_int n) 318 { 319 for (volatile int i = 0; i < n; i++) 320 ; 321 } 322 323 static int 324 cpu_enable_meson8b(int phandle) 325 { 326 const bus_addr_t cbar = armreg_cbar_read(); 327 bus_space_tag_t bst = &arm_generic_bs_tag; 328 329 const bus_space_handle_t scu_bsh = 330 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 331 const bus_space_handle_t cpuconf_bsh = 332 MESON8B_SRAM_VBASE + MESON8B_SRAM_CPUCONF_OFFSET; 333 const bus_space_handle_t ao_bsh = 334 MESON8B_AOBUS_VBASE; 335 const bus_space_handle_t cbus_bsh = 336 MESON_CORE_APB3_VBASE + MESON_CBUS_OFFSET; 337 uint32_t pwr_sts, pwr_cntl0, pwr_cntl1, cpuclk, mempd0; 338 uint64_t mpidr; 339 340 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 341 342 const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0); 343 344 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 345 KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 346 347 pwr_sts = bus_space_read_4(bst, scu_bsh, SCU_CPU_PWR_STS); 348 pwr_sts &= ~(3 << (8 * cpuno)); 349 bus_space_write_4(bst, scu_bsh, SCU_CPU_PWR_STS, pwr_sts); 350 351 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 352 pwr_cntl0 &= ~((3 << 18) << ((cpuno - 1) * 2)); 353 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 354 355 meson8b_mpinit_delay(5000); 356 357 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 358 cpuclk |= (1 << (24 + cpuno)); 359 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 360 361 mempd0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG); 362 mempd0 &= ~((uint32_t)(0xf << 28) >> ((cpuno - 1) * 4)); 363 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG, mempd0); 364 365 pwr_cntl1 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG); 366 pwr_cntl1 &= ~((3 << 4) << ((cpuno - 1) * 2)); 367 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG, pwr_cntl1); 368 369 meson8b_mpinit_delay(10000); 370 371 for (;;) { 372 pwr_cntl1 = bus_space_read_4(bst, ao_bsh, 373 MESON_AOBUS_PWR_CTRL1_REG) & ((1 << 17) << (cpuno - 1)); 374 if (pwr_cntl1) 375 break; 376 meson8b_mpinit_delay(10000); 377 } 378 379 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG); 380 pwr_cntl0 &= ~(1 << cpuno); 381 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0); 382 383 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG); 384 cpuclk &= ~(1 << (24 + cpuno)); 385 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk); 386 387 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno), 388 KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 389 390 uint32_t ctrl = bus_space_read_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG); 391 ctrl |= __BITS(cpuno,0); 392 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG, ctrl); 393 394 return 0; 395 } 396 397 ARM_CPU_METHOD(meson8b, "amlogic,meson8b-smp", cpu_enable_meson8b); 398 #endif 399 400 static void 401 meson_mpstart(void) 402 { 403 #ifdef MULTIPROCESSOR 404 const bus_addr_t cbar = armreg_cbar_read(); 405 bus_space_tag_t bst = &arm_generic_bs_tag; 406 407 if (cbar == 0) 408 return; 409 410 const bus_space_handle_t scu_bsh = 411 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE; 412 413 const uint32_t scu_cfg = bus_space_read_4(bst, scu_bsh, SCU_CFG); 414 const u_int ncpus = (scu_cfg & SCU_CFG_CPUMAX) + 1; 415 416 if (ncpus < 2) 417 return; 418 419 /* 420 * Invalidate all SCU cache tags. That is, for all cores (0-3) 421 */ 422 bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff); 423 424 uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL); 425 scu_ctl |= SCU_CTL_SCU_ENA; 426 bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl); 427 428 armv7_dcache_wbinv_all(); 429 430 arm_fdt_cpu_mpstart(); 431 #endif 432 } 433 434 435 #if defined(SOC_MESON8B) 436 static const struct arm_platform meson8b_platform = { 437 .ap_devmap = meson_platform_devmap, 438 .ap_bootstrap = meson8b_platform_bootstrap, 439 .ap_init_attach_args = meson_platform_init_attach_args, 440 .ap_device_register = meson8b_platform_device_register, 441 .ap_reset = meson_platform_reset, 442 .ap_delay = a9tmr_delay, 443 .ap_uart_freq = meson_platform_uart_freq, 444 .ap_mpstart = meson_mpstart, 445 }; 446 447 ARM_PLATFORM(meson8b, "amlogic,meson8b", &meson8b_platform); 448 #endif 449
Indexes created Tue Sep 30 20:09:53 GMT 2025