meson_sdhc.c revision 1.1
1 /* $NetBSD: meson_sdhc.c,v 1.1 2019/01/20 00:44:01 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: meson_sdhc.c,v 1.1 2019/01/20 00:44:01 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/gpio.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/amlogic/meson_sdhcreg.h> 47 48 enum { 49 SDHC_PORT_A = 0, 50 SDHC_PORT_B = 1, 51 SDHC_PORT_C = 2 52 }; 53 54 static int meson_sdhc_match(device_t, cfdata_t, void *); 55 static void meson_sdhc_attach(device_t, device_t, void *); 56 static void meson_sdhc_attach_i(device_t); 57 58 static int meson_sdhc_intr(void *); 59 60 struct meson_sdhc_softc { 61 device_t sc_dev; 62 bus_space_tag_t sc_bst; 63 bus_space_handle_t sc_bsh; 64 bus_dma_tag_t sc_dmat; 65 void *sc_ih; 66 67 device_t sc_sdmmc_dev; 68 kmutex_t sc_intr_lock; 69 kcondvar_t sc_intr_cv; 70 71 uint32_t sc_intr_ista; 72 73 bus_dmamap_t sc_dmamap; 74 bus_dma_segment_t sc_segs[1]; 75 void *sc_bbuf; 76 77 u_int sc_bus_freq; 78 79 struct fdtbus_gpio_pin *sc_gpio_cd; 80 int sc_gpio_cd_inverted; 81 struct fdtbus_gpio_pin *sc_gpio_wp; 82 int sc_gpio_wp_inverted; 83 84 struct fdtbus_regulator *sc_reg_vmmc; 85 struct fdtbus_regulator *sc_reg_vqmmc; 86 87 bool sc_non_removable; 88 bool sc_broken_cd; 89 90 int sc_port; 91 int sc_slot_phandle; 92 int sc_signal_voltage; 93 }; 94 95 CFATTACH_DECL_NEW(meson_sdhc, sizeof(struct meson_sdhc_softc), 96 meson_sdhc_match, meson_sdhc_attach, NULL, NULL); 97 98 static int meson_sdhc_host_reset(sdmmc_chipset_handle_t); 99 static uint32_t meson_sdhc_host_ocr(sdmmc_chipset_handle_t); 100 static int meson_sdhc_host_maxblklen(sdmmc_chipset_handle_t); 101 static int meson_sdhc_card_detect(sdmmc_chipset_handle_t); 102 static int meson_sdhc_write_protect(sdmmc_chipset_handle_t); 103 static int meson_sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 104 static int meson_sdhc_bus_clock(sdmmc_chipset_handle_t, int); 105 static int meson_sdhc_bus_width(sdmmc_chipset_handle_t, int); 106 static int meson_sdhc_bus_rod(sdmmc_chipset_handle_t, int); 107 static void meson_sdhc_exec_command(sdmmc_chipset_handle_t, 108 struct sdmmc_command *); 109 static void meson_sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 110 static void meson_sdhc_card_intr_ack(sdmmc_chipset_handle_t); 111 static int meson_sdhc_signal_voltage(sdmmc_chipset_handle_t, int); 112 static int meson_sdhc_execute_tuning(sdmmc_chipset_handle_t, int); 113 114 static int meson_sdhc_default_rx_phase(struct meson_sdhc_softc *); 115 static int meson_sdhc_set_clock(struct meson_sdhc_softc *, u_int); 116 static int meson_sdhc_wait_idle(struct meson_sdhc_softc *); 117 static int meson_sdhc_wait_ista(struct meson_sdhc_softc *, uint32_t, int); 118 119 static void meson_sdhc_dmainit(struct meson_sdhc_softc *); 120 121 static struct sdmmc_chip_functions meson_sdhc_chip_functions = { 122 .host_reset = meson_sdhc_host_reset, 123 .host_ocr = meson_sdhc_host_ocr, 124 .host_maxblklen = meson_sdhc_host_maxblklen, 125 .card_detect = meson_sdhc_card_detect, 126 .write_protect = meson_sdhc_write_protect, 127 .bus_power = meson_sdhc_bus_power, 128 .bus_clock = meson_sdhc_bus_clock, 129 .bus_width = meson_sdhc_bus_width, 130 .bus_rod = meson_sdhc_bus_rod, 131 .exec_command = meson_sdhc_exec_command, 132 .card_enable_intr = meson_sdhc_card_enable_intr, 133 .card_intr_ack = meson_sdhc_card_intr_ack, 134 .signal_voltage = meson_sdhc_signal_voltage, 135 .execute_tuning = meson_sdhc_execute_tuning, 136 }; 137 138 #define SDHC_WRITE(sc, reg, val) \ 139 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 140 #define SDHC_READ(sc, reg) \ 141 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 142 #define SDHC_SET_CLEAR meson_sdhc_set_clear 143 144 static inline void 145 meson_sdhc_set_clear(struct meson_sdhc_softc *sc, bus_addr_t reg, uint32_t set, uint32_t clr) 146 { 147 const uint32_t old = SDHC_READ(sc, reg); 148 const uint32_t new = set | (old & ~clr); 149 if (old != new) 150 SDHC_WRITE(sc, reg, new); 151 } 152 153 static const char * const compatible[] = { 154 "amlogic,meson8b-sdhc", 155 NULL 156 }; 157 158 static const char * const slot_compatible[] = { 159 "mmc-slot", 160 NULL 161 }; 162 163 static int 164 meson_sdhc_match(device_t parent, cfdata_t cf, void *aux) 165 { 166 struct fdt_attach_args * const faa = aux; 167 168 return of_match_compatible(faa->faa_phandle, compatible); 169 } 170 171 static void 172 meson_sdhc_attach(device_t parent, device_t self, void *aux) 173 { 174 struct meson_sdhc_softc * const sc = device_private(self); 175 struct fdt_attach_args * const faa = aux; 176 const int phandle = faa->faa_phandle; 177 char intrstr[128]; 178 struct clk *clk_clkin, *clk_core; 179 bus_addr_t addr, port; 180 bus_size_t size; 181 int child; 182 183 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 184 aprint_error(": couldn't get registers\n"); 185 return; 186 } 187 188 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 189 aprint_error(": failed to decode interrupt\n"); 190 return; 191 } 192 193 clk_core = fdtbus_clock_get(phandle, "core"); 194 if (clk_core == NULL || clk_enable(clk_core) != 0) { 195 aprint_error(": failed to enable core clock\n"); 196 return; 197 } 198 199 clk_clkin = fdtbus_clock_get(phandle, "clkin"); 200 if (clk_clkin == NULL || clk_enable(clk_clkin) != 0) { 201 aprint_error(": failed to get clkin clock\n"); 202 return; 203 } 204 205 sc->sc_dev = self; 206 sc->sc_bst = faa->faa_bst; 207 sc->sc_dmat = faa->faa_dmat; 208 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 209 aprint_error(": failed to map registers\n"); 210 return; 211 } 212 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 213 cv_init(&sc->sc_intr_cv, "sdhcintr"); 214 sc->sc_signal_voltage = SDMMC_SIGNAL_VOLTAGE_330; 215 216 sc->sc_port = -1; 217 for (child = OF_child(phandle); child; child = OF_peer(child)) 218 if (of_match_compatible(child, slot_compatible) > 0) { 219 if (fdtbus_get_reg(child, 0, &port, NULL) == 0) { 220 sc->sc_slot_phandle = child; 221 sc->sc_port = port; 222 } 223 break; 224 } 225 if (sc->sc_port == -1) { 226 aprint_error(": couldn't get mmc slot\n"); 227 return; 228 } 229 230 aprint_naive("\n"); 231 aprint_normal(": SDHC controller (port %c)\n", sc->sc_port + 'A'); 232 233 sc->sc_reg_vmmc = fdtbus_regulator_acquire(sc->sc_slot_phandle, "vmmc-supply"); 234 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(sc->sc_slot_phandle, "vqmmc-supply"); 235 236 sc->sc_gpio_cd = fdtbus_gpio_acquire(sc->sc_slot_phandle, "cd-gpios", 237 GPIO_PIN_INPUT); 238 sc->sc_gpio_wp = fdtbus_gpio_acquire(sc->sc_slot_phandle, "wp-gpios", 239 GPIO_PIN_INPUT); 240 241 sc->sc_gpio_cd_inverted = of_hasprop(sc->sc_slot_phandle, "cd-inverted"); 242 sc->sc_gpio_wp_inverted = of_hasprop(sc->sc_slot_phandle, "wp-inverted"); 243 244 sc->sc_non_removable = of_hasprop(sc->sc_slot_phandle, "non-removable"); 245 sc->sc_broken_cd = of_hasprop(sc->sc_slot_phandle, "broken-cd"); 246 247 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, 248 meson_sdhc_intr, sc); 249 if (sc->sc_ih == NULL) { 250 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 251 intrstr); 252 return; 253 } 254 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 255 256 sc->sc_bus_freq = clk_get_rate(clk_clkin); 257 258 aprint_normal_dev(self, "core %u Hz, clkin %u Hz\n", clk_get_rate(clk_core), clk_get_rate(clk_clkin)); 259 260 meson_sdhc_dmainit(sc); 261 262 config_interrupts(self, meson_sdhc_attach_i); 263 } 264 265 static void 266 meson_sdhc_attach_i(device_t self) 267 { 268 struct meson_sdhc_softc *sc = device_private(self); 269 struct sdmmcbus_attach_args saa; 270 u_int pll_freq; 271 272 pll_freq = sc->sc_bus_freq / 1000; 273 274 meson_sdhc_host_reset(sc); 275 meson_sdhc_bus_width(sc, 1); 276 277 memset(&saa, 0, sizeof(saa)); 278 saa.saa_busname = "sdmmc"; 279 saa.saa_sct = &meson_sdhc_chip_functions; 280 saa.saa_dmat = sc->sc_dmat; 281 saa.saa_sch = sc; 282 saa.saa_clkmin = 400; 283 saa.saa_clkmax = pll_freq; 284 /* Do not advertise DMA capabilities, we handle DMA ourselves */ 285 saa.saa_caps = SMC_CAPS_4BIT_MODE| 286 SMC_CAPS_SD_HIGHSPEED| 287 SMC_CAPS_MMC_HIGHSPEED| 288 SMC_CAPS_UHS_SDR50| 289 SMC_CAPS_UHS_SDR104| 290 SMC_CAPS_AUTO_STOP; 291 292 if (sc->sc_port == SDHC_PORT_C) { 293 saa.saa_caps |= SMC_CAPS_MMC_HS200; 294 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 295 } 296 297 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 298 } 299 300 static int 301 meson_sdhc_intr(void *priv) 302 { 303 struct meson_sdhc_softc *sc = priv; 304 uint32_t ista; 305 306 mutex_enter(&sc->sc_intr_lock); 307 ista = SDHC_READ(sc, SD_ISTA_REG); 308 309 if (!ista) { 310 mutex_exit(&sc->sc_intr_lock); 311 return 0; 312 } 313 314 SDHC_WRITE(sc, SD_ISTA_REG, ista); 315 316 sc->sc_intr_ista |= ista; 317 cv_broadcast(&sc->sc_intr_cv); 318 319 mutex_exit(&sc->sc_intr_lock); 320 321 return 1; 322 } 323 324 static void 325 meson_sdhc_dmainit(struct meson_sdhc_softc *sc) 326 { 327 int error, rseg; 328 329 error = bus_dmamem_alloc(sc->sc_dmat, MAXPHYS, PAGE_SIZE, MAXPHYS, 330 sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 331 if (error) { 332 device_printf(sc->sc_dev, "bus_dmamem_alloc failed: %d\n", error); 333 return; 334 } 335 KASSERT(rseg == 1); 336 337 error = bus_dmamem_map(sc->sc_dmat, sc->sc_segs, rseg, MAXPHYS, 338 &sc->sc_bbuf, BUS_DMA_WAITOK); 339 if (error) { 340 device_printf(sc->sc_dev, "bus_dmamem_map failed\n"); 341 return; 342 } 343 344 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 345 BUS_DMA_WAITOK, &sc->sc_dmamap); 346 if (error) { 347 device_printf(sc->sc_dev, "bus_dmamap_create failed\n"); 348 return; 349 } 350 351 } 352 353 static int 354 meson_sdhc_default_rx_phase(struct meson_sdhc_softc *sc) 355 { 356 const u_int pll_freq = sc->sc_bus_freq / 1000; 357 const u_int clkc = SDHC_READ(sc, SD_CLKC_REG); 358 const u_int clk_div = __SHIFTOUT(clkc, SD_CLKC_CLK_DIV); 359 const u_int act_freq = pll_freq / clk_div; 360 361 if (act_freq > 90000) { 362 return 1; 363 } else if (act_freq > 45000) { 364 if (sc->sc_signal_voltage == SDMMC_SIGNAL_VOLTAGE_330) { 365 return 15; 366 } else { 367 return 11; 368 } 369 } else if (act_freq >= 25000) { 370 return 15; 371 } else if (act_freq > 5000) { 372 return 23; 373 } else if (act_freq > 1000) { 374 return 55; 375 } else { 376 return 1061; 377 } 378 } 379 380 static int 381 meson_sdhc_set_clock(struct meson_sdhc_softc *sc, u_int freq) 382 { 383 uint32_t clkc; 384 uint32_t clk2; 385 u_int pll_freq, clk_div; 386 387 clkc = SDHC_READ(sc, SD_CLKC_REG); 388 clkc &= ~SD_CLKC_TX_CLK_ENABLE; 389 clkc &= ~SD_CLKC_RX_CLK_ENABLE; 390 clkc &= ~SD_CLKC_SD_CLK_ENABLE; 391 SDHC_WRITE(sc, SD_CLKC_REG, clkc); 392 clkc &= ~SD_CLKC_MOD_CLK_ENABLE; 393 SDHC_WRITE(sc, SD_CLKC_REG, clkc); 394 395 if (freq == 0) 396 return 0; 397 398 clkc &= ~SD_CLKC_CLK_DIV; 399 clkc &= ~SD_CLKC_CLK_IN_SEL; 400 401 clkc |= __SHIFTIN(SD_CLKC_CLK_IN_SEL_FCLK_DIV3, 402 SD_CLKC_CLK_IN_SEL); 403 404 pll_freq = sc->sc_bus_freq / 1000; /* 2.55GHz */ 405 clk_div = howmany(pll_freq, freq); 406 407 clkc |= __SHIFTIN(clk_div - 1, SD_CLKC_CLK_DIV); 408 409 SDHC_WRITE(sc, SD_CLKC_REG, clkc); 410 411 clkc |= SD_CLKC_MOD_CLK_ENABLE; 412 SDHC_WRITE(sc, SD_CLKC_REG, clkc); 413 414 clkc |= SD_CLKC_TX_CLK_ENABLE; 415 clkc |= SD_CLKC_RX_CLK_ENABLE; 416 clkc |= SD_CLKC_SD_CLK_ENABLE; 417 SDHC_WRITE(sc, SD_CLKC_REG, clkc); 418 419 clk2 = SDHC_READ(sc, SD_CLK2_REG); 420 clk2 &= ~SD_CLK2_SD_CLK_PHASE; 421 clk2 |= __SHIFTIN(1, SD_CLK2_SD_CLK_PHASE); 422 clk2 &= ~SD_CLK2_RX_CLK_PHASE; 423 clk2 |= __SHIFTIN(meson_sdhc_default_rx_phase(sc), 424 SD_CLK2_RX_CLK_PHASE); 425 SDHC_WRITE(sc, SD_CLK2_REG, clk2); 426 427 return 0; 428 } 429 430 static int 431 meson_sdhc_wait_idle(struct meson_sdhc_softc *sc) 432 { 433 int i; 434 435 for (i = 0; i < 1000000; i++) { 436 const uint32_t stat = SDHC_READ(sc, SD_STAT_REG); 437 const uint32_t esta = SDHC_READ(sc, SD_ESTA_REG); 438 if ((stat & SD_STAT_BUSY) == 0 && 439 (esta & SD_ESTA_BUSY) == 0) 440 return 0; 441 delay(1); 442 } 443 444 return EBUSY; 445 } 446 447 static int 448 meson_sdhc_wait_ista(struct meson_sdhc_softc *sc, uint32_t mask, int timeout) 449 { 450 int retry, error; 451 452 KASSERT(mutex_owned(&sc->sc_intr_lock)); 453 454 if (sc->sc_intr_ista & mask) 455 return 0; 456 457 retry = timeout / hz; 458 459 while (retry > 0) { 460 error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_lock, hz); 461 if (error && error != EWOULDBLOCK) 462 return error; 463 if (sc->sc_intr_ista & mask) 464 return 0; 465 --retry; 466 } 467 468 return ETIMEDOUT; 469 } 470 471 static int 472 meson_sdhc_host_reset(sdmmc_chipset_handle_t sch) 473 { 474 struct meson_sdhc_softc *sc = sch; 475 uint32_t enhc; 476 477 SDHC_WRITE(sc, SD_SRST_REG, 478 SD_SRST_MAIN_CTRL | SD_SRST_TX_FIFO | SD_SRST_RX_FIFO | 479 SD_SRST_DPHY_TX | SD_SRST_DPHY_RX | SD_SRST_DMA_IF); 480 481 delay(50); 482 483 SDHC_WRITE(sc, SD_SRST_REG, 0); 484 485 delay(10); 486 487 SDHC_WRITE(sc, SD_CNTL_REG, 488 __SHIFTIN(0x7, SD_CNTL_TX_ENDIAN_CTRL) | 489 __SHIFTIN(0x7, SD_CNTL_RX_ENDIAN_CTRL) | 490 __SHIFTIN(0xf, SD_CNTL_RX_PERIOD) | 491 __SHIFTIN(0x7f, SD_CNTL_RX_TIMEOUT)); 492 493 SDHC_WRITE(sc, SD_CLKC_REG, 494 SDHC_READ(sc, SD_CLKC_REG) & ~SD_CLKC_MEM_PWR); 495 496 SDHC_WRITE(sc, SD_PDMA_REG, 497 __SHIFTIN(7, SD_PDMA_TX_BURST_LEN) | 498 __SHIFTIN(49, SD_PDMA_TXFIFO_THRESHOLD) | 499 __SHIFTIN(15, SD_PDMA_RX_BURST_LEN) | 500 __SHIFTIN(7, SD_PDMA_RXFIFO_THRESHOLD) | 501 SD_PDMA_DMA_URGENT); 502 503 SDHC_WRITE(sc, SD_MISC_REG, 504 __SHIFTIN(7, SD_MISC_TXSTART_THRESHOLD) | 505 __SHIFTIN(5, SD_MISC_WCRC_ERR_PATTERN) | 506 __SHIFTIN(2, SD_MISC_WCRC_OK_PATTERN)); 507 508 enhc = SDHC_READ(sc, SD_ENHC_REG); 509 enhc &= ~SD_ENHC_RXFIFO_THRESHOLD; 510 enhc |= __SHIFTIN(63, SD_ENHC_RXFIFO_THRESHOLD); 511 enhc &= ~SD_ENHC_DMA_RX_RESP; 512 enhc |= SD_ENHC_DMA_TX_RESP; 513 enhc &= ~SD_ENHC_SDIO_IRQ_PERIOD; 514 enhc |= __SHIFTIN(12, SD_ENHC_SDIO_IRQ_PERIOD); 515 enhc &= ~SD_ENHC_RX_TIMEOUT; 516 enhc |= __SHIFTIN(0xff, SD_ENHC_RX_TIMEOUT); 517 SDHC_WRITE(sc, SD_ENHC_REG, enhc); 518 519 SDHC_WRITE(sc, SD_ICTL_REG, 0); 520 SDHC_WRITE(sc, SD_ISTA_REG, SD_INT_CLEAR); 521 522 return 0; 523 } 524 525 static uint32_t 526 meson_sdhc_host_ocr(sdmmc_chipset_handle_t sch) 527 { 528 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | 529 MMC_OCR_HCS | MMC_OCR_S18A; 530 } 531 532 static int 533 meson_sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 534 { 535 return 512; 536 } 537 538 static int 539 meson_sdhc_card_detect(sdmmc_chipset_handle_t sch) 540 { 541 struct meson_sdhc_softc *sc = sch; 542 int val; 543 544 if (sc->sc_non_removable || sc->sc_broken_cd) { 545 return 1; 546 } else if (sc->sc_gpio_cd != NULL) { 547 val = fdtbus_gpio_read(sc->sc_gpio_cd); 548 if (sc->sc_gpio_cd_inverted) 549 val = !val; 550 return val; 551 } else { 552 return 1; 553 } 554 } 555 556 static int 557 meson_sdhc_write_protect(sdmmc_chipset_handle_t sch) 558 { 559 struct meson_sdhc_softc *sc = sch; 560 int val; 561 562 if (sc->sc_gpio_wp != NULL) { 563 val = fdtbus_gpio_read(sc->sc_gpio_wp); 564 if (sc->sc_gpio_wp_inverted) 565 val = !val; 566 return val; 567 } 568 569 return 0; 570 } 571 572 static int 573 meson_sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 574 { 575 return 0; 576 } 577 578 static int 579 meson_sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 580 { 581 struct meson_sdhc_softc *sc = sch; 582 583 return meson_sdhc_set_clock(sc, freq); 584 } 585 586 static int 587 meson_sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 588 { 589 struct meson_sdhc_softc *sc = sch; 590 uint32_t cntl; 591 592 cntl = SDHC_READ(sc, SD_CNTL_REG); 593 cntl &= ~SD_CNTL_DAT_TYPE; 594 switch (width) { 595 case 1: 596 cntl |= __SHIFTIN(0, SD_CNTL_DAT_TYPE); 597 break; 598 case 4: 599 cntl |= __SHIFTIN(1, SD_CNTL_DAT_TYPE); 600 break; 601 case 8: 602 cntl |= __SHIFTIN(2, SD_CNTL_DAT_TYPE); 603 break; 604 default: 605 return EINVAL; 606 } 607 608 SDHC_WRITE(sc, SD_CNTL_REG, cntl); 609 610 return 0; 611 } 612 613 static int 614 meson_sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 615 { 616 return ENOTSUP; 617 } 618 619 static void 620 meson_sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 621 { 622 struct meson_sdhc_softc *sc = sch; 623 uint32_t cmdval = 0, cntl, srst, pdma, ictl; 624 bool use_bbuf = false; 625 int i; 626 627 KASSERT(cmd->c_blklen <= 512); 628 629 mutex_enter(&sc->sc_intr_lock); 630 631 /* Filter SDIO commands */ 632 switch (cmd->c_opcode) { 633 case SD_IO_SEND_OP_COND: 634 case SD_IO_RW_DIRECT: 635 case SD_IO_RW_EXTENDED: 636 cmd->c_error = EINVAL; 637 goto done; 638 } 639 640 if (cmd->c_opcode == MMC_STOP_TRANSMISSION) 641 cmdval |= SD_SEND_DATA_STOP; 642 if (cmd->c_flags & SCF_RSP_PRESENT) 643 cmdval |= SD_SEND_COMMAND_HAS_RESP; 644 if (cmd->c_flags & SCF_RSP_136) { 645 cmdval |= SD_SEND_RESPONSE_LENGTH; 646 cmdval |= SD_SEND_RESPONSE_NO_CRC; 647 } 648 if ((cmd->c_flags & SCF_RSP_CRC) == 0) 649 cmdval |= SD_SEND_RESPONSE_NO_CRC; 650 651 SDHC_WRITE(sc, SD_ICTL_REG, 0); 652 SDHC_WRITE(sc, SD_ISTA_REG, SD_INT_CLEAR); 653 sc->sc_intr_ista = 0; 654 655 ictl = SD_INT_ERROR; 656 657 cntl = SDHC_READ(sc, SD_CNTL_REG); 658 cntl &= ~SD_CNTL_PACK_LEN; 659 if (cmd->c_datalen > 0) { 660 unsigned int nblks; 661 662 cmdval |= SD_SEND_COMMAND_HAS_DATA; 663 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 664 cmdval |= SD_SEND_DATA_DIRECTION; 665 } 666 667 nblks = cmd->c_datalen / cmd->c_blklen; 668 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 669 ++nblks; 670 671 cntl |= __SHIFTIN(cmd->c_blklen & 0x1ff, SD_CNTL_PACK_LEN); 672 673 cmdval |= __SHIFTIN(nblks - 1, SD_SEND_TOTAL_PACK); 674 675 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 676 ictl |= SD_INT_DATA_COMPLETE; 677 } else { 678 ictl |= SD_INT_DMA_DONE; 679 } 680 } else { 681 ictl |= SD_INT_RESP_COMPLETE; 682 } 683 684 SDHC_WRITE(sc, SD_ICTL_REG, ictl); 685 686 SDHC_WRITE(sc, SD_CNTL_REG, cntl); 687 688 pdma = SDHC_READ(sc, SD_PDMA_REG); 689 if (cmd->c_datalen > 0) { 690 pdma |= SD_PDMA_DMA_MODE; 691 } else { 692 pdma &= ~SD_PDMA_DMA_MODE; 693 } 694 SDHC_WRITE(sc, SD_PDMA_REG, pdma); 695 696 SDHC_WRITE(sc, SD_ARGU_REG, cmd->c_arg); 697 698 cmd->c_error = meson_sdhc_wait_idle(sc); 699 if (cmd->c_error) { 700 goto done; 701 } 702 703 if (cmd->c_datalen > 0) { 704 cmd->c_error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 705 sc->sc_bbuf, MAXPHYS, NULL, BUS_DMA_WAITOK); 706 if (cmd->c_error) { 707 device_printf(sc->sc_dev, "bus_dmamap_load failed\n"); 708 goto done; 709 } 710 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 711 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, 712 MAXPHYS, BUS_DMASYNC_PREREAD); 713 } else { 714 memcpy(sc->sc_bbuf, cmd->c_data, cmd->c_datalen); 715 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, 716 MAXPHYS, BUS_DMASYNC_PREWRITE); 717 } 718 SDHC_WRITE(sc, SD_ADDR_REG, sc->sc_dmamap->dm_segs[0].ds_addr); 719 use_bbuf = true; 720 } 721 722 cmd->c_resid = cmd->c_datalen; 723 SDHC_WRITE(sc, SD_SEND_REG, cmdval | cmd->c_opcode); 724 725 if (cmd->c_datalen > 0) { 726 uint32_t wbit = ISSET(cmd->c_flags, SCF_CMD_READ) ? 727 SD_INT_DATA_COMPLETE : SD_INT_DMA_DONE; 728 cmd->c_error = meson_sdhc_wait_ista(sc, 729 SD_INT_ERROR | wbit, hz * 10); 730 if (cmd->c_error == 0 && 731 (sc->sc_intr_ista & SD_INT_ERROR)) { 732 cmd->c_error = ETIMEDOUT; 733 } 734 if (cmd->c_error) { 735 goto done; 736 } 737 } else { 738 cmd->c_error = meson_sdhc_wait_ista(sc, 739 SD_INT_ERROR | SD_INT_RESP_COMPLETE, hz * 10); 740 if (cmd->c_error == 0 && (sc->sc_intr_ista & SD_INT_ERROR)) { 741 if (sc->sc_intr_ista & SD_INT_TIMEOUT) { 742 cmd->c_error = ETIMEDOUT; 743 } else { 744 cmd->c_error = EIO; 745 } 746 } 747 if (cmd->c_error) { 748 goto done; 749 } 750 } 751 752 SDHC_WRITE(sc, SD_ISTA_REG, sc->sc_intr_ista); 753 754 if (cmd->c_flags & SCF_RSP_PRESENT) { 755 pdma = SDHC_READ(sc, SD_PDMA_REG); 756 pdma &= ~SD_PDMA_DMA_MODE; 757 if (cmd->c_flags & SCF_RSP_136) { 758 for (i = 4; i >= 1; i--) { 759 pdma &= ~SD_PDMA_PIO_RDRESP; 760 pdma |= __SHIFTIN(i, SD_PDMA_PIO_RDRESP); 761 SDHC_WRITE(sc, SD_PDMA_REG, pdma); 762 cmd->c_resp[i - 1] = SDHC_READ(sc, SD_ARGU_REG); 763 764 } 765 if (cmd->c_flags & SCF_RSP_CRC) { 766 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 767 (cmd->c_resp[1] << 24); 768 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 769 (cmd->c_resp[2] << 24); 770 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 771 (cmd->c_resp[3] << 24); 772 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 773 } 774 } else { 775 pdma &= ~SD_PDMA_PIO_RDRESP; 776 pdma |= __SHIFTIN(0, SD_PDMA_PIO_RDRESP); 777 SDHC_WRITE(sc, SD_PDMA_REG, pdma); 778 cmd->c_resp[0] = SDHC_READ(sc, SD_ARGU_REG); 779 } 780 } 781 782 done: 783 if (use_bbuf) { 784 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 785 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, 786 MAXPHYS, BUS_DMASYNC_POSTREAD); 787 } else { 788 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, 789 MAXPHYS, BUS_DMASYNC_POSTWRITE); 790 } 791 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 792 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 793 memcpy(cmd->c_data, sc->sc_bbuf, cmd->c_datalen); 794 } 795 } 796 797 cmd->c_flags |= SCF_ITSDONE; 798 799 SDHC_WRITE(sc, SD_ISTA_REG, SD_INT_CLEAR); 800 SDHC_WRITE(sc, SD_ICTL_REG, 0); 801 802 srst = SDHC_READ(sc, SD_SRST_REG); 803 srst |= (SD_SRST_TX_FIFO | SD_SRST_RX_FIFO); 804 SDHC_WRITE(sc, SD_SRST_REG, srst); 805 806 mutex_exit(&sc->sc_intr_lock); 807 } 808 809 static void 810 meson_sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 811 { 812 } 813 814 static void 815 meson_sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 816 { 817 } 818 819 static int 820 meson_sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 821 { 822 struct meson_sdhc_softc *sc = sch; 823 u_int uvol; 824 int error; 825 826 if (sc->sc_reg_vqmmc == NULL) 827 return 0; 828 829 switch (signal_voltage) { 830 case SDMMC_SIGNAL_VOLTAGE_330: 831 uvol = 3300000; 832 break; 833 case SDMMC_SIGNAL_VOLTAGE_180: 834 uvol = 1800000; 835 break; 836 default: 837 return EINVAL; 838 } 839 840 error = fdtbus_regulator_supports_voltage(sc->sc_reg_vqmmc, uvol, uvol); 841 if (error != 0) 842 return 0; 843 844 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 845 if (error != 0) 846 return error; 847 848 error = fdtbus_regulator_enable(sc->sc_reg_vqmmc); 849 if (error != 0) 850 return error; 851 852 sc->sc_signal_voltage = signal_voltage; 853 return 0; 854 } 855 856 static int 857 meson_sdhc_execute_tuning(sdmmc_chipset_handle_t sch, int timing) 858 { 859 static const uint8_t tuning_blk_8bit[] = { 860 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 861 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, 862 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, 863 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, 864 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, 865 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, 866 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, 867 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, 868 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 869 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 870 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 871 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 872 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 873 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 874 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 875 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 876 }; 877 static const uint8_t tuning_blk_4bit[] = { 878 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc, 879 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef, 880 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb, 881 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef, 882 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c, 883 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee, 884 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff, 885 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde, 886 }; 887 888 struct meson_sdhc_softc *sc = sch; 889 struct sdmmc_command cmd; 890 uint8_t data[sizeof(tuning_blk_8bit)]; 891 const uint8_t *tblk; 892 size_t tsize; 893 struct window_s { 894 int start; 895 u_int size; 896 } best = { .start = -1, .size = 0 }, 897 curr = { .start = -1, .size = 0 }, 898 wrap = { .start = 0, .size = 0 }; 899 u_int ph, rx_phase, clk_div; 900 int opcode; 901 902 switch (timing) { 903 case SDMMC_TIMING_MMC_HS200: 904 tblk = tuning_blk_8bit; 905 tsize = sizeof(tuning_blk_8bit); 906 opcode = MMC_SEND_TUNING_BLOCK_HS200; 907 break; 908 case SDMMC_TIMING_UHS_SDR50: 909 case SDMMC_TIMING_UHS_SDR104: 910 tblk = tuning_blk_4bit; 911 tsize = sizeof(tuning_blk_4bit); 912 opcode = MMC_SEND_TUNING_BLOCK; 913 break; 914 default: 915 return EINVAL; 916 } 917 918 const uint32_t clkc = SDHC_READ(sc, SD_CLKC_REG); 919 clk_div = __SHIFTOUT(clkc, SD_CLKC_CLK_DIV); 920 921 for (ph = 0; ph <= clk_div; ph++) { 922 SDHC_SET_CLEAR(sc, SD_CLK2_REG, 923 __SHIFTIN(ph, SD_CLK2_RX_CLK_PHASE), SD_CLK2_RX_CLK_PHASE); 924 delay(10); 925 926 u_int nmatch = 0; 927 #define NUMTRIES 10 928 for (u_int i = 0; i < NUMTRIES; i++) { 929 memset(data, 0, tsize); 930 memset(&cmd, 0, sizeof(cmd)); 931 cmd.c_data = data; 932 cmd.c_datalen = cmd.c_blklen = tsize; 933 cmd.c_opcode = opcode; 934 cmd.c_arg = 0; 935 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 936 meson_sdhc_exec_command(sc, &cmd); 937 if (cmd.c_error == 0 && memcmp(data, tblk, tsize) == 0) 938 nmatch++; 939 } 940 if (nmatch == NUMTRIES) { /* good phase value */ 941 if (wrap.start == 0) 942 wrap.size++; 943 if (curr.start == -1) 944 curr.start = ph; 945 curr.size++; 946 } else { 947 wrap.start = -1; 948 if (curr.start != -1) { /* end of current window */ 949 if (best.start == -1 || best.size < curr.size) 950 best = curr; 951 curr = (struct window_s) 952 { .start = -1, .size = 0 }; 953 } 954 } 955 #undef NUMTRIES 956 } 957 958 if (curr.start != -1) { /* the current window wraps around */ 959 curr.size += wrap.size; 960 if (curr.size > ph) 961 curr.size = ph; 962 if (best.start == -1 || best.size < curr.size) 963 best = curr; 964 } 965 966 if (best.start == -1) { /* no window - use default rx_phase */ 967 rx_phase = meson_sdhc_default_rx_phase(sc); 968 } else { 969 rx_phase = best.start + best.size / 2; 970 if (rx_phase >= ph) 971 rx_phase -= ph; 972 } 973 974 SDHC_SET_CLEAR(sc, SD_CLK2_REG, 975 __SHIFTIN(rx_phase, SD_CLK2_RX_CLK_PHASE), SD_CLK2_RX_CLK_PHASE); 976 977 return 0; 978 } 979
Indexes created Sun Sep 28 16:09:52 GMT 2025