meson_usbctrl.c revision 1.2
1 /* $NetBSD: meson_usbctrl.c,v 1.2 2021/01/18 02:35:48 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2021 Ryo Shimizu <ryo (at) nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: meson_usbctrl.c,v 1.2 2021/01/18 02:35:48 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/types.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 37 #include <dev/fdt/fdtvar.h> 38 39 /* 40 * USB Glue registers: 0xffe09000 41 */ 42 43 /* usb2 phy ports control registers */ 44 #define MESONUSBCTRL_MAXPHYS 3 45 #define U2P_R0_REG(i) (0x20 * (i) + 0x00) 46 #define U2P_R0_DRV_VBUS __BIT(5) 47 #define U2P_R0_ID_PULLUP __BIT(4) 48 #define U2P_R0_POWER_ON_RESET __BIT(3) 49 #define U2P_R0_HAST_MODE __BIT(2) 50 #define U2P_R0_POWER_OK __BIT(1) 51 #define U2P_R0_HOST_DEVICE __BIT(0) 52 #define U2P_R1_REG(i) (0x20 * (i) + 0x04) 53 #define U2P_R1_VBUS_VALID __BIT(3) 54 #define U2P_R1_OTG_SESSION_VALID __BIT(2) 55 #define U2P_R1_ID_DIG __BIT(1) 56 #define U2P_R1_PHY_READY __BIT(0) 57 58 /* glue registers */ 59 #define USB_R0_REG 0x80 60 #define USB_R0_U2D_ACT __BIT(31) 61 #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK __BITS(30,29) 62 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK __BITS(28,19) 63 #define USB_R0_P30_LANE0_EXT_PCLK_REQ __BIT(18) 64 #define USB_R0_P30_LANE0_TX2RX_LOOPBACK __BIT(17) 65 #define USB_R1_REG 0x84 66 #define USB_R1_P30_PCS_TX_SWING_FULL_MASK __BITS(31,25) 67 #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK __BITS(24,19) 68 #define USB_R1_U3H_HOST_MSI_ENABLE __BIT(18) 69 #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT __BIT(17) 70 #define USB_R1_U3H_HOST_U3_PORT_DISABLE __BIT(16) 71 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK __BITS(13,12) 72 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK __BITS(9,7) 73 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK __BITS(4,2) 74 #define USB_R1_U3H_PME_ENABLE __BIT(1) 75 #define USB_R1_U3H_BIGENDIAN_GS __BIT(0) 76 #define USB_R2_REG 0x88 77 #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK __BITS(31,26) 78 #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK __BITS(25,20) 79 #define USB_R3_REG 0x8c 80 #define USB_R3_P30_REF_SSP_EN __BIT(13) 81 #define USB_R3_P30_SSC_REF_CLK_SEL_MASK __BITS(12,4) 82 #define USB_R3_P30_SSC_RANGE_MASK __BITS(3,1) 83 #define USB_R3_P30_SSC_ENABLE __BIT(0) 84 #define USB_R4_REG 0x90 85 #define USB_R4_P21_ONLY __BIT(4) 86 #define USB_R4_MEM_PD_MASK __BITS(3,2) 87 #define USB_R4_P21_SLEEP_M0 __BIT(1) 88 #define USB_R4_P21_PORT_RESET_0 __BIT(0) 89 #define USB_R5_REG 0x94 90 #define USB_R5_ID_DIG_CNT_MASK __BITS(23,16) 91 #define USB_R5_ID_DIG_TH_MASK __BITS(15,8) 92 #define USB_R5_ID_DIG_IRQ __BIT(7) 93 #define USB_R5_ID_DIG_CURR __BIT(6) 94 #define USB_R5_ID_DIG_EN_1 __BIT(5) 95 #define USB_R5_ID_DIG_EN_0 __BIT(4) 96 #define USB_R5_ID_DIG_CFG_MASK __BITS(3,2) 97 #define USB_R5_ID_DIG_REG __BIT(1) 98 #define USB_R5_ID_DIG_SYNC __BIT(0) 99 100 #define USBCTRL_READ_REG(sc, reg) \ 101 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 102 #define USBCTRL_WRITE_REG(sc, reg, val) \ 103 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 104 105 struct meson_usbctrl_config { 106 int num_phys; 107 }; 108 109 struct meson_usbctrl_config mesong12_conf = { 110 .num_phys = 3 111 }; 112 113 static const struct device_compatible_entry compat_data[] = { 114 { .compat = "amlogic,meson-g12a-usb-ctrl", .data = &mesong12_conf }, 115 116 { 0 } 117 }; 118 119 struct meson_usbctrl_softc { 120 device_t sc_dev; 121 bus_space_tag_t sc_bst; 122 bus_space_handle_t sc_bsh; 123 const struct meson_usbctrl_config *sc_conf; 124 struct fdtbus_regulator *sc_supply; 125 int sc_phandle; 126 }; 127 128 static void 129 meson_usbctrl_usb2_init(struct meson_usbctrl_softc *sc) 130 { 131 int i; 132 const char *p; 133 134 for (i = 0; i < sc->sc_conf->num_phys; i++) { 135 /* setup only for usb2 phys */ 136 p = fdtbus_get_string_index(sc->sc_phandle, "phy-names", i); 137 if (p == NULL || strstr(p, "usb2") == NULL) 138 continue; 139 140 USBCTRL_WRITE_REG(sc, U2P_R0_REG(i), 141 USBCTRL_READ_REG(sc, U2P_R0_REG(i)) | 142 U2P_R0_POWER_ON_RESET); 143 144 /* XXX: OTG not supported. always set HOST_DEVICE mode */ 145 USBCTRL_WRITE_REG(sc, U2P_R0_REG(i), 146 USBCTRL_READ_REG(sc, U2P_R0_REG(i)) | 147 U2P_R0_HOST_DEVICE); 148 149 USBCTRL_WRITE_REG(sc, U2P_R0_REG(i), 150 USBCTRL_READ_REG(sc, U2P_R0_REG(i)) & 151 ~U2P_R0_POWER_ON_RESET); 152 } 153 } 154 155 static void 156 meson_usbctrl_usb_glue_init(struct meson_usbctrl_softc *sc) 157 { 158 uint32_t val; 159 160 val = USBCTRL_READ_REG(sc, USB_R1_REG); 161 val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK; 162 val |= __SHIFTIN(0x20, USB_R1_U3H_FLADJ_30MHZ_REG_MASK); 163 USBCTRL_WRITE_REG(sc, USB_R1_REG, val); 164 165 val = USBCTRL_READ_REG(sc, USB_R5_REG); 166 val |= USB_R5_ID_DIG_EN_0; 167 USBCTRL_WRITE_REG(sc, USB_R5_REG, val); 168 169 val = USBCTRL_READ_REG(sc, USB_R5_REG); 170 val |= USB_R5_ID_DIG_EN_1; 171 USBCTRL_WRITE_REG(sc, USB_R5_REG, val); 172 173 val = USBCTRL_READ_REG(sc, USB_R5_REG); 174 val &= ~USB_R5_ID_DIG_TH_MASK; 175 val |= __SHIFTIN(0xff, USB_R5_ID_DIG_TH_MASK); 176 USBCTRL_WRITE_REG(sc, USB_R5_REG, val); 177 } 178 179 static void 180 meson_usbctrl_usb3_init(struct meson_usbctrl_softc *sc) 181 { 182 uint32_t val; 183 184 val = USBCTRL_READ_REG(sc, USB_R3_REG); 185 val &= ~USB_R3_P30_SSC_RANGE_MASK; 186 val &= ~USB_R3_P30_SSC_ENABLE; 187 val |= __SHIFTIN(2, USB_R3_P30_SSC_RANGE_MASK); 188 val |= USB_R3_P30_REF_SSP_EN; 189 USBCTRL_WRITE_REG(sc, USB_R3_REG, val); 190 191 delay(2); 192 193 val = USBCTRL_READ_REG(sc, USB_R2_REG); 194 val &= ~USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK; 195 val |= __SHIFTIN(0x15, USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK); 196 USBCTRL_WRITE_REG(sc, USB_R2_REG, val); 197 198 val = USBCTRL_READ_REG(sc, USB_R2_REG); 199 val &= ~USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK; 200 val |= __SHIFTIN(0x20, USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK); 201 USBCTRL_WRITE_REG(sc, USB_R2_REG, val); 202 203 delay(2); 204 205 val = USBCTRL_READ_REG(sc, USB_R1_REG); 206 val |= USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT; 207 USBCTRL_WRITE_REG(sc, USB_R1_REG, val); 208 209 val = USBCTRL_READ_REG(sc, USB_R1_REG); 210 val &= ~USB_R1_P30_PCS_TX_SWING_FULL_MASK; 211 val |= __SHIFTIN(127, USB_R1_P30_PCS_TX_SWING_FULL_MASK); 212 USBCTRL_WRITE_REG(sc, USB_R1_REG, val); 213 214 /* XXX: force HOST_DEVICE mode */ 215 val = USBCTRL_READ_REG(sc, USB_R0_REG); 216 val &= ~USB_R0_U2D_ACT; 217 USBCTRL_WRITE_REG(sc, USB_R0_REG, val); 218 219 val = USBCTRL_READ_REG(sc, USB_R4_REG); 220 val &= ~USB_R4_P21_SLEEP_M0; 221 USBCTRL_WRITE_REG(sc, USB_R4_REG, val); 222 } 223 224 static void 225 meson_usbctrl_enable_usb3_phys(struct meson_usbctrl_softc *sc) 226 { 227 struct fdtbus_phy *phy; 228 int i; 229 const char *phyname; 230 231 /* 232 * enable only for usb3 phys. 233 * node of "snps,dwc3" decl in "amlogic,meson-g12a-usb-ctrl" have 234 * no "phys" property, so enable the phy here. 235 */ 236 for (i = 0; i < sc->sc_conf->num_phys; i++) { 237 phyname = fdtbus_get_string_index(sc->sc_phandle, 238 "phy-names", i); 239 if (strstr(phyname, "usb3") == NULL) 240 continue; 241 242 phy = fdtbus_phy_get_index(sc->sc_phandle, i); 243 if (phy == NULL) 244 continue; 245 if (fdtbus_phy_enable(phy, true) != 0) 246 aprint_error_dev(sc->sc_dev, "couldn't enable phy %s\n", 247 phyname); 248 } 249 } 250 251 static int 252 meson_usbctrl_match(device_t parent, cfdata_t cf, void *aux) 253 { 254 struct fdt_attach_args * const faa = aux; 255 256 return of_match_compat_data(faa->faa_phandle, compat_data); 257 } 258 259 static void 260 meson_usbctrl_attach(device_t parent, device_t self, void *aux) 261 { 262 struct meson_usbctrl_softc * const sc = device_private(self); 263 struct fdt_attach_args * const faa = aux; 264 bus_addr_t addr; 265 bus_size_t size; 266 int phandle, child; 267 268 sc->sc_dev = self; 269 sc->sc_bst = faa->faa_bst; 270 sc->sc_phandle = phandle = faa->faa_phandle; 271 sc->sc_conf = of_search_compatible(phandle, compat_data)->data; 272 273 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 274 aprint_error(": couldn't get registers\n"); 275 return; 276 } 277 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 278 aprint_error(": couldn't map registers\n"); 279 return; 280 } 281 282 aprint_naive("\n"); 283 aprint_normal(": USB Controllers\n"); 284 285 sc->sc_supply = fdtbus_regulator_acquire(phandle, "vbus-supply"); 286 if (sc->sc_supply != NULL) 287 fdtbus_regulator_enable(sc->sc_supply); /* USB HOST MODE */ 288 289 meson_usbctrl_usb2_init(sc); 290 meson_usbctrl_usb_glue_init(sc); 291 meson_usbctrl_usb3_init(sc); 292 meson_usbctrl_enable_usb3_phys(sc); 293 294 for (child = OF_child(phandle); child; child = OF_peer(child)) { 295 fdt_add_child(parent, child, faa, 0); 296 } 297 } 298 299 CFATTACH_DECL_NEW(meson_usbctrl, sizeof(struct meson_usbctrl_softc), 300 meson_usbctrl_match, meson_usbctrl_attach, NULL, NULL); 301
Indexes created Mon Sep 29 21:09:56 GMT 2025