meson_usbphy.c revision 1.1
1 /* $NetBSD: meson_usbphy.c,v 1.1 2019/01/19 20:56:03 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: meson_usbphy.c,v 1.1 2019/01/19 20:56:03 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #define CBUS_REG(x) ((x) << 2) 43 #define PREI_USB_PHY_CFG_REG CBUS_REG(0x00) 44 #define PREI_USB_PHY_CFG_CLK_32K_ALT_SEL __BIT(15) 45 #define PREI_USB_PHY_CTRL_REG CBUS_REG(0x01) 46 #define PREI_USB_PHY_CTRL_FSEL __BITS(24,22) 47 #define PREI_USB_PHY_CTRL_FSEL_24M 5 48 #define PREI_USB_PHY_CTRL_FSEL_12M 2 49 #define PREI_USB_PHY_CTRL_POR __BIT(15) 50 #define PREI_USB_PHY_CTRL_CLK_DET __BIT(8) 51 #define PREI_USB_PHY_ADP_BC_REG CBUS_REG(0x03) 52 #define PREI_USB_PHY_ADP_BC_ACA_FLOATING __BIT(26) 53 #define PREI_USB_PHY_ADP_BC_ACA_ENABLE __BIT(16) 54 55 static int meson_usbphy_match(device_t, cfdata_t, void *); 56 static void meson_usbphy_attach(device_t, device_t, void *); 57 58 enum meson_usbphy_type { 59 USBPHY_MESON8B, 60 }; 61 62 static const struct of_compat_data compat_data[] = { 63 { "amlogic,meson8b-usb2-phy", USBPHY_MESON8B }, 64 { NULL } 65 }; 66 67 struct meson_usbphy_softc { 68 device_t sc_dev; 69 bus_space_tag_t sc_bst; 70 bus_space_handle_t sc_bsh; 71 int sc_phandle; 72 const char *sc_dr_mode; 73 enum meson_usbphy_type sc_type; 74 }; 75 76 #define PHY_READ(sc, reg) \ 77 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 78 #define PHY_WRITE(sc, reg, val) \ 79 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 80 81 CFATTACH_DECL_NEW(meson_usbphy, sizeof(struct meson_usbphy_softc), 82 meson_usbphy_match, meson_usbphy_attach, NULL, NULL); 83 84 static const char * 85 meson_usbphy_dr_mode(struct meson_usbphy_softc *sc) 86 { 87 int index, phandle; 88 89 index = 0; 90 while ((phandle = fdt_find_with_property("phys", &index)) != -1) { 91 const int phy_phandle = fdtbus_get_phandle(phandle, "phys"); 92 if (phy_phandle != sc->sc_phandle) 93 continue; 94 return fdtbus_get_string(phandle, "dr_mode"); 95 } 96 97 return NULL; 98 } 99 100 static void * 101 meson_usbphy_acquire(device_t dev, const void *data, size_t len) 102 { 103 if (len != 0) 104 return NULL; 105 106 return (void *)(uintptr_t)1; 107 } 108 109 static void 110 meson_usbphy_release(device_t dev, void *priv) 111 { 112 } 113 114 static int 115 meson_usbphy_enable(device_t dev, void *priv, bool enable) 116 { 117 struct meson_usbphy_softc * const sc = device_private(dev); 118 uint32_t val; 119 120 if (enable) { 121 delay(1000); 122 123 val = PHY_READ(sc, PREI_USB_PHY_CFG_REG); 124 val |= PREI_USB_PHY_CFG_CLK_32K_ALT_SEL; 125 PHY_WRITE(sc, PREI_USB_PHY_CFG_REG, val); 126 127 val = PHY_READ(sc, PREI_USB_PHY_CTRL_REG); 128 val &= ~PREI_USB_PHY_CTRL_FSEL; 129 val |= __SHIFTIN(PREI_USB_PHY_CTRL_FSEL_24M, 130 PREI_USB_PHY_CTRL_FSEL); 131 val |= PREI_USB_PHY_CTRL_POR; 132 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val); 133 134 delay(1000); 135 136 val = PHY_READ(sc, PREI_USB_PHY_CTRL_REG); 137 val &= ~PREI_USB_PHY_CTRL_POR; 138 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val); 139 140 delay(50000); 141 142 val = PHY_READ(sc, PREI_USB_PHY_CTRL_REG); 143 if ((val & PREI_USB_PHY_CTRL_CLK_DET) == 0) 144 aprint_error_dev(dev, "WARNING: USB PHY clock not detected\n"); 145 146 if (sc->sc_dr_mode && strcmp(sc->sc_dr_mode, "host") == 0) { 147 val = PHY_READ(sc, PREI_USB_PHY_ADP_BC_REG); 148 val |= PREI_USB_PHY_ADP_BC_ACA_ENABLE; 149 PHY_WRITE(sc, PREI_USB_PHY_ADP_BC_REG, val); 150 151 delay(1000); 152 153 val = PHY_READ(sc, PREI_USB_PHY_ADP_BC_REG); 154 if ((val & PREI_USB_PHY_ADP_BC_ACA_FLOATING) != 0) 155 aprint_error_dev(dev, "WARNING: USB PHY failed to enable ACA detection\n"); 156 } 157 } 158 159 return 0; 160 } 161 162 const struct fdtbus_phy_controller_func meson_usbphy_funcs = { 163 .acquire = meson_usbphy_acquire, 164 .release = meson_usbphy_release, 165 .enable = meson_usbphy_enable, 166 }; 167 168 static int 169 meson_usbphy_match(device_t parent, cfdata_t cf, void *aux) 170 { 171 struct fdt_attach_args * const faa = aux; 172 173 return of_match_compat_data(faa->faa_phandle, compat_data); 174 } 175 176 static void 177 meson_usbphy_attach(device_t parent, device_t self, void *aux) 178 { 179 struct meson_usbphy_softc * const sc = device_private(self); 180 struct fdt_attach_args * const faa = aux; 181 const int phandle = faa->faa_phandle; 182 struct fdtbus_reset *rst; 183 struct clk *clk; 184 bus_addr_t addr; 185 bus_size_t size; 186 u_int n; 187 188 sc->sc_dev = self; 189 sc->sc_bst = faa->faa_bst; 190 sc->sc_phandle = phandle; 191 sc->sc_type = of_search_compatible(phandle, compat_data)->data; 192 193 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 194 aprint_error(": couldn't get registers\n"); 195 return; 196 } 197 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 198 aprint_error(": couldn't map registers\n"); 199 return; 200 } 201 202 /* Enable clocks */ 203 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 204 if (clk_enable(clk) != 0) { 205 aprint_error(": couldn't enable clock #%d\n", n); 206 return; 207 } 208 /* De-assert resets */ 209 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 210 if (fdtbus_reset_deassert(rst) != 0) { 211 aprint_error(": couldn't de-assert reset #%d\n", n); 212 return; 213 } 214 215 sc->sc_dr_mode = meson_usbphy_dr_mode(sc); 216 217 aprint_naive("\n"); 218 aprint_normal(": USB2 PHY (%s)\n", sc->sc_dr_mode ? sc->sc_dr_mode : "unknown mode"); 219 220 fdtbus_register_phy_controller(self, phandle, &meson_usbphy_funcs); 221 } 222
Indexes created Tue Sep 30 17:09:57 GMT 2025