meson_usbphy.c revision 1.2.4.2
1 /* $NetBSD: meson_usbphy.c,v 1.2.4.2 2019/06/10 22:05:51 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: meson_usbphy.c,v 1.2.4.2 2019/06/10 22:05:51 christos Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #define CBUS_REG(x) ((x) << 2) 43 #define PREI_USB_PHY_CFG_REG CBUS_REG(0x00) 44 #define PREI_USB_PHY_CFG_CLK_32K_ALT_SEL __BIT(15) 45 #define PREI_USB_PHY_CTRL_REG CBUS_REG(0x01) 46 #define PREI_USB_PHY_CTRL_FSEL __BITS(24,22) 47 #define PREI_USB_PHY_CTRL_FSEL_24M 5 48 #define PREI_USB_PHY_CTRL_FSEL_12M 2 49 #define PREI_USB_PHY_CTRL_POR __BIT(15) 50 #define PREI_USB_PHY_CTRL_CLK_DET __BIT(8) 51 #define PREI_USB_PHY_ADP_BC_REG CBUS_REG(0x03) 52 #define PREI_USB_PHY_ADP_BC_ACA_FLOATING __BIT(26) 53 #define PREI_USB_PHY_ADP_BC_ACA_ENABLE __BIT(16) 54 55 static int meson_usbphy_match(device_t, cfdata_t, void *); 56 static void meson_usbphy_attach(device_t, device_t, void *); 57 58 enum meson_usbphy_type { 59 USBPHY_MESON8B, 60 }; 61 62 static const struct of_compat_data compat_data[] = { 63 { "amlogic,meson8b-usb2-phy", USBPHY_MESON8B }, 64 { "amlogic,meson-gxbb-usb2-phy", USBPHY_MESON8B }, 65 { NULL } 66 }; 67 68 struct meson_usbphy_softc { 69 device_t sc_dev; 70 bus_space_tag_t sc_bst; 71 bus_space_handle_t sc_bsh; 72 int sc_phandle; 73 const char *sc_dr_mode; 74 enum meson_usbphy_type sc_type; 75 }; 76 77 #define PHY_READ(sc, reg) \ 78 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 79 #define PHY_WRITE(sc, reg, val) \ 80 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 81 82 CFATTACH_DECL_NEW(meson_usbphy, sizeof(struct meson_usbphy_softc), 83 meson_usbphy_match, meson_usbphy_attach, NULL, NULL); 84 85 static const char * 86 meson_usbphy_dr_mode(struct meson_usbphy_softc *sc) 87 { 88 int index, phandle; 89 90 index = 0; 91 while ((phandle = fdt_find_with_property("phys", &index)) != -1) { 92 const int phy_phandle = fdtbus_get_phandle(phandle, "phys"); 93 if (phy_phandle != sc->sc_phandle) 94 continue; 95 return fdtbus_get_string(phandle, "dr_mode"); 96 } 97 98 return NULL; 99 } 100 101 static void * 102 meson_usbphy_acquire(device_t dev, const void *data, size_t len) 103 { 104 if (len != 0) 105 return NULL; 106 107 return (void *)(uintptr_t)1; 108 } 109 110 static void 111 meson_usbphy_release(device_t dev, void *priv) 112 { 113 } 114 115 static int 116 meson_usbphy_enable(device_t dev, void *priv, bool enable) 117 { 118 struct meson_usbphy_softc * const sc = device_private(dev); 119 struct fdtbus_regulator *reg; 120 uint32_t val; 121 int error; 122 123 if (enable) { 124 if (of_hasprop(sc->sc_phandle, "phy-supply")) { 125 reg = fdtbus_regulator_acquire(sc->sc_phandle, "phy-supply"); 126 if (reg != NULL) { 127 error = fdtbus_regulator_enable(reg); 128 if (error != 0) 129 device_printf(dev, "WARNING: couldn't enable phy-supply: %d\n", error); 130 } else { 131 device_printf(dev, "WARNING: couldn't acquire phy-supply\n"); 132 } 133 } 134 135 delay(1000); 136 137 val = PHY_READ(sc, PREI_USB_PHY_CFG_REG); 138 val |= PREI_USB_PHY_CFG_CLK_32K_ALT_SEL; 139 PHY_WRITE(sc, PREI_USB_PHY_CFG_REG, val); 140 141 val = PHY_READ(sc, PREI_USB_PHY_CTRL_REG); 142 val &= ~PREI_USB_PHY_CTRL_FSEL; 143 val |= __SHIFTIN(PREI_USB_PHY_CTRL_FSEL_24M, 144 PREI_USB_PHY_CTRL_FSEL); 145 val |= PREI_USB_PHY_CTRL_POR; 146 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val); 147 148 delay(1000); 149 150 val = PHY_READ(sc, PREI_USB_PHY_CTRL_REG); 151 val &= ~PREI_USB_PHY_CTRL_POR; 152 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val); 153 154 delay(50000); 155 156 val = PHY_READ(sc, PREI_USB_PHY_CTRL_REG); 157 if ((val & PREI_USB_PHY_CTRL_CLK_DET) == 0) 158 aprint_error_dev(dev, "WARNING: USB PHY clock not detected\n"); 159 160 if (sc->sc_dr_mode && strcmp(sc->sc_dr_mode, "host") == 0) { 161 val = PHY_READ(sc, PREI_USB_PHY_ADP_BC_REG); 162 val |= PREI_USB_PHY_ADP_BC_ACA_ENABLE; 163 PHY_WRITE(sc, PREI_USB_PHY_ADP_BC_REG, val); 164 165 delay(1000); 166 167 val = PHY_READ(sc, PREI_USB_PHY_ADP_BC_REG); 168 if ((val & PREI_USB_PHY_ADP_BC_ACA_FLOATING) != 0) 169 aprint_error_dev(dev, "WARNING: USB PHY failed to enable ACA detection\n"); 170 } 171 } 172 173 return 0; 174 } 175 176 const struct fdtbus_phy_controller_func meson_usbphy_funcs = { 177 .acquire = meson_usbphy_acquire, 178 .release = meson_usbphy_release, 179 .enable = meson_usbphy_enable, 180 }; 181 182 static int 183 meson_usbphy_match(device_t parent, cfdata_t cf, void *aux) 184 { 185 struct fdt_attach_args * const faa = aux; 186 187 return of_match_compat_data(faa->faa_phandle, compat_data); 188 } 189 190 static void 191 meson_usbphy_attach(device_t parent, device_t self, void *aux) 192 { 193 struct meson_usbphy_softc * const sc = device_private(self); 194 struct fdt_attach_args * const faa = aux; 195 const int phandle = faa->faa_phandle; 196 struct fdtbus_reset *rst; 197 struct clk *clk; 198 bus_addr_t addr; 199 bus_size_t size; 200 u_int n; 201 202 sc->sc_dev = self; 203 sc->sc_bst = faa->faa_bst; 204 sc->sc_phandle = phandle; 205 sc->sc_type = of_search_compatible(phandle, compat_data)->data; 206 207 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 208 aprint_error(": couldn't get registers\n"); 209 return; 210 } 211 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 212 aprint_error(": couldn't map registers\n"); 213 return; 214 } 215 216 /* Enable clocks */ 217 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 218 if (clk_enable(clk) != 0) { 219 aprint_error(": couldn't enable clock #%d\n", n); 220 return; 221 } 222 /* De-assert resets */ 223 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 224 if (fdtbus_reset_deassert(rst) != 0) { 225 aprint_error(": couldn't de-assert reset #%d\n", n); 226 return; 227 } 228 229 sc->sc_dr_mode = meson_usbphy_dr_mode(sc); 230 231 aprint_naive("\n"); 232 aprint_normal(": USB2 PHY (%s)\n", sc->sc_dr_mode ? sc->sc_dr_mode : "unknown mode"); 233 234 fdtbus_register_phy_controller(self, phandle, &meson_usbphy_funcs); 235 } 236
Indexes created Tue Sep 30 17:09:57 GMT 2025