1 1.1 jmcneill /* $NetBSD: meson_vpureg.h,v 1.1 2019/01/19 21:43:43 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /*- 4 1.1 jmcneill * Copyright (c) 2015 Jared McNeill <jmcneill (at) invisible.ca> 5 1.1 jmcneill * All rights reserved. 6 1.1 jmcneill * 7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without 8 1.1 jmcneill * modification, are permitted provided that the following conditions 9 1.1 jmcneill * are met: 10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright 11 1.1 jmcneill * notice, this list of conditions and the following disclaimer. 12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the 14 1.1 jmcneill * documentation and/or other materials provided with the distribution. 15 1.1 jmcneill * 16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 jmcneill * SUCH DAMAGE. 27 1.1 jmcneill */ 28 1.1 jmcneill 29 1.1 jmcneill #ifndef _MESON_VPUREG_H 30 1.1 jmcneill #define _MESON_VPUREG_H 31 1.1 jmcneill 32 1.1 jmcneill #define VPU_REG(n) ((n) << 2) 33 1.1 jmcneill 34 1.1 jmcneill #define VIU_OSD2_CTRL_STAT_REG VPU_REG(0x1a30) 35 1.1 jmcneill #define VIU_OSD2_TCOLOR_AG0_REG VPU_REG(0x1a37) 36 1.1 jmcneill #define VIU_OSD2_TCOLOR_AG1_REG VPU_REG(0x1a38) 37 1.1 jmcneill #define VIU_OSD2_TCOLOR_AG2_REG VPU_REG(0x1a39) 38 1.1 jmcneill #define VIU_OSD2_TCOLOR_AG3_REG VPU_REG(0x1a3a) 39 1.1 jmcneill #define VIU_OSD2_BLK0_CFG_W0_REG VPU_REG(0x1a3b) 40 1.1 jmcneill #define VIU_OSD2_BLK0_CFG_W1_REG VPU_REG(0x1a3c) 41 1.1 jmcneill #define VIU_OSD2_BLK0_CFG_W2_REG VPU_REG(0x1a3d) 42 1.1 jmcneill #define VIU_OSD2_BLK0_CFG_W3_REG VPU_REG(0x1a3e) 43 1.1 jmcneill #define VIU_OSD2_BLK0_CFG_W4_REG VPU_REG(0x1a64) 44 1.1 jmcneill #define VPP_MISC_REG VPU_REG(0x1d26) 45 1.1 jmcneill #define VPP_OSD_VSC_PHASE_STEP_REG VPU_REG(0x1dc0) 46 1.1 jmcneill #define VPP_OSD_VSC_INI_PHASE_REG VPU_REG(0x1dc1) 47 1.1 jmcneill #define VPP_OSD_VSC_CTRL0_REG VPU_REG(0x1dc2) 48 1.1 jmcneill #define VPP_OSD_HSC_PHASE_STEP_REG VPU_REG(0x1dc3) 49 1.1 jmcneill #define VPP_OSD_HSC_INI_PHASE_REG VPU_REG(0x1dc4) 50 1.1 jmcneill #define VPP_OSD_HSC_CTRL0_REG VPU_REG(0x1dc5) 51 1.1 jmcneill #define VPP_OSD_SC_DUMMY_DATA_REG VPU_REG(0x1dc7) 52 1.1 jmcneill #define VPP_OSD_SC_CTRL0_REG VPU_REG(0x1dc8) 53 1.1 jmcneill #define VPP_OSD_SCI_WH_M1_REG VPU_REG(0x1dc9) 54 1.1 jmcneill #define VPP_OSD_SCO_H_REG VPU_REG(0x1dca) 55 1.1 jmcneill #define VPP_OSD_SCO_V_REG VPU_REG(0x1dcb) 56 1.1 jmcneill 57 1.1 jmcneill #define VIU_OSD_CTRL_STAT_ENABLE __BIT(21) 58 1.1 jmcneill #define VIU_OSD_CTRL_STAT_GLOBAL_ALPHA __BITS(20,12) 59 1.1 jmcneill #define VIU_OSD_CTRL_STAT_BLK3_ENABLE __BIT(3) 60 1.1 jmcneill #define VIU_OSD_CTRL_STAT_BLK2_ENABLE __BIT(2) 61 1.1 jmcneill #define VIU_OSD_CTRL_STAT_BLK1_ENABLE __BIT(1) 62 1.1 jmcneill #define VIU_OSD_CTRL_STAT_BLK0_ENABLE __BIT(0) 63 1.1 jmcneill 64 1.1 jmcneill #define VIU_OSD_TCOLOR_R __BITS(31,24) 65 1.1 jmcneill #define VIU_OSD_TCOLOR_G __BITS(23,16) 66 1.1 jmcneill #define VIU_OSD_TCOLOR_B __BITS(15,8) 67 1.1 jmcneill #define VIU_OSD_TCOLOR_A __BITS(7,0) 68 1.1 jmcneill 69 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_TBL_ADDR __BITS(23,16) 70 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_LITTLE_ENDIAN __BIT(15) 71 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_RPT_Y __BIT(14) 72 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_INTERP_CTRL __BITS(13,12) 73 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE __BITS(11,8) 74 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_PAL4 0 75 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_PAL16 1 76 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_PAL256 2 77 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_YUV 3 78 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_16BPP 4 79 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_32BPP 5 80 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_24BPP 7 81 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_RGB_EN __BIT(7) 82 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_TC_ALPHA_EN __BIT(6) 83 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX __BITS(5,2) 84 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGB 0 85 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGBA 0 86 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_ARGB 1 87 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_ABGR 2 88 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_BGRA 3 89 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGB565 4 90 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_INTERLACE_EN __BIT(1) 91 1.1 jmcneill #define VIU_OSD_BLK_CFG_W0_INTERLACE_SEL_ODD __BIT(0) 92 1.1 jmcneill 93 1.1 jmcneill #define VIU_OSD_BLK_CFG_W1_X_END __BITS(28,16) 94 1.1 jmcneill #define VIU_OSD_BLK_CFG_W1_X_START __BITS(12,0) 95 1.1 jmcneill 96 1.1 jmcneill #define VIU_OSD_BLK_CFG_W2_Y_END __BITS(28,16) 97 1.1 jmcneill #define VIU_OSD_BLK_CFG_W2_Y_START __BITS(12,0) 98 1.1 jmcneill 99 1.1 jmcneill #define VIU_OSD_BLK_CFG_W3_H_END __BITS(27,16) 100 1.1 jmcneill #define VIU_OSD_BLK_CFG_W3_H_START __BITS(11,0) 101 1.1 jmcneill 102 1.1 jmcneill #define VIU_OSD_BLK_CFG_W4_V_END __BITS(27,16) 103 1.1 jmcneill #define VIU_OSD_BLK_CFG_W4_V_START __BITS(11,0) 104 1.1 jmcneill 105 1.1 jmcneill #define VPP_MISC_OSD2_PREBLEND __BIT(17) 106 1.1 jmcneill #define VPP_MISC_OSD1_PREBLEND __BIT(16) 107 1.1 jmcneill #define VPP_MISC_OSD2_POSTBLEND __BIT(13) 108 1.1 jmcneill #define VPP_MISC_OSD1_POSTBLEND __BIT(12) 109 1.1 jmcneill #define VPP_MISC_POSTBLEND __BIT(7) 110 1.1 jmcneill #define VPP_MISC_PREBLEND __BIT(6) 111 1.1 jmcneill 112 1.1 jmcneill #define VPP_OSD_VSC_PHASE_STEP_FORMAT __BITS(27,0) 113 1.1 jmcneill 114 1.1 jmcneill #define VPP_OSD_VSC_INI_PHASE_0 __BITS(31,16) 115 1.1 jmcneill #define VPP_OSD_VSC_INI_PHASE_1 __BITS(15,0) 116 1.1 jmcneill 117 1.1 jmcneill #define VPP_OSD_VSC_CTRL0_VSCALE_EN __BIT(24) 118 1.1 jmcneill #define VPP_OSC_VSC_CTRL0_INTERLACE __BIT(23) 119 1.1 jmcneill #define VPP_OSD_VSC_CTRL0_BOT_RPT_P0_NUM0 __BITS(17,16) 120 1.1 jmcneill #define VPP_OSD_VSC_CTRL0_BOT_INI_RCV_NUM0 __BITS(14,11) 121 1.1 jmcneill #define VPP_OSD_VSC_CTRL0_TOP_RPT_P0_NUM0 __BITS(9,8) 122 1.1 jmcneill #define VPP_OSD_VSC_CTRL0_TOP_INI_RCV_NUM0 __BITS(6,3) 123 1.1 jmcneill #define VPP_OSD_VSC_CTRL0_BANK_LENGTH __BITS(2,0) 124 1.1 jmcneill 125 1.1 jmcneill #define VPP_OSD_HSC_PHASE_STEP_FORMAT __BITS(27,0) 126 1.1 jmcneill 127 1.1 jmcneill #define VPP_OSD_HSC_INI_PHASE_0 __BITS(31,16) 128 1.1 jmcneill #define VPP_OSD_HSC_INI_PHASE_1 __BITS(15,0) 129 1.1 jmcneill 130 1.1 jmcneill #define VPP_OSD_HSC_CTRL0_HSCALE_EN __BIT(22) 131 1.1 jmcneill #define VPP_OSD_HSC_CTRL0_RPT_P0_NUM0 __BITS(9,8) 132 1.1 jmcneill #define VPP_OSD_HSC_CTRL0_INI_RCV_NUM0 __BITS(6,3) 133 1.1 jmcneill #define VPP_OSD_HSC_CTRL0_BANK_LENGTH __BITS(2,0) 134 1.1 jmcneill 135 1.1 jmcneill #define VPP_OSD_SC_CTRL0_OSC_SC_DIN_OSD1_ALPHA_MODE __BIT(14) 136 1.1 jmcneill #define VPP_OSD_SC_CTRL0_OSC_SC_DIN_OSD2_ALPHA_MODE __BIT(13) 137 1.1 jmcneill #define VPP_OSD_SC_CTRL0_OSC_SC_ALPHA_MODE __BIT(12) 138 1.1 jmcneill #define VPP_OSD_SC_CTRL0_DEFAULT_ALPHA __BITS(11,4) 139 1.1 jmcneill #define VPP_OSD_SC_CTRL0_OSD_SC_PATH_EN __BIT(3) 140 1.1 jmcneill #define VPP_OSD_SC_CTRL0_OSD_SC_SEL __BITS(1,0) 141 1.1 jmcneill 142 1.1 jmcneill #define VPP_OSD_SCI_WH_M1_WIDTH __BITS(28,16) 143 1.1 jmcneill #define VPP_OSD_SCI_WH_M1_HEIGHT __BITS(12,0) 144 1.1 jmcneill 145 1.1 jmcneill #define VPP_OSD_SCO_H_START __BITS(28,16) 146 1.1 jmcneill #define VPP_OSD_SCO_H_END __BITS(12,0) 147 1.1 jmcneill 148 1.1 jmcneill #define VPP_OSD_SCO_V_START __BITS(28,16) 149 1.1 jmcneill #define VPP_OSD_SCO_V_END __BITS(12,0) 150 1.1 jmcneill 151 1.1 jmcneill #endif /* _MESON_VPUREG_H */ 152