mesong12_usb2phy.c revision 1.3
1 /* $NetBSD: mesong12_usb2phy.c,v 1.3 2024/02/07 04:20:26 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2021 Ryo Shimizu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: mesong12_usb2phy.c,v 1.3 2024/02/07 04:20:26 msaitoh Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/types.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 37 #include <dev/fdt/fdtvar.h> 38 39 /* 40 * USB PHY 20: 0xff636000 41 * USB PHY 21: 0xff63a000 42 */ 43 #define USB2PHY_R00_REG 0x00 44 #define USB2PHY_R01_REG 0x04 45 #define USB2PHY_R02_REG 0x08 46 #define USB2PHY_R03_REG 0x0c 47 #define USB2PHY_R03_DISC_THRESH __BITS(7,4) 48 #define USB2PHY_R03_HSDIC_REF __BITS(3,2) 49 #define USB2PHY_R03_SQUELCH_REF __BITS(1,0) 50 #define USB2PHY_R04_REG 0x10 51 #define USB2PHY_R04_I_C2L_BIAS_TRIM __BITS(31,28) 52 #define USB2PHY_R04_TEST_BYPASS_MODE_EN __BIT(27) 53 #define USB2PHY_R04_I_C2L_CAL_DONE __BIT(26) 54 #define USB2PHY_R04_I_C2L_CAL_RESET_N __BIT(25) 55 #define USB2PHY_R04_I_C2L_CAL_EN __BIT(24) 56 #define USB2PHY_R04_CALIBRATION_CODE_VALUE __BITS(23,0) 57 #define USB2PHY_R05_REG 0x14 58 #define USB2PHY_R06_REG 0x18 59 #define USB2PHY_R07_REG 0x1c 60 #define USB2PHY_R08_REG 0x20 61 #define USB2PHY_R09_REG 0x24 62 #define USB2PHY_R10_REG 0x28 63 #define USB2PHY_R11_REG 0x2c 64 #define USB2PHY_R12_REG 0x30 65 #define USB2PHY_R13_REG 0x34 66 #define USB2PHY_R13_I_C2L_FSLS_RX_EN __BIT(30) 67 #define USB2PHY_R13_I_C2L_HS_RX_EN __BIT(29) 68 #define USB2PHY_R13_I_C2L_FS_OE __BIT(28) 69 #define USB2PHY_R13_I_C2L_HS_OE __BIT(27) 70 #define USB2PHY_R13_I_C2L_LS_EN __BIT(26) 71 #define USB2PHY_R13_I_C2L_FS_EN __BIT(25) 72 #define USB2PHY_R13_I_C2L_HS_EN __BIT(24) 73 #define USB2PHY_R13_BYPASS_HOST_DISCONNECT_ENABLE __BIT(23) 74 #define USB2PHY_R13_BYPASS_HOST_DISCONNECT_VALUE __BIT(22) 75 #define USB2PHY_R13_CLEAR_HOLD_HS_DISCONNECT __BIT(21) 76 #define USB2PHY_R13_MINIMUM_COUNT_FOR_SYNC_DETECTION __BITS(20,16) 77 #define USB2PHY_R13_UPDATE_PMA_SIGNALS __BIT(15) 78 #define USB2PHY_R13_LOAD_STAT __BIT(14) 79 #define USB2PHY_R13_CUSTOM_PATTERN_19 __BITS(7,0) 80 #define USB2PHY_R14_REG 0x38 81 #define USB2PHY_R14_BYPASS_CTRL __BITS(23,8) 82 #define USB2PHY_R14_I_C2L_ASSERT_SINGLE_ENABLE_ZERO __BIT(6) 83 #define USB2PHY_R14_I_C2L_DATA_16_8 __BIT(5) 84 #define USB2PHY_R14_PG_RSTN __BIT(4) 85 #define USB2PHY_R14_I_RPU_SW2_EN __BITS(3,2) 86 #define USB2PHY_R14_I_RPU_SW1_EN __BIT(1) 87 #define USB2PHY_R14_I_RDP_EN __BIT(0) 88 #define USB2PHY_R15_REG 0x3c 89 #define USB2PHY_R16_REG 0x40 90 #define USB2PHY_R16_USB2_MPLL_LOCK_DIG __BIT(31) 91 #define USB2PHY_R16_USB2_MPLL_LOCK __BIT(30) 92 #define USB2PHY_R16_USB2_MPLL_RESET __BIT(29) 93 #define USB2PHY_R16_USB2_MPLL_EN __BIT(28) 94 #define USB2PHY_R16_USB2_MPLL_FAST_LOCK __BIT(27) 95 #define USB2PHY_R16_USB2_MPLL_LOCK_F __BIT(26) 96 #define USB2PHY_R16_USB2_MPLL_LOCK_LONG __BITS(25,24) 97 #define USB2PHY_R16_USB2_MPLL_DCO_SDM_EN __BIT(23) 98 #define USB2PHY_R16_USB2_MPLL_LOAD __BIT(22) 99 #define USB2PHY_R16_USB2_MPLL_SDM_EN __BIT(21) 100 #define USB2PHY_R16_USB2_MPLL_TDC_MODE __BIT(20) 101 #define USB2PHY_R16_USB2_MPLL_N __BITS(14,10) 102 #define USB2PHY_R16_USB2_MPLL_M __BITS(8,0) 103 #define USB2PHY_R17_REG 0x44 104 #define USB2PHY_R17_USB2_MPLL_FILTER_PVT1 __BITS(31,28) 105 #define USB2PHY_R17_USB2_MPLL_FILTER_PVT2 __BITS(27,24) 106 #define USB2PHY_R17_USB2_MPLL_FILTER_MODE __BIT(23) 107 #define USB2PHY_R17_USB2_MPLL_LAMBDA0 __BITS(22,20) 108 #define USB2PHY_R17_USB2_MPLL_LAMBDA1 __BITS(19,17) 109 #define USB2PHY_R17_USB2_MPLL_FIX_EN __BIT(16) 110 #define USB2PHY_R17_USB2_MPLL_FRAC_IN __BITS(13,0) 111 #define USB2PHY_R18_REG 0x48 112 #define USB2PHY_R18_USB2_MPLL_ACG_RANGE __BIT(31) 113 #define USB2PHY_R18_USB2_MPLL_ADJ_LDO __BITS(30,29) 114 #define USB2PHY_R18_USB2_MPLL_ALPHA __BITS(28,26) 115 #define USB2PHY_R18_USB2_MPLL_BB_MODE __BITS(25,24) 116 #define USB2PHY_R18_USB2_MPLL_BIAS_ADJ __BITS(23,22) 117 #define USB2PHY_R18_USB2_MPLL_DATA_SEL __BITS(21,19) 118 #define USB2PHY_R18_USB2_MPLL_ROU __BITS(18,16) 119 #define USB2PHY_R18_USB2_MPLL_PFD_GAIN __BITS(15,14) 120 #define USB2PHY_R18_USB2_MPLL_DCO_CLK_SEL __BIT(13) 121 #define USB2PHY_R18_USB2_MPLL_DCO_M_EN __BIT(12) 122 #define USB2PHY_R18_USB2_MPLL_LK_S __BITS(11,6) 123 #define USB2PHY_R18_USB2_MPLL_LK_W __BITS(5,2) 124 #define USB2PHY_R18_USB2_MPLL_LKW_SEL __BITS(1,0) 125 #define USB2PHY_R19_REG 0x4c 126 #define USB2PHY_R20_REG 0x50 127 #define USB2PHY_R20_BYPASS_CAL_DONE_R5 __BIT(31) 128 #define USB2PHY_R20_USB2_BGR_DBG_1_0 __BITS(30,29) 129 #define USB2PHY_R20_USB2_BGR_VREF_4_0 __BITS(28,24) 130 #define USB2PHY_R20_USB2_BGR_START __BIT(21) 131 #define USB2PHY_R20_USB2_BGR_ADJ_4_0 __BITS(20,16) 132 #define USB2PHY_R20_USB2_EDGE_DRV_TRIM_1_0 __BITS(15,14) 133 #define USB2PHY_R20_USB2_EDGE_DRV_EN __BIT(13) 134 #define USB2PHY_R20_USB2_DMON_SEL_3_0 __BITS(12,9) 135 #define USB2PHY_R20_USB2_DMON_EN __BIT(8) 136 #define USB2PHY_R20_BYPASS_OTG_DET __BIT(7) 137 #define USB2PHY_R20_USB2_CAL_CODE_R5 __BIT(6) 138 #define USB2PHY_R20_USB2_AMON_EN __BIT(5) 139 #define USB2PHY_R20_USB2_OTG_VBUSDET_EN __BIT(4) 140 #define USB2PHY_R20_USB2_OTG_VBUS_TRIM_2_0 __BITS(3,1) 141 #define USB2PHY_R20_USB2_IDDET_EN __BIT(0) 142 #define USB2PHY_R21_REG 0x54 143 #define USB2PHY_R21_BYPASS_UTMI_REG __BITS(25,20) 144 #define USB2PHY_R21_BYPASS_UTMI_CNTR __BITS(15,6) 145 #define USB2PHY_R21_USB2_OTG_ACA_TRIM_1_0 __BITS(5,4) 146 #define USB2PHY_R21_USB2_TX_STRG_PD __BIT(3) 147 #define USB2PHY_R21_USB2_OTG_ACA_EN __BIT(2) 148 #define USB2PHY_R21_USB2_CAL_ACK_EN __BIT(1) 149 #define USB2PHY_R21_USB2_BGR_FORCE __BIT(0) 150 #define USB2PHY_R22_REG 0x58 151 #define USB2PHY_R23_REG 0x5c 152 153 #define USB2PHY_READ_REG(sc, reg) \ 154 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 155 #define USB2PHY_WRITE_REG(sc, reg, val) \ 156 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 157 158 struct mesong12_usb2phy_softc { 159 device_t sc_dev; 160 bus_space_tag_t sc_bst; 161 bus_space_handle_t sc_bsh; 162 struct clk *sc_clk; 163 struct fdtbus_reset *sc_reset; 164 struct fdtbus_regulator *sc_supply; 165 int sc_phandle; 166 }; 167 168 static void * 169 mesong12_usb2phy_acquire(device_t dev, const void *data, size_t len) 170 { 171 if (len != 0) 172 return NULL; 173 174 return (void *)(uintptr_t)1; 175 } 176 177 static void 178 mesong12_usb2phy_release(device_t dev, void *priv) 179 { 180 __nothing; 181 } 182 183 static int 184 mesong12_usb2phy_enable(device_t dev, void *priv, bool enable) 185 { 186 struct mesong12_usb2phy_softc * const sc = device_private(dev); 187 188 if (sc->sc_reset != NULL) { 189 fdtbus_reset_assert(sc->sc_reset); 190 delay(10); 191 fdtbus_reset_deassert(sc->sc_reset); 192 delay(1000); 193 } 194 195 if (sc->sc_supply != NULL) 196 fdtbus_regulator_enable(sc->sc_supply); 197 198 if (!enable) 199 return 0; 200 201 USB2PHY_WRITE_REG(sc, USB2PHY_R21_REG, 202 USB2PHY_READ_REG(sc, USB2PHY_R21_REG) | 203 USB2PHY_R21_USB2_OTG_ACA_EN); 204 205 /* set PLL to 480MHz */ 206 USB2PHY_WRITE_REG(sc, USB2PHY_R16_REG, 207 USB2PHY_R16_USB2_MPLL_RESET | 208 USB2PHY_R16_USB2_MPLL_EN | 209 USB2PHY_R16_USB2_MPLL_FAST_LOCK | 210 __SHIFTIN(1, USB2PHY_R16_USB2_MPLL_LOCK_LONG) | 211 USB2PHY_R16_USB2_MPLL_LOAD | 212 __SHIFTIN(1, USB2PHY_R16_USB2_MPLL_N) | 213 __SHIFTIN(20, USB2PHY_R16_USB2_MPLL_M)); 214 USB2PHY_WRITE_REG(sc, USB2PHY_R17_REG, 215 __SHIFTIN(0, USB2PHY_R17_USB2_MPLL_FILTER_PVT1) | 216 __SHIFTIN(7, USB2PHY_R17_USB2_MPLL_FILTER_PVT2) | 217 __SHIFTIN(7, USB2PHY_R17_USB2_MPLL_LAMBDA0) | 218 __SHIFTIN(2, USB2PHY_R17_USB2_MPLL_LAMBDA1) | 219 __SHIFTIN(9, USB2PHY_R17_USB2_MPLL_FRAC_IN)); 220 USB2PHY_WRITE_REG(sc, USB2PHY_R18_REG, 221 USB2PHY_R18_USB2_MPLL_ACG_RANGE | 222 __SHIFTIN(1, USB2PHY_R18_USB2_MPLL_ADJ_LDO) | 223 __SHIFTIN(3, USB2PHY_R18_USB2_MPLL_ALPHA) | 224 __SHIFTIN(0, USB2PHY_R18_USB2_MPLL_BB_MODE) | 225 __SHIFTIN(1, USB2PHY_R18_USB2_MPLL_BIAS_ADJ) | 226 __SHIFTIN(3, USB2PHY_R18_USB2_MPLL_DATA_SEL) | 227 __SHIFTIN(7, USB2PHY_R18_USB2_MPLL_ROU) | 228 __SHIFTIN(1, USB2PHY_R18_USB2_MPLL_PFD_GAIN) | 229 __SHIFTIN(39, USB2PHY_R18_USB2_MPLL_LK_S) | 230 __SHIFTIN(9, USB2PHY_R18_USB2_MPLL_LK_W) | 231 __SHIFTIN(1, USB2PHY_R18_USB2_MPLL_LKW_SEL)); 232 delay(100); 233 USB2PHY_WRITE_REG(sc, USB2PHY_R16_REG, 234 USB2PHY_R16_USB2_MPLL_EN | 235 USB2PHY_R16_USB2_MPLL_FAST_LOCK | 236 __SHIFTIN(1, USB2PHY_R16_USB2_MPLL_LOCK_LONG) | 237 USB2PHY_R16_USB2_MPLL_LOAD | 238 __SHIFTIN(1, USB2PHY_R16_USB2_MPLL_N) | 239 __SHIFTIN(20, USB2PHY_R16_USB2_MPLL_M)); 240 241 /* tune PHY */ 242 USB2PHY_WRITE_REG(sc, USB2PHY_R20_REG, 243 __SHIFTIN(0, USB2PHY_R20_USB2_BGR_DBG_1_0) | 244 __SHIFTIN(0, USB2PHY_R20_USB2_BGR_VREF_4_0) | 245 __SHIFTIN(0, USB2PHY_R20_USB2_BGR_ADJ_4_0) | 246 __SHIFTIN(3, USB2PHY_R20_USB2_EDGE_DRV_TRIM_1_0) | 247 USB2PHY_R20_USB2_EDGE_DRV_EN | 248 __SHIFTIN(15, USB2PHY_R20_USB2_DMON_SEL_3_0) | 249 USB2PHY_R20_USB2_OTG_VBUSDET_EN | 250 __SHIFTIN(4, USB2PHY_R20_USB2_OTG_VBUS_TRIM_2_0)); 251 252 USB2PHY_WRITE_REG(sc, USB2PHY_R04_REG, 253 __SHIFTIN(0, USB2PHY_R04_I_C2L_BIAS_TRIM) | 254 USB2PHY_R04_TEST_BYPASS_MODE_EN | 255 __SHIFTIN(0xfff, USB2PHY_R04_CALIBRATION_CODE_VALUE)); 256 257 /* tune disconnect threshold */ 258 USB2PHY_WRITE_REG(sc, USB2PHY_R03_REG, 259 __SHIFTIN(3, USB2PHY_R03_DISC_THRESH) | 260 __SHIFTIN(1, USB2PHY_R03_HSDIC_REF) | 261 __SHIFTIN(0, USB2PHY_R03_SQUELCH_REF)); 262 263 /* analog settings */ 264 USB2PHY_WRITE_REG(sc, USB2PHY_R14_REG, 265 __SHIFTIN(0, USB2PHY_R14_BYPASS_CTRL) | 266 __SHIFTIN(0, USB2PHY_R14_I_RPU_SW2_EN)); 267 USB2PHY_WRITE_REG(sc, USB2PHY_R13_REG, 268 __SHIFTIN(7, USB2PHY_R13_MINIMUM_COUNT_FOR_SYNC_DETECTION) | 269 USB2PHY_R13_UPDATE_PMA_SIGNALS); 270 271 return 0; 272 } 273 274 static const struct device_compatible_entry compat_data[] = { 275 { .compat = "amlogic,g12a-usb2-phy" }, 276 DEVICE_COMPAT_EOL 277 }; 278 279 static int 280 mesong12_usb2phy_match(device_t parent, cfdata_t cf, void *aux) 281 { 282 struct fdt_attach_args * const faa = aux; 283 284 return of_compatible_match(faa->faa_phandle, compat_data); 285 } 286 287 static const struct fdtbus_phy_controller_func mesong12_usb2phy_funcs = { 288 .acquire = mesong12_usb2phy_acquire, 289 .release = mesong12_usb2phy_release, 290 .enable = mesong12_usb2phy_enable 291 }; 292 293 static void 294 mesong12_usb2phy_attach(device_t parent, device_t self, void *aux) 295 { 296 struct mesong12_usb2phy_softc * const sc = device_private(self); 297 struct fdt_attach_args * const faa = aux; 298 const int phandle = faa->faa_phandle; 299 bus_addr_t addr; 300 bus_size_t size; 301 302 sc->sc_dev = self; 303 sc->sc_bst = faa->faa_bst; 304 sc->sc_phandle = phandle; 305 306 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 307 aprint_error(": couldn't get registers\n"); 308 return; 309 } 310 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 311 aprint_error(": couldn't map registers\n"); 312 return; 313 } 314 315 sc->sc_clk = fdtbus_clock_get_index(phandle, 0); 316 if (sc->sc_clk == NULL) { 317 aprint_error(": couldn't get clock\n"); 318 goto attach_failure; 319 } 320 if (clk_enable(sc->sc_clk) != 0) { 321 aprint_error(": couldn't enable clock\n"); 322 goto attach_failure; 323 } 324 325 sc->sc_reset = fdtbus_reset_get_index(phandle, 0); 326 sc->sc_supply = fdtbus_regulator_acquire(phandle, "phy-supply"); 327 328 aprint_naive("\n"); 329 aprint_normal(": USB2 PHY\n"); 330 331 fdtbus_register_phy_controller(self, phandle, &mesong12_usb2phy_funcs); 332 return; 333 334 attach_failure: 335 bus_space_unmap(sc->sc_bst, sc->sc_bsh, size); 336 return; 337 } 338 339 CFATTACH_DECL_NEW(mesong12_usb2phy, sizeof(struct mesong12_usb2phy_softc), 340 mesong12_usb2phy_match, mesong12_usb2phy_attach, NULL, NULL); 341
Indexes created Thu Oct 23 22:10:10 GMT 2025