mesongx_mmc.c revision 1.12
1 /* $NetBSD: mesongx_mmc.c,v 1.12 2021/01/27 01:49:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.12 2021/01/27 01:49:36 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bitops.h> 39 #include <sys/gpio.h> 40 41 #include <dev/sdmmc/sdmmcvar.h> 42 #include <dev/sdmmc/sdmmcchip.h> 43 #include <dev/sdmmc/sdmmc_ioreg.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #define SD_EMMC_CLOCK 0x00 48 #define CLOCK_CFG_V2_IRQ_SDIO_SLEEP __BIT(25) 49 #define CLOCK_CFG_V2_ALWAYS_ON __BIT(24) 50 #define CLOCK_CFG_V2_RX_DELAY __BITS(23,20) 51 #define CLOCK_CFG_V2_TX_DELAY __BITS(19,16) 52 #define CLOCK_CFG_V3_IRQ_SDIO_SLEEP __BIT(29) 53 #define CLOCK_CFG_V3_ALWAYS_ON __BIT(28) 54 #define CLOCK_CFG_V3_RX_DELAY __BITS(27,22) 55 #define CLOCK_CFG_V3_TX_DELAY __BITS(21,16) 56 #define CLOCK_CFG_SRAM_PD __BITS(15,14) 57 #define CLOCK_CFG_RX_PHASE __BITS(13,12) 58 #define CLOCK_CFG_TX_PHASE __BITS(11,10) 59 #define CLOCK_CFG_CO_PHASE __BITS(9,8) 60 #define CLOCK_CFG_SRC __BITS(7,6) 61 #define CLOCK_CFG_DIV __BITS(5,0) 62 #define SD_EMMC_DELAY 0x04 63 #define SD_EMMC_ADJUST 0x08 /* V2 */ 64 #define ADJUST_ADJ_DELAY __BITS(21,16) 65 #define ADJUST_CALI_RISE __BIT(14) 66 #define ADJUST_ADJ_ENABLE __BIT(13) 67 #define ADJUST_CALI_ENABLE __BIT(12) 68 #define ADJUST_CALI_SEL __BITS(11,8) 69 #define SD_EMMC_CALOUT 0x10 70 #define CALOUT_CALI_SETUP __BITS(15,8) 71 #define CALOUT_CALI_VLD __BIT(7) 72 #define CALOUT_CALI_IDX __BITS(5,0) 73 #define SD_EMMC_V3_ADJUST 0x0c 74 #define SD_EMMC_START 0x40 75 #define START_DESC_ADDR __BITS(31,2) 76 #define START_DESC_BUSY __BIT(1) 77 #define START_DESC_INT __BIT(0) 78 #define SD_EMMC_CFG 0x44 79 #define CFG_IP_TXD_ADJ __BITS(31,28) 80 #define CFG_ERR_ABORT __BIT(27) 81 #define CFG_IRQ_DS __BIT(26) 82 #define CFG_TXD_RETRY __BIT(25) 83 #define CFG_TXD_ADD_ERR __BIT(24) 84 #define CFG_AUTO_CLK __BIT(23) 85 #define CFG_STOP_CLK __BIT(22) 86 #define CFG_CMD_LOW __BIT(21) 87 #define CFG_CHK_DS __BIT(20) 88 #define CFG_IGNORE_OWNER __BIT(19) 89 #define CFG_SDCLK_ALWAYS_ON __BIT(18) 90 #define CFG_BLK_GAP_IP __BIT(17) 91 #define CFG_OUT_FALL __BIT(16) 92 #define CFG_RC_CC __BITS(15,12) 93 #define CFG_RESP_TIMEOUT __BIT(11,8) 94 #define CFG_BL_LEN __BITS(7,4) 95 #define CFG_DC_UGT __BIT(3) 96 #define CFG_DDR __BIT(2) 97 #define CFG_BUS_WIDTH __BITS(1,0) 98 #define CFG_BUS_WIDTH_1 0 99 #define CFG_BUS_WIDTH_4 1 100 #define CFG_BUS_WIDTH_8 2 101 #define SD_EMMC_STATUS 0x48 102 #define STATUS_CORE_BUSY __BIT(31) 103 #define STATUS_DESC_BUSY __BIT(30) 104 #define STATUS_BUS_FSM __BIT(29,26) 105 #define STATUS_DS __BIT(25) 106 #define STATUS_CMD_I __BIT(24) 107 #define STATUS_DAT_I __BITS(23,16) 108 #define STATUS_IRQ_SDIO __BIT(15) 109 #define STATUS_RESP_STATUS __BIT(14) 110 #define STATUS_END_OF_CHAIN __BIT(13) 111 #define STATUS_DESC_TIMEOUT __BIT(12) 112 #define STATUS_RESP_TIMEOUT __BIT(11) 113 #define STATUS_RESP_ERR __BIT(10) 114 #define STATUS_DESC_ERR __BIT(9) 115 #define STATUS_TXD_ERR __BIT(8) 116 #define STATUS_RXD_ERR __BITS(7,0) 117 #define STATUS_TIMEOUT (STATUS_DESC_TIMEOUT | STATUS_RESP_TIMEOUT) 118 #define STATUS_ERROR (STATUS_RESP_ERR | STATUS_DESC_ERR | STATUS_RXD_ERR | STATUS_TXD_ERR) 119 #define SD_EMMC_IRQ_EN 0x4c 120 #define IRQ_EN_CFG_SECURE __BIT(16) 121 #define IRQ_EN_IRQ_SDIO __BIT(15) 122 #define IRQ_EN_RESP_STATUS __BIT(14) 123 #define IRQ_EN_END_OF_CHAIN __BIT(13) 124 #define IRQ_EN_DESC_TIMEOUT __BIT(12) 125 #define IRQ_EN_RESP_TIMEOUT __BIT(11) 126 #define IRQ_EN_RESP_ERR __BIT(10) 127 #define IRQ_EN_DESC_ERR __BIT(9) 128 #define IRQ_EN_TXD_ERR __BIT(8) 129 #define IRQ_EN_RXD_ERR __BITS(7,0) 130 #define SD_EMMC_CMD_CFG 0x50 131 #define SD_EMMC_CMD_ARG 0x54 132 #define SD_EMMC_CMD_DAT 0x58 133 #define SD_EMMC_CMD_RSP 0x5c 134 #define SD_EMMC_CMD_RSP1 0x60 135 #define SD_EMMC_CMD_RSP2 0x64 136 #define SD_EMMC_CMD_RSP3 0x68 137 138 struct mesongx_mmc_desc { 139 uint32_t flags; 140 #define MESONGX_MMC_FLAGS_OWNER __BIT(31) 141 #define MESONGX_MMC_FLAGS_ERROR __BIT(30) 142 #define MESONGX_MMC_FLAGS_CMD_INDEX __BITS(29,24) 143 #define MESONGX_MMC_FLAGS_DATA_NUM __BIT(23) 144 #define MESONGX_MMC_FLAGS_RESP_NUM __BIT(22) 145 #define MESONGX_MMC_FLAGS_RESP_128 __BIT(21) 146 #define MESONGX_MMC_FLAGS_RESP_NOCRC __BIT(20) 147 #define MESONGX_MMC_FLAGS_DATA_WR __BIT(19) 148 #define MESONGX_MMC_FLAGS_DATA_IO __BIT(18) 149 #define MESONGX_MMC_FLAGS_NO_CMD __BIT(17) 150 #define MESONGX_MMC_FLAGS_NO_RESP __BIT(16) 151 #define MESONGX_MMC_FLAGS_TIMEOUT __BITS(15,12) 152 #define MESONGX_MMC_FLAGS_END_OF_CHAIN __BIT(11) 153 #define MESONGX_MMC_FLAGS_R1B __BIT(10) 154 #define MESONGX_MMC_FLAGS_BLOCK_MODE __BIT(9) 155 #define MESONGX_MMC_FLAGS_LENGTH __BITS(8,0) 156 uint32_t arg; 157 uint32_t data; 158 #define MESONGX_MMC_DATA_BIG_ENDIAN __BIT(1) 159 #define MESONGX_MMC_DATA_SRAM __BIT(0) 160 uint32_t resp; 161 #define MESONGX_MMC_RESP_SRAM __BIT(0) 162 } __packed; 163 164 #define MESONGX_MMC_NDESC 256 165 166 struct mesongx_mmc_softc; 167 168 static int mesongx_mmc_match(device_t, cfdata_t, void *); 169 static void mesongx_mmc_attach(device_t, device_t, void *); 170 static void mesongx_mmc_attach_i(device_t); 171 172 static int mesongx_mmc_intr(void *); 173 static int mesongx_mmc_dma_setup(struct mesongx_mmc_softc *); 174 static int mesongx_mmc_dmabounce_setup(struct mesongx_mmc_softc *); 175 176 static int mesongx_mmc_host_reset(sdmmc_chipset_handle_t); 177 static uint32_t mesongx_mmc_host_ocr(sdmmc_chipset_handle_t); 178 static int mesongx_mmc_host_maxblklen(sdmmc_chipset_handle_t); 179 static int mesongx_mmc_card_detect(sdmmc_chipset_handle_t); 180 static int mesongx_mmc_write_protect(sdmmc_chipset_handle_t); 181 static int mesongx_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 182 static int mesongx_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 183 static int mesongx_mmc_bus_width(sdmmc_chipset_handle_t, int); 184 static int mesongx_mmc_bus_rod(sdmmc_chipset_handle_t, int); 185 static int mesongx_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 186 static int mesongx_mmc_execute_tuning(sdmmc_chipset_handle_t, int); 187 static void mesongx_mmc_exec_command(sdmmc_chipset_handle_t, 188 struct sdmmc_command *); 189 static void mesongx_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 190 static void mesongx_mmc_card_intr_ack(sdmmc_chipset_handle_t); 191 192 static struct sdmmc_chip_functions mesongx_mmc_chip_functions = { 193 .host_reset = mesongx_mmc_host_reset, 194 .host_ocr = mesongx_mmc_host_ocr, 195 .host_maxblklen = mesongx_mmc_host_maxblklen, 196 .card_detect = mesongx_mmc_card_detect, 197 .write_protect = mesongx_mmc_write_protect, 198 .bus_power = mesongx_mmc_bus_power, 199 .bus_clock_ddr = mesongx_mmc_bus_clock, 200 .bus_width = mesongx_mmc_bus_width, 201 .bus_rod = mesongx_mmc_bus_rod, 202 .signal_voltage = mesongx_mmc_signal_voltage, 203 .execute_tuning = mesongx_mmc_execute_tuning, 204 .exec_command = mesongx_mmc_exec_command, 205 .card_enable_intr = mesongx_mmc_card_enable_intr, 206 .card_intr_ack = mesongx_mmc_card_intr_ack, 207 }; 208 209 struct mesongx_mmc_softc { 210 device_t sc_dev; 211 bus_space_tag_t sc_bst; 212 bus_space_handle_t sc_bsh; 213 bus_dma_tag_t sc_dmat; 214 int sc_phandle; 215 216 void *sc_ih; 217 kmutex_t sc_intr_lock; 218 kcondvar_t sc_intr_cv; 219 220 device_t sc_sdmmc_dev; 221 uint32_t sc_host_ocr; 222 int sc_hwtype; 223 224 struct sdmmc_command *sc_cmd; 225 226 bus_dma_segment_t sc_desc_segs[1]; 227 int sc_desc_nsegs; 228 bus_size_t sc_desc_size; 229 bus_dmamap_t sc_desc_map; 230 int sc_desc_ndesc; 231 void *sc_desc_desc; 232 233 bus_dmamap_t sc_dmabounce_map; 234 void *sc_dmabounce_buf; 235 size_t sc_dmabounce_buflen; 236 237 struct clk *sc_clk_core; 238 struct clk *sc_clk_clkin[2]; 239 240 struct fdtbus_reset *sc_rst; 241 242 struct fdtbus_gpio_pin *sc_gpio_cd; 243 int sc_gpio_cd_inverted; 244 struct fdtbus_gpio_pin *sc_gpio_wp; 245 int sc_gpio_wp_inverted; 246 247 struct fdtbus_regulator *sc_reg_vmmc; 248 struct fdtbus_regulator *sc_reg_vqmmc; 249 250 struct fdtbus_mmc_pwrseq *sc_pwrseq; 251 252 u_int sc_max_frequency; 253 bool sc_non_removable; 254 bool sc_broken_cd; 255 }; 256 257 CFATTACH_DECL_NEW(mesongx_mmc, sizeof(struct mesongx_mmc_softc), 258 mesongx_mmc_match, mesongx_mmc_attach, NULL, NULL); 259 260 #define MMC_WRITE(sc, reg, val) \ 261 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 262 #define MMC_READ(sc, reg) \ 263 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 264 265 enum { 266 MESONGX_MMC_V2 = 2, 267 MESONGX_MMC_V3 = 3, 268 }; 269 270 static const struct device_compatible_entry compat_data[] = { 271 { .compat = "amlogic,meson-gx-mmc", .value = MESONGX_MMC_V2 }, 272 { .compat = "amlogic,meson-gxbb-mmc", .value = MESONGX_MMC_V2 }, 273 { .compat = "amlogic,meson-axg-mmc", .value = MESONGX_MMC_V3 }, 274 DEVICE_COMPAT_EOL 275 }; 276 277 static int 278 mesongx_mmc_match(device_t parent, cfdata_t cf, void *aux) 279 { 280 struct fdt_attach_args * const faa = aux; 281 282 return of_match_compat_data(faa->faa_phandle, compat_data); 283 } 284 285 static void 286 mesongx_mmc_attach(device_t parent, device_t self, void *aux) 287 { 288 struct mesongx_mmc_softc * const sc = device_private(self); 289 struct fdt_attach_args * const faa = aux; 290 const int phandle = faa->faa_phandle; 291 char intrstr[128]; 292 bus_addr_t addr; 293 bus_size_t size; 294 295 sc->sc_hwtype = of_search_compatible(phandle, compat_data)->value; 296 297 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 298 aprint_error(": couldn't get registers\n"); 299 return; 300 } 301 302 sc->sc_clk_core = fdtbus_clock_get(phandle, "core"); 303 sc->sc_clk_clkin[0] = fdtbus_clock_get(phandle, "clkin0"); 304 sc->sc_clk_clkin[1] = fdtbus_clock_get(phandle, "clkin1"); 305 306 if (sc->sc_clk_core == NULL || sc->sc_clk_clkin[0] == NULL || 307 sc->sc_clk_clkin[1] == NULL) { 308 aprint_error(": couldn't get clocks\n"); 309 return; 310 } 311 312 sc->sc_rst = fdtbus_reset_get_index(phandle, 0); 313 if (sc->sc_rst == NULL) { 314 aprint_error(": couldn't get reset\n"); 315 return; 316 } 317 318 sc->sc_pwrseq = fdtbus_mmc_pwrseq_get(phandle); 319 320 if (clk_enable(sc->sc_clk_core) != 0) { 321 aprint_error(": couldn't enable core clock\n"); 322 return; 323 } 324 if (clk_enable(sc->sc_clk_clkin[0]) != 0 || 325 clk_enable(sc->sc_clk_clkin[1]) != 0) { 326 aprint_error(": couldn't enable clkin clocks\n"); 327 return; 328 } 329 330 if (fdtbus_reset_deassert(sc->sc_rst) != 0) { 331 aprint_error(": couldn't de-assert reset\n"); 332 return; 333 } 334 335 sc->sc_dev = self; 336 sc->sc_phandle = phandle; 337 sc->sc_bst = faa->faa_bst; 338 sc->sc_dmat = faa->faa_dmat; 339 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 340 cv_init(&sc->sc_intr_cv, "gxmmcirq"); 341 342 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 343 aprint_error(": couldn't map registers\n"); 344 return; 345 } 346 347 aprint_naive("\n"); 348 aprint_normal(": eMMC/SD/SDIO controller\n"); 349 350 sc->sc_reg_vmmc = fdtbus_regulator_acquire(phandle, "vmmc-supply"); 351 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 352 353 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 354 GPIO_PIN_INPUT); 355 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 356 GPIO_PIN_INPUT); 357 358 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 1 : 0; 359 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 1 : 0; 360 361 sc->sc_non_removable = of_hasprop(phandle, "non-removable"); 362 sc->sc_broken_cd = of_hasprop(phandle, "broken-cd"); 363 364 if (of_getprop_uint32(phandle, "max-frequency", &sc->sc_max_frequency)) 365 sc->sc_max_frequency = 52000000; 366 367 if (mesongx_mmc_dma_setup(sc) != 0 || 368 mesongx_mmc_dmabounce_setup(sc) != 0) { 369 aprint_error_dev(self, "failed to setup DMA\n"); 370 return; 371 } 372 373 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 374 aprint_error_dev(self, "failed to decode interrupt\n"); 375 return; 376 } 377 378 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_BIO, 379 FDT_INTR_MPSAFE, mesongx_mmc_intr, sc, device_xname(self)); 380 if (sc->sc_ih == NULL) { 381 aprint_error_dev(self, "failed to establish interrupt on %s\n", 382 intrstr); 383 return; 384 } 385 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 386 387 if (sc->sc_pwrseq) 388 fdtbus_mmc_pwrseq_reset(sc->sc_pwrseq); 389 390 config_interrupts(self, mesongx_mmc_attach_i); 391 } 392 393 static int 394 mesongx_mmc_dma_setup(struct mesongx_mmc_softc *sc) 395 { 396 int error; 397 398 sc->sc_desc_ndesc = MESONGX_MMC_NDESC; 399 sc->sc_desc_size = sizeof(struct mesongx_mmc_desc) * 400 sc->sc_desc_ndesc; 401 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_desc_size, 402 sizeof(struct mesongx_mmc_desc), 403 sc->sc_desc_size, sc->sc_desc_segs, 1, 404 &sc->sc_desc_nsegs, BUS_DMA_WAITOK); 405 if (error) 406 return error; 407 error = bus_dmamem_map(sc->sc_dmat, sc->sc_desc_segs, 408 sc->sc_desc_nsegs, sc->sc_desc_size, 409 &sc->sc_desc_desc, BUS_DMA_WAITOK); 410 if (error) 411 goto free; 412 error = bus_dmamap_create(sc->sc_dmat, sc->sc_desc_size, 1, 413 sc->sc_desc_size, 0, BUS_DMA_WAITOK, &sc->sc_desc_map); 414 if (error) 415 goto unmap; 416 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map, 417 sc->sc_desc_desc, sc->sc_desc_size, NULL, BUS_DMA_WAITOK); 418 if (error) 419 goto destroy; 420 return 0; 421 422 destroy: 423 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 424 unmap: 425 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc_desc, sc->sc_desc_size); 426 free: 427 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, sc->sc_desc_nsegs); 428 return error; 429 } 430 431 static int 432 mesongx_mmc_dmabounce_setup(struct mesongx_mmc_softc *sc) 433 { 434 bus_dma_segment_t ds[1]; 435 int error, rseg; 436 437 sc->sc_dmabounce_buflen = MAXPHYS; 438 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0, 439 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK); 440 if (error) 441 return error; 442 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen, 443 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK); 444 if (error) 445 goto free; 446 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1, 447 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map); 448 if (error) 449 goto unmap; 450 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map, 451 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL, 452 BUS_DMA_WAITOK); 453 if (error) 454 goto destroy; 455 return 0; 456 457 destroy: 458 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map); 459 unmap: 460 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf, 461 sc->sc_dmabounce_buflen); 462 free: 463 bus_dmamem_free(sc->sc_dmat, ds, rseg); 464 return error; 465 } 466 467 static int 468 mesongx_mmc_set_clock(struct mesongx_mmc_softc *sc, u_int freq, bool ddr) 469 { 470 int best_diff, best_sel, best_div, sel, div; 471 uint32_t val; 472 473 if (freq == 0) 474 freq = SDMMC_SDCLK_400K; 475 476 best_diff = INT_MAX; 477 best_sel = 0; 478 best_div = 0; 479 480 const u_int target_rate = (freq * 1000) << ddr; 481 for (sel = 0; sel <= 1; sel++) { 482 const u_int parent_rate = clk_get_rate(sc->sc_clk_clkin[sel]); 483 for (div = 1; div <= 63; div++) { 484 const u_int rate = parent_rate / div; 485 if (rate > target_rate) 486 continue; 487 const int diff = target_rate - rate; 488 if (diff < best_diff) { 489 best_diff = diff; 490 best_sel = sel; 491 best_div = div; 492 } 493 } 494 } 495 496 if (best_diff == INT_MAX) 497 return ERANGE; 498 499 val = MMC_READ(sc, SD_EMMC_CLOCK); 500 if (sc->sc_hwtype == MESONGX_MMC_V3) 501 val |= CLOCK_CFG_V3_ALWAYS_ON; 502 else 503 val |= CLOCK_CFG_V2_ALWAYS_ON; 504 val &= ~CLOCK_CFG_RX_PHASE; 505 val |= __SHIFTIN(0, CLOCK_CFG_RX_PHASE); 506 val &= ~CLOCK_CFG_TX_PHASE; 507 val |= __SHIFTIN(2, CLOCK_CFG_TX_PHASE); 508 val &= ~CLOCK_CFG_CO_PHASE; 509 val |= __SHIFTIN(3, CLOCK_CFG_CO_PHASE); 510 val &= ~CLOCK_CFG_SRC; 511 val |= __SHIFTIN(best_sel, CLOCK_CFG_SRC); 512 val &= ~CLOCK_CFG_DIV; 513 val |= __SHIFTIN(best_div, CLOCK_CFG_DIV); 514 MMC_WRITE(sc, SD_EMMC_CLOCK, val); 515 516 return 0; 517 } 518 519 static void 520 mesongx_mmc_attach_i(device_t self) 521 { 522 struct mesongx_mmc_softc * const sc = device_private(self); 523 struct sdmmcbus_attach_args saa; 524 uint32_t width; 525 526 if (sc->sc_pwrseq) 527 fdtbus_mmc_pwrseq_pre_power_on(sc->sc_pwrseq); 528 529 mesongx_mmc_bus_clock(sc, SDMMC_SDCLK_400K, false); 530 mesongx_mmc_host_reset(sc); 531 mesongx_mmc_bus_width(sc, 1); 532 533 if (sc->sc_pwrseq) 534 fdtbus_mmc_pwrseq_post_power_on(sc->sc_pwrseq); 535 536 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 537 width = 4; 538 539 memset(&saa, 0, sizeof(saa)); 540 saa.saa_busname = "sdmmc"; 541 saa.saa_sct = &mesongx_mmc_chip_functions; 542 saa.saa_sch = sc; 543 saa.saa_dmat = sc->sc_dmat; 544 saa.saa_clkmin = SDMMC_SDCLK_400K; 545 saa.saa_clkmax = sc->sc_max_frequency / 1000; 546 saa.saa_caps = SMC_CAPS_DMA; 547 #if notyet 548 /* XXX causes init to die when using root on eMMC with ODROID-C2 */ 549 saa.saa_caps |= SMC_CAPS_MULTI_SEG_DMA; 550 #endif 551 552 sc->sc_host_ocr = MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 553 554 if (of_getprop_bool(sc->sc_phandle, "cap-sd-highspeed")) { 555 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 556 sc->sc_host_ocr |= MMC_OCR_HCS; 557 } 558 if (of_getprop_bool(sc->sc_phandle, "cap-mmc-highspeed")) 559 saa.saa_caps |= SMC_CAPS_MMC_HIGHSPEED; 560 561 if (of_getprop_bool(sc->sc_phandle, "mmc-ddr-3_3v")) { 562 saa.saa_caps |= SMC_CAPS_MMC_DDR52; 563 } 564 565 if (of_getprop_bool(sc->sc_phandle, "mmc-ddr-1_8v")) { 566 saa.saa_caps |= SMC_CAPS_MMC_DDR52; 567 sc->sc_host_ocr |= MMC_OCR_1_65V_1_95V; 568 } 569 if (of_getprop_bool(sc->sc_phandle, "mmc-hs200-1_8v")) { 570 saa.saa_caps |= SMC_CAPS_MMC_HS200; 571 sc->sc_host_ocr |= MMC_OCR_1_65V_1_95V; 572 } 573 574 if (width == 4) 575 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 576 if (width == 8) 577 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 578 579 if (sc->sc_gpio_cd) 580 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 581 582 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 583 } 584 585 static int 586 mesongx_mmc_intr(void *priv) 587 { 588 struct mesongx_mmc_softc * const sc = priv; 589 struct sdmmc_command *cmd; 590 int rv = 0; 591 592 mutex_enter(&sc->sc_intr_lock); 593 594 const uint32_t irq_en = MMC_READ(sc, SD_EMMC_IRQ_EN); 595 const uint32_t status = MMC_READ(sc, SD_EMMC_STATUS) & irq_en; 596 597 if ((status & STATUS_IRQ_SDIO) != 0) { 598 rv = 1; 599 sdmmc_card_intr(sc->sc_sdmmc_dev); 600 } 601 602 cmd = sc->sc_cmd; 603 if (cmd == NULL) { 604 device_printf(sc->sc_dev, "WARNING: IRQ with no active command, status %#x\n", status); 605 goto done; 606 } 607 608 if ((status & STATUS_TIMEOUT) != 0) { 609 rv = 1; 610 cmd->c_error = ETIMEDOUT; 611 goto done; 612 } 613 614 if ((status & STATUS_ERROR) != 0) { 615 rv = 1; 616 cmd->c_error = EIO; 617 goto done; 618 } 619 620 if ((status & STATUS_END_OF_CHAIN) != 0 && (cmd->c_flags & SCF_ITSDONE) == 0) { 621 rv = 1; 622 if ((cmd->c_flags & SCF_RSP_PRESENT) != 0) { 623 if (cmd->c_flags & SCF_RSP_136) { 624 cmd->c_resp[0] = MMC_READ(sc, SD_EMMC_CMD_RSP); 625 cmd->c_resp[1] = MMC_READ(sc, SD_EMMC_CMD_RSP1); 626 cmd->c_resp[2] = MMC_READ(sc, SD_EMMC_CMD_RSP2); 627 cmd->c_resp[3] = MMC_READ(sc, SD_EMMC_CMD_RSP3); 628 if (cmd->c_flags & SCF_RSP_CRC) { 629 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 630 (cmd->c_resp[1] << 24); 631 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 632 (cmd->c_resp[2] << 24); 633 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 634 (cmd->c_resp[3] << 24); 635 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 636 } 637 } else { 638 cmd->c_resp[0] = MMC_READ(sc, SD_EMMC_CMD_RSP); 639 } 640 } 641 cmd->c_flags |= SCF_ITSDONE; 642 cmd->c_error = 0; 643 goto done; 644 } 645 646 done: 647 if (rv) { 648 cv_broadcast(&sc->sc_intr_cv); 649 MMC_WRITE(sc, SD_EMMC_STATUS, irq_en); 650 } 651 652 mutex_exit(&sc->sc_intr_lock); 653 654 return rv; 655 } 656 657 static int 658 mesongx_mmc_host_reset(sdmmc_chipset_handle_t sch) 659 { 660 struct mesongx_mmc_softc * const sc = sch; 661 uint32_t val; 662 663 MMC_WRITE(sc, SD_EMMC_START, 0); 664 665 val = MMC_READ(sc, SD_EMMC_CFG); 666 val &= ~CFG_RC_CC; 667 val |= __SHIFTIN(ilog2(16), CFG_RC_CC); 668 val |= CFG_SDCLK_ALWAYS_ON; 669 MMC_WRITE(sc, SD_EMMC_CFG, val); 670 671 return 0; 672 } 673 674 static uint32_t 675 mesongx_mmc_host_ocr(sdmmc_chipset_handle_t sch) 676 { 677 struct mesongx_mmc_softc * const sc = sch; 678 679 return sc->sc_host_ocr; 680 } 681 682 static int 683 mesongx_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 684 { 685 return 512; 686 } 687 688 static int 689 mesongx_mmc_card_detect(sdmmc_chipset_handle_t sch) 690 { 691 struct mesongx_mmc_softc * const sc = sch; 692 int val; 693 694 if (sc->sc_non_removable || sc->sc_broken_cd) { 695 /* 696 * Non-removable or broken card detect flag set in 697 * DT, assume always present 698 */ 699 return 1; 700 } else if (sc->sc_gpio_cd != NULL) { 701 val = fdtbus_gpio_read(sc->sc_gpio_cd); 702 if (sc->sc_gpio_cd_inverted) 703 val = !val; 704 return val; 705 } else { 706 return 1; 707 } 708 } 709 710 static int 711 mesongx_mmc_write_protect(sdmmc_chipset_handle_t sch) 712 { 713 struct mesongx_mmc_softc * const sc = sch; 714 int val; 715 716 if (sc->sc_gpio_wp != NULL) { 717 val = fdtbus_gpio_read(sc->sc_gpio_wp); 718 if (sc->sc_gpio_wp_inverted) 719 val = !val; 720 return val; 721 } 722 723 return 0; 724 } 725 726 static int 727 mesongx_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 728 { 729 return 0; 730 } 731 732 static int 733 mesongx_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 734 { 735 struct mesongx_mmc_softc * const sc = sch; 736 uint32_t val; 737 int error; 738 739 error = mesongx_mmc_set_clock(sc, freq, ddr); 740 if (error != 0) 741 return error; 742 743 val = MMC_READ(sc, SD_EMMC_CFG); 744 if (ddr) 745 val |= CFG_DDR; 746 else 747 val &= ~CFG_DDR; 748 MMC_WRITE(sc, SD_EMMC_CFG, val); 749 750 return 0; 751 } 752 753 static int 754 mesongx_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 755 { 756 struct mesongx_mmc_softc *sc = sch; 757 uint32_t val; 758 759 val = MMC_READ(sc, SD_EMMC_CFG); 760 val &= ~CFG_BUS_WIDTH; 761 762 switch (width) { 763 case 1: 764 val |= __SHIFTIN(CFG_BUS_WIDTH_1, CFG_BUS_WIDTH); 765 break; 766 case 4: 767 val |= __SHIFTIN(CFG_BUS_WIDTH_4, CFG_BUS_WIDTH); 768 break; 769 case 8: 770 val |= __SHIFTIN(CFG_BUS_WIDTH_8, CFG_BUS_WIDTH); 771 break; 772 default: 773 return EINVAL; 774 } 775 776 MMC_WRITE(sc, SD_EMMC_CFG, val); 777 778 return 0; 779 } 780 781 static int 782 mesongx_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 783 { 784 return -1; 785 } 786 787 static int 788 mesongx_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 789 { 790 struct mesongx_mmc_softc *sc = sch; 791 u_int uvol; 792 int error; 793 794 if (sc->sc_reg_vqmmc == NULL) 795 return 0; 796 797 switch (signal_voltage) { 798 case SDMMC_SIGNAL_VOLTAGE_330: 799 uvol = 3300000; 800 break; 801 case SDMMC_SIGNAL_VOLTAGE_180: 802 uvol = 1800000; 803 break; 804 default: 805 return EINVAL; 806 } 807 808 error = fdtbus_regulator_supports_voltage(sc->sc_reg_vqmmc, uvol, uvol); 809 if (error != 0) 810 return 0; 811 812 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 813 if (error != 0) 814 return error; 815 816 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 817 } 818 819 static int 820 mesongx_mmc_execute_tuning(sdmmc_chipset_handle_t sch, int timing) 821 { 822 switch (timing) { 823 case SDMMC_TIMING_MMC_HS200: 824 break; 825 default: 826 return EINVAL; 827 } 828 829 return 0; 830 } 831 832 static int 833 mesongx_mmc_dma_prepare(struct mesongx_mmc_softc *sc, struct sdmmc_command *cmd, uint32_t cmdflags) 834 { 835 struct mesongx_mmc_desc *dma = sc->sc_desc_desc; 836 bus_dmamap_t map = cmd->c_dmamap; 837 u_int xferlen, blen, resid; 838 bus_size_t off; 839 uint32_t flags; 840 int desc, seg; 841 842 if (cmd->c_blklen > 512) { 843 device_printf(sc->sc_dev, "block length %d not supported\n", cmd->c_blklen); 844 return EINVAL; 845 } 846 847 for (seg = 0; seg < map->dm_nsegs; seg++) { 848 if (map->dm_segs[seg].ds_len % cmd->c_blklen != 0) { 849 /* Force DMA bounce for unaligned transfers */ 850 map = NULL; 851 break; 852 } 853 } 854 855 if (map == NULL) { 856 map = sc->sc_dmabounce_map; 857 cmd->c_flags |= SCF_NEED_BOUNCE; 858 859 if ((cmd->c_flags & SCF_CMD_READ) != 0) { 860 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen); 861 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 862 0, cmd->c_datalen, BUS_DMASYNC_PREREAD); 863 } else { 864 memcpy(sc->sc_dmabounce_buf, cmd->c_data, cmd->c_datalen); 865 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 866 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE); 867 } 868 } 869 870 desc = 0; 871 for (seg = 0; seg < map->dm_nsegs; seg++) { 872 bus_addr_t paddr = map->dm_segs[seg].ds_addr; 873 bus_size_t len = map->dm_segs[seg].ds_len; 874 resid = uimin(len, cmd->c_resid); 875 off = 0; 876 while (resid > 0) { 877 if (desc == sc->sc_desc_ndesc) 878 break; 879 880 flags = cmdflags; 881 882 if (resid >= cmd->c_blklen) { 883 xferlen = (resid / cmd->c_blklen) * cmd->c_blklen; 884 blen = xferlen / cmd->c_blklen; 885 flags |= MESONGX_MMC_FLAGS_BLOCK_MODE; 886 } else { 887 blen = xferlen = resid; 888 } 889 KASSERT(xferlen > 0); 890 KASSERT(blen <= 512); 891 892 flags |= __SHIFTIN(blen % 512, MESONGX_MMC_FLAGS_LENGTH); 893 if (desc > 0) 894 flags |= MESONGX_MMC_FLAGS_NO_CMD; 895 if (cmd->c_resid == xferlen) 896 flags |= MESONGX_MMC_FLAGS_END_OF_CHAIN; 897 898 dma[desc].flags = htole32(flags); 899 dma[desc].arg = htole32(cmd->c_arg); 900 dma[desc].data = htole32(paddr + off); 901 dma[desc].resp = 0; 902 903 cmd->c_resid -= xferlen; 904 resid -= xferlen; 905 off += xferlen; 906 907 if (cmd->c_resid == 0) 908 break; 909 910 ++desc; 911 } 912 } 913 if (desc == sc->sc_desc_ndesc) { 914 device_printf(sc->sc_dev, 915 "not enough descriptors for %d byte transfer (%d segs)!\n", 916 cmd->c_datalen, map->dm_nsegs); 917 return EIO; 918 } 919 920 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 921 sc->sc_desc_size, BUS_DMASYNC_PREWRITE); 922 923 return 0; 924 } 925 926 static void 927 mesongx_mmc_dma_complete(struct mesongx_mmc_softc *sc, struct sdmmc_command *cmd) 928 { 929 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 930 sc->sc_desc_size, BUS_DMASYNC_POSTWRITE); 931 932 if ((cmd->c_flags & SCF_NEED_BOUNCE) != 0) { 933 if ((cmd->c_flags & SCF_CMD_READ) != 0) { 934 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 935 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD); 936 memcpy(cmd->c_data, sc->sc_dmabounce_buf, cmd->c_datalen); 937 } else { 938 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 939 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 940 } 941 } 942 } 943 944 static void 945 mesongx_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 946 { 947 struct mesongx_mmc_softc *sc = sch; 948 uint32_t cmdflags, val; 949 int error; 950 951 const uint32_t irq_mask = IRQ_EN_RESP_STATUS | 952 IRQ_EN_END_OF_CHAIN | 953 IRQ_EN_DESC_TIMEOUT | 954 IRQ_EN_RESP_TIMEOUT | 955 IRQ_EN_RESP_ERR | 956 IRQ_EN_DESC_ERR | 957 IRQ_EN_TXD_ERR | 958 IRQ_EN_RXD_ERR; 959 960 mutex_enter(&sc->sc_intr_lock); 961 962 while (sc->sc_cmd != NULL) 963 cv_wait(&sc->sc_intr_cv, &sc->sc_intr_lock); 964 sc->sc_cmd = cmd; 965 966 MMC_WRITE(sc, SD_EMMC_START, 0); 967 MMC_WRITE(sc, SD_EMMC_STATUS, MMC_READ(sc, SD_EMMC_STATUS)); 968 969 val = MMC_READ(sc, SD_EMMC_IRQ_EN); 970 MMC_WRITE(sc, SD_EMMC_IRQ_EN, val | irq_mask); 971 972 cmdflags = MESONGX_MMC_FLAGS_OWNER; 973 cmdflags |= __SHIFTIN(12, MESONGX_MMC_FLAGS_TIMEOUT); /* 2^12 = 4096 ms timeout */ 974 cmdflags |= __SHIFTIN(cmd->c_opcode, MESONGX_MMC_FLAGS_CMD_INDEX); 975 976 if ((cmd->c_flags & SCF_RSP_PRESENT) == 0) { 977 cmdflags |= MESONGX_MMC_FLAGS_NO_RESP; 978 } else { 979 cmdflags |= MESONGX_MMC_FLAGS_RESP_NUM; 980 if ((cmd->c_flags & SCF_RSP_136) != 0) 981 cmdflags |= MESONGX_MMC_FLAGS_RESP_128; 982 if ((cmd->c_flags & SCF_RSP_CRC) == 0) 983 cmdflags |= MESONGX_MMC_FLAGS_RESP_NOCRC; 984 if ((cmd->c_flags & SCF_RSP_MASK) == SCF_RSP_R1B) 985 cmdflags |= MESONGX_MMC_FLAGS_R1B; 986 } 987 988 if (cmd->c_datalen > 0) { 989 cmdflags |= MESONGX_MMC_FLAGS_DATA_IO; 990 if ((cmd->c_flags & SCF_CMD_READ) == 0) 991 cmdflags |= MESONGX_MMC_FLAGS_DATA_WR; 992 993 val = MMC_READ(sc, SD_EMMC_CFG); 994 val &= ~CFG_BL_LEN; 995 val |= __SHIFTIN(ilog2(cmd->c_blklen), CFG_BL_LEN); 996 MMC_WRITE(sc, SD_EMMC_CFG, val); 997 998 cmd->c_resid = cmd->c_datalen; 999 cmd->c_error = mesongx_mmc_dma_prepare(sc, cmd, cmdflags); 1000 if (cmd->c_error != 0) 1001 goto done; 1002 1003 const bus_addr_t desc_paddr = sc->sc_desc_map->dm_segs[0].ds_addr; 1004 MMC_WRITE(sc, SD_EMMC_START, desc_paddr | START_DESC_BUSY); /* starts transfer */ 1005 } else { 1006 MMC_WRITE(sc, SD_EMMC_CMD_CFG, cmdflags | MESONGX_MMC_FLAGS_END_OF_CHAIN); 1007 MMC_WRITE(sc, SD_EMMC_CMD_DAT, 0); 1008 MMC_WRITE(sc, SD_EMMC_CMD_ARG, cmd->c_arg); /* starts transfer */ 1009 } 1010 1011 struct bintime timeout = { .sec = 5, .frac = 0 }; 1012 const struct bintime epsilon = { .sec = 1, .frac = 0 }; 1013 1014 while ((cmd->c_flags & SCF_ITSDONE) == 0 && cmd->c_error == 0) { 1015 error = cv_timedwaitbt(&sc->sc_intr_cv, &sc->sc_intr_lock, &timeout, &epsilon); 1016 if (error != 0) { 1017 cmd->c_error = error; 1018 goto done; 1019 } 1020 } 1021 1022 if (cmd->c_error == 0 && cmd->c_datalen > 0) 1023 mesongx_mmc_dma_complete(sc, cmd); 1024 1025 done: 1026 MMC_WRITE(sc, SD_EMMC_START, 0); 1027 1028 val = MMC_READ(sc, SD_EMMC_IRQ_EN); 1029 MMC_WRITE(sc, SD_EMMC_IRQ_EN, val & ~irq_mask); 1030 1031 sc->sc_cmd = NULL; 1032 cv_broadcast(&sc->sc_intr_cv); 1033 1034 #ifdef MESONGX_MMC_DEBUG 1035 if (cmd->c_error != 0) { 1036 for (u_int reg = 0x00; reg < 0x100; reg += 0x10) { 1037 device_printf(sc->sc_dev, " %02x: %08x %08x %08x %08x\n", reg, 1038 MMC_READ(sc, reg + 0), 1039 MMC_READ(sc, reg + 4), 1040 MMC_READ(sc, reg + 8), 1041 MMC_READ(sc, reg + 12)); 1042 } 1043 } 1044 #endif 1045 1046 mutex_exit(&sc->sc_intr_lock); 1047 } 1048 1049 static void 1050 mesongx_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1051 { 1052 struct mesongx_mmc_softc * const sc = sch; 1053 uint32_t val; 1054 1055 mutex_enter(&sc->sc_intr_lock); 1056 1057 val = MMC_READ(sc, SD_EMMC_IRQ_EN); 1058 MMC_WRITE(sc, SD_EMMC_IRQ_EN, val | IRQ_EN_IRQ_SDIO); 1059 1060 mutex_exit(&sc->sc_intr_lock); 1061 } 1062 1063 static void 1064 mesongx_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 1065 { 1066 struct mesongx_mmc_softc *sc = sch; 1067 1068 MMC_WRITE(sc, SD_EMMC_STATUS, STATUS_IRQ_SDIO); 1069 } 1070
Indexes created Thu Oct 16 14:10:15 GMT 2025