xref: /src/sys/arch/arm/amlogic/mesongxbb_clkc.h

/* $NetBSD: mesongxbb_clkc.h,v 1.1 2019/02/25 19:30:17 jmcneill Exp $ */

/*-
 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef _MESONGXBB_CLKC_H
#define _MESONGXBB_CLKC_H

#define	MESONGXBB_CLOCK_SYS_PLL				0
#define	MESONGXBB_CLOCK_HDMI_PLL			2
#define	MESONGXBB_CLOCK_FIXED_PLL			3
#define	MESONGXBB_CLOCK_FCLK_DIV2			4
#define	MESONGXBB_CLOCK_FCLK_DIV3			5
#define	MESONGXBB_CLOCK_FCLK_DIV4			6
#define	MESONGXBB_CLOCK_FCLK_DIV5			7
#define	MESONGXBB_CLOCK_FCLK_DIV7			8
#define	MESONGXBB_CLOCK_GP0_PLL				9
#define	MESONGXBB_CLOCK_MPEG_SEL			10
#define	MESONGXBB_CLOCK_MPEG_DIV			11
#define	MESONGXBB_CLOCK_CLK81				12
#define	MESONGXBB_CLOCK_MPLL0				13
#define	MESONGXBB_CLOCK_MPLL1				14
#define	MESONGXBB_CLOCK_MPLL2				15
#define	MESONGXBB_CLOCK_DDR				16
#define	MESONGXBB_CLOCK_DOS				17
#define	MESONGXBB_CLOCK_ISA				18
#define	MESONGXBB_CLOCK_PL301				19
#define	MESONGXBB_CLOCK_PERIPHS				20
#define	MESONGXBB_CLOCK_SPICC				21
#define	MESONGXBB_CLOCK_I2C				22
#define	MESONGXBB_CLOCK_SAR_ADC				23
#define	MESONGXBB_CLOCK_SMART_CARD			24
#define	MESONGXBB_CLOCK_RNG0				25
#define	MESONGXBB_CLOCK_UART0				26
#define	MESONGXBB_CLOCK_SDHC				27
#define	MESONGXBB_CLOCK_STREAM				28
#define	MESONGXBB_CLOCK_ASYNC_FIFO			29
#define	MESONGXBB_CLOCK_SDIO				30
#define	MESONGXBB_CLOCK_ABUF				31
#define	MESONGXBB_CLOCK_HIU_IFACE			32
#define	MESONGXBB_CLOCK_ASSIST_MISC			33
#define	MESONGXBB_CLOCK_SPI				34
#define	MESONGXBB_CLOCK_I2S_SPDIF			35
#define	MESONGXBB_CLOCK_ETH				36
#define	MESONGXBB_CLOCK_DEMUX				37
#define	MESONGXBB_CLOCK_AIU_GLUE			38
#define	MESONGXBB_CLOCK_IEC958				39
#define	MESONGXBB_CLOCK_I2S_OUT				40
#define	MESONGXBB_CLOCK_AMCLK				41
#define	MESONGXBB_CLOCK_AIFIFO2				42
#define	MESONGXBB_CLOCK_MIXER				43
#define	MESONGXBB_CLOCK_MIXER_IFACE			44
#define	MESONGXBB_CLOCK_ADC				45
#define	MESONGXBB_CLOCK_BLKMV				46
#define	MESONGXBB_CLOCK_AIU				47
#define	MESONGXBB_CLOCK_UART1				48
#define	MESONGXBB_CLOCK_G2D				49
#define	MESONGXBB_CLOCK_USB0				50
#define	MESONGXBB_CLOCK_USB1				51
#define	MESONGXBB_CLOCK_RESET				52
#define	MESONGXBB_CLOCK_NAND				53
#define	MESONGXBB_CLOCK_DOS_PARSER			54
#define	MESONGXBB_CLOCK_USB				55
#define	MESONGXBB_CLOCK_VDIN1				56
#define	MESONGXBB_CLOCK_AHB_ARB0			57
#define	MESONGXBB_CLOCK_EFUSE				58
#define	MESONGXBB_CLOCK_BOOT_ROM			59
#define	MESONGXBB_CLOCK_AHB_DATA_BUS			60
#define	MESONGXBB_CLOCK_AHB_CTRL_BUS			61
#define	MESONGXBB_CLOCK_HDMI_INTR_SYNC			62
#define	MESONGXBB_CLOCK_HDMI_PCLK			63
#define	MESONGXBB_CLOCK_USB1_DDR_BRIDGE			64
#define	MESONGXBB_CLOCK_USB0_DDR_BRIDGE			65
#define	MESONGXBB_CLOCK_MMC_PCLK			66
#define	MESONGXBB_CLOCK_DVIN				67
#define	MESONGXBB_CLOCK_UART2				68
#define	MESONGXBB_CLOCK_SANA				69
#define	MESONGXBB_CLOCK_VPU_INTR			70
#define	MESONGXBB_CLOCK_SEC_AHB_AHB3_BRIDGE		71
#define	MESONGXBB_CLOCK_CLK81_A53			72
#define	MESONGXBB_CLOCK_VCLK2_VENCI0			73
#define	MESONGXBB_CLOCK_VCLK2_VENCI1			74
#define	MESONGXBB_CLOCK_VCLK2_VENCP0			75
#define	MESONGXBB_CLOCK_VCLK2_VENCP1			76
#define	MESONGXBB_CLOCK_GCLK_VENCI_INT0			77
#define	MESONGXBB_CLOCK_GCLK_VENCI_INT			78
#define	MESONGXBB_CLOCK_DAC_CLK				79
#define	MESONGXBB_CLOCK_AOCLK_GATE			80
#define	MESONGXBB_CLOCK_IEC958_GATE			81
#define	MESONGXBB_CLOCK_ENC480P				82
#define	MESONGXBB_CLOCK_RNG1				83
#define	MESONGXBB_CLOCK_GCLK_VENCI_INT1			84
#define	MESONGXBB_CLOCK_VCLK2_VENCLMCC			85
#define	MESONGXBB_CLOCK_VCLK2_VENCL			86
#define	MESONGXBB_CLOCK_VCLK_OTHER			87
#define	MESONGXBB_CLOCK_EDP				88
#define	MESONGXBB_CLOCK_AO_MEDIA_CPU			89
#define	MESONGXBB_CLOCK_AO_AHB_SRAM			90
#define	MESONGXBB_CLOCK_AO_AHB_BUS			91
#define	MESONGXBB_CLOCK_AO_IFACE			92
#define	MESONGXBB_CLOCK_AO_I2C				93
#define	MESONGXBB_CLOCK_SD_EMMC_A			94
#define	MESONGXBB_CLOCK_SD_EMMC_B			95
#define	MESONGXBB_CLOCK_SD_EMMC_C			96
#define	MESONGXBB_CLOCK_SAR_ADC_CLK			97
#define	MESONGXBB_CLOCK_SAR_ADC_SEL			98
#define	MESONGXBB_CLOCK_SAR_ADC_DIV			99
#define	MESONGXBB_CLOCK_MALI_0_SEL			100
#define	MESONGXBB_CLOCK_MALI_0_DIV			101
#define	MESONGXBB_CLOCK_MALI_0				102
#define	MESONGXBB_CLOCK_MALI_1_SEL			103
#define	MESONGXBB_CLOCK_MALI_1_DIV			104
#define	MESONGXBB_CLOCK_MALI_1				105
#define	MESONGXBB_CLOCK_MALI				106
#define	MESONGXBB_CLOCK_CTS_AMCLK			107
#define	MESONGXBB_CLOCK_CTS_AMCLK_SEL			108
#define	MESONGXBB_CLOCK_CTS_AMCLK_DIV			109
#define	MESONGXBB_CLOCK_CTS_MCLK_I958			110
#define	MESONGXBB_CLOCK_CTS_MCLK_I958_SEL		111
#define	MESONGXBB_CLOCK_CTS_MCLK_I958_DIV		112
#define	MESONGXBB_CLOCK_CTS_I958			113
#define	MESONGXBB_CLOCK_32K_CLK				114
#define	MESONGXBB_CLOCK_32K_CLK_SEL			115
#define	MESONGXBB_CLOCK_32K_CLK_DIV			116
#define	MESONGXBB_CLOCK_SD_EMMC_A_CLK0_SEL		117
#define	MESONGXBB_CLOCK_SD_EMMC_A_CLK0_DIV		118
#define	MESONGXBB_CLOCK_SD_EMMC_A_CLK0			119
#define	MESONGXBB_CLOCK_SD_EMMC_B_CLK0_SEL		120
#define	MESONGXBB_CLOCK_SD_EMMC_B_CLK0_DIV		121
#define	MESONGXBB_CLOCK_SD_EMMC_B_CLK0			122
#define	MESONGXBB_CLOCK_SD_EMMC_C_CLK0_SEL		123
#define	MESONGXBB_CLOCK_SD_EMMC_C_CLK0_DIV		124
#define	MESONGXBB_CLOCK_SD_EMMC_C_CLK0			125
#define	MESONGXBB_CLOCK_VPU_0_SEL			126
#define	MESONGXBB_CLOCK_VPU_0_DIV			127
#define	MESONGXBB_CLOCK_VPU_0				128
#define	MESONGXBB_CLOCK_VPU_1_SEL			129
#define	MESONGXBB_CLOCK_VPU_1_DIV			130
#define	MESONGXBB_CLOCK_VPU_1				131
#define	MESONGXBB_CLOCK_VPU				132
#define	MESONGXBB_CLOCK_VAPB_0_SEL			133
#define	MESONGXBB_CLOCK_VAPB_0_DIV			134
#define	MESONGXBB_CLOCK_VAPB_0				135
#define	MESONGXBB_CLOCK_VAPB_1_SEL			136
#define	MESONGXBB_CLOCK_VAPB_1_DIV			137
#define	MESONGXBB_CLOCK_VAPB_1				138
#define	MESONGXBB_CLOCK_VAPB_SEL			139
#define	MESONGXBB_CLOCK_VAPB				140
#define	MESONGXBB_CLOCK_HDMI_PLL_PRE_MULT		141
#define	MESONGXBB_CLOCK_MPLL0_DIV			142
#define	MESONGXBB_CLOCK_MPLL1_DIV			143
#define	MESONGXBB_CLOCK_MPLL2_DIV			144
#define	MESONGXBB_CLOCK_MPLL_PREDIV			145
#define	MESONGXBB_CLOCK_FCLK_DIV2_DIV			146
#define	MESONGXBB_CLOCK_FCLK_DIV3_DIV			147
#define	MESONGXBB_CLOCK_FCLK_DIV4_DIV			148
#define	MESONGXBB_CLOCK_FCLK_DIV5_DIV			149
#define	MESONGXBB_CLOCK_FCLK_DIV7_DIV			150
#define	MESONGXBB_CLOCK_VDEC_1_SEL			151
#define	MESONGXBB_CLOCK_VDEC_1_DIV			152
#define	MESONGXBB_CLOCK_VDEC_1				153
#define	MESONGXBB_CLOCK_VDEC_HEVC_SEL			154
#define	MESONGXBB_CLOCK_VDEC_HEVC_DIV			155
#define	MESONGXBB_CLOCK_VDEC_HEVC			156
#define	MESONGXBB_CLOCK_GEN_CLK_SEL			157
#define	MESONGXBB_CLOCK_GEN_CLK_DIV			158
#define	MESONGXBB_CLOCK_GEN_CLK				159
#define	MESONGXBB_CLOCK_FIXED_PLL_DCO			160
#define	MESONGXBB_CLOCK_HDMI_PLL_DCO			161
#define	MESONGXBB_CLOCK_HDMI_PLL_OD			162
#define	MESONGXBB_CLOCK_HDMI_PLL_OD2			163
#define	MESONGXBB_CLOCK_SYS_PLL_DCO			164
#define	MESONGXBB_CLOCK_GP0_PLL_DCO			165

#endif /* _MESONGXBB_CLKC_H */