mesongxbb_pinctrl.c revision 1.2.4.2
1 /* $NetBSD: mesongxbb_pinctrl.c,v 1.2.4.2 2019/06/10 22:05:51 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: mesongxbb_pinctrl.c,v 1.2.4.2 2019/06/10 22:05:51 christos Exp $"); 31 32 #include <sys/param.h> 33 34 #include <arm/amlogic/meson_pinctrl.h> 35 36 /* CBUS pinmux registers */ 37 #define CBUS_REG(n) ((n) << 2) 38 #define REG0 CBUS_REG(0) 39 #define REG1 CBUS_REG(1) 40 #define REG2 CBUS_REG(2) 41 #define REG3 CBUS_REG(3) 42 #define REG4 CBUS_REG(4) 43 #define REG5 CBUS_REG(5) 44 #define REG6 CBUS_REG(6) 45 #define REG7 CBUS_REG(7) 46 #define REG8 CBUS_REG(8) 47 #define REG9 CBUS_REG(9) 48 49 /* AO pinmux registers */ 50 #define AOREG0 0x00 51 #define AOREG1 0x04 52 53 /* 54 * GPIO banks. The values must match those in dt-bindings/gpio/meson-gxbb-gpio.h 55 */ 56 enum { 57 GPIOZ_0 = 0, 58 GPIOZ_1, 59 GPIOZ_2, 60 GPIOZ_3, 61 GPIOZ_4, 62 GPIOZ_5, 63 GPIOZ_6, 64 GPIOZ_7, 65 GPIOZ_8, 66 GPIOZ_9, 67 GPIOZ_10, 68 GPIOZ_11, 69 GPIOZ_12, 70 GPIOZ_13, 71 GPIOZ_14, 72 GPIOZ_15, 73 74 GPIOH_0 = 16, 75 GPIOH_1, 76 GPIOH_2, 77 GPIOH_3, 78 79 BOOT_0 = 20, 80 BOOT_1, 81 BOOT_2, 82 BOOT_3, 83 BOOT_4, 84 BOOT_5, 85 BOOT_6, 86 BOOT_7, 87 BOOT_8, 88 BOOT_9, 89 BOOT_10, 90 BOOT_11, 91 BOOT_12, 92 BOOT_13, 93 BOOT_14, 94 BOOT_15, 95 BOOT_16, 96 BOOT_17, 97 98 CARD_0 = 38, 99 CARD_1, 100 CARD_2, 101 CARD_3, 102 CARD_4, 103 CARD_5, 104 CARD_6, 105 106 GPIODV_0 = 45, 107 GPIODV_1, 108 GPIODV_2, 109 GPIODV_3, 110 GPIODV_4, 111 GPIODV_5, 112 GPIODV_6, 113 GPIODV_7, 114 GPIODV_8, 115 GPIODV_9, 116 GPIODV_10, 117 GPIODV_11, 118 GPIODV_12, 119 GPIODV_13, 120 GPIODV_14, 121 GPIODV_15, 122 GPIODV_16, 123 GPIODV_17, 124 GPIODV_18, 125 GPIODV_19, 126 GPIODV_20, 127 GPIODV_21, 128 GPIODV_22, 129 GPIODV_23, 130 GPIODV_24, 131 GPIODV_25, 132 GPIODV_26, 133 GPIODV_27, 134 GPIODV_28, 135 GPIODV_29, 136 137 GPIOY_0 = 75, 138 GPIOY_1, 139 GPIOY_2, 140 GPIOY_3, 141 GPIOY_4, 142 GPIOY_5, 143 GPIOY_6, 144 GPIOY_7, 145 GPIOY_8, 146 GPIOY_9, 147 GPIOY_10, 148 GPIOY_11, 149 GPIOY_12, 150 GPIOY_13, 151 GPIOY_14, 152 GPIOY_15, 153 GPIOY_16, 154 155 GPIOX_0 = 92, 156 GPIOX_1, 157 GPIOX_2, 158 GPIOX_3, 159 GPIOX_4, 160 GPIOX_5, 161 GPIOX_6, 162 GPIOX_7, 163 GPIOX_8, 164 GPIOX_9, 165 GPIOX_10, 166 GPIOX_11, 167 GPIOX_12, 168 GPIOX_13, 169 GPIOX_14, 170 GPIOX_15, 171 GPIOX_16, 172 GPIOX_17, 173 GPIOX_18, 174 GPIOX_19, 175 GPIOX_20, 176 GPIOX_21, 177 GPIOX_22, 178 179 GPIOCLK_0 = 115, 180 GPIOCLK_1, 181 GPIOCLK_2, 182 GPIOCLK_3, 183 184 GPIOAO_0 = 0, 185 GPIOAO_1, 186 GPIOAO_2, 187 GPIOAO_3, 188 GPIOAO_4, 189 GPIOAO_5, 190 GPIOAO_6, 191 GPIOAO_7, 192 GPIOAO_8, 193 GPIOAO_9, 194 GPIOAO_10, 195 GPIOAO_11, 196 GPIOAO_12, 197 GPIOAO_13, 198 GPIO_TEST_N, 199 }; 200 201 #define CBUS_GPIO(_id, _off, _bit) \ 202 [_id] = { \ 203 .id = (_id), \ 204 .name = __STRING(_id), \ 205 .oen = { \ 206 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 207 .reg = CBUS_REG((_off) * 3 + 0), \ 208 .mask = __BIT(_bit) \ 209 }, \ 210 .out = { \ 211 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 212 .reg = CBUS_REG((_off) * 3 + 1), \ 213 .mask = __BIT(_bit) \ 214 }, \ 215 .in = { \ 216 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 217 .reg = CBUS_REG((_off) * 3 + 2), \ 218 .mask = __BIT(_bit) \ 219 }, \ 220 .pupden = { \ 221 .type = MESON_PINCTRL_REGTYPE_PULL_ENABLE, \ 222 .reg = CBUS_REG(_off), \ 223 .mask = __BIT(_bit) \ 224 }, \ 225 .pupd = { \ 226 .type = MESON_PINCTRL_REGTYPE_PULL, \ 227 .reg = CBUS_REG(_off), \ 228 .mask = __BIT(_bit) \ 229 }, \ 230 } 231 232 static const struct meson_pinctrl_gpio mesongxbb_periphs_gpios[] = { 233 /* GPIODV */ 234 CBUS_GPIO(GPIODV_0, 0, 0), 235 CBUS_GPIO(GPIODV_1, 0, 1), 236 CBUS_GPIO(GPIODV_2, 0, 2), 237 CBUS_GPIO(GPIODV_3, 0, 3), 238 CBUS_GPIO(GPIODV_4, 0, 4), 239 CBUS_GPIO(GPIODV_5, 0, 5), 240 CBUS_GPIO(GPIODV_6, 0, 6), 241 CBUS_GPIO(GPIODV_7, 0, 7), 242 CBUS_GPIO(GPIODV_8, 0, 8), 243 CBUS_GPIO(GPIODV_9, 0, 9), 244 CBUS_GPIO(GPIODV_10, 0, 10), 245 CBUS_GPIO(GPIODV_11, 0, 11), 246 CBUS_GPIO(GPIODV_12, 0, 12), 247 CBUS_GPIO(GPIODV_13, 0, 13), 248 CBUS_GPIO(GPIODV_14, 0, 14), 249 CBUS_GPIO(GPIODV_15, 0, 15), 250 CBUS_GPIO(GPIODV_16, 0, 16), 251 CBUS_GPIO(GPIODV_17, 0, 17), 252 CBUS_GPIO(GPIODV_18, 0, 18), 253 CBUS_GPIO(GPIODV_19, 0, 19), 254 CBUS_GPIO(GPIODV_20, 0, 20), 255 CBUS_GPIO(GPIODV_21, 0, 21), 256 CBUS_GPIO(GPIODV_22, 0, 22), 257 258 /* GPIOY */ 259 CBUS_GPIO(GPIOY_0, 1, 0), 260 CBUS_GPIO(GPIOY_1, 1, 1), 261 CBUS_GPIO(GPIOY_2, 1, 2), 262 CBUS_GPIO(GPIOY_3, 1, 3), 263 CBUS_GPIO(GPIOY_4, 1, 4), 264 CBUS_GPIO(GPIOY_5, 1, 5), 265 CBUS_GPIO(GPIOY_6, 1, 6), 266 CBUS_GPIO(GPIOY_7, 1, 7), 267 CBUS_GPIO(GPIOY_8, 1, 8), 268 CBUS_GPIO(GPIOY_9, 1, 9), 269 CBUS_GPIO(GPIOY_10, 1, 10), 270 CBUS_GPIO(GPIOY_11, 1, 11), 271 CBUS_GPIO(GPIOY_12, 1, 12), 272 CBUS_GPIO(GPIOY_13, 1, 13), 273 CBUS_GPIO(GPIOY_14, 1, 14), 274 CBUS_GPIO(GPIOY_15, 1, 15), 275 CBUS_GPIO(GPIOY_16, 1, 16), 276 277 /* GPIOH */ 278 CBUS_GPIO(GPIOH_0, 1, 20), 279 CBUS_GPIO(GPIOH_1, 1, 21), 280 CBUS_GPIO(GPIOH_2, 1, 22), 281 CBUS_GPIO(GPIOH_3, 1, 23), 282 283 /* BOOT */ 284 CBUS_GPIO(BOOT_0, 2, 0), 285 CBUS_GPIO(BOOT_1, 2, 1), 286 CBUS_GPIO(BOOT_2, 2, 2), 287 CBUS_GPIO(BOOT_3, 2, 3), 288 CBUS_GPIO(BOOT_4, 2, 4), 289 CBUS_GPIO(BOOT_5, 2, 5), 290 CBUS_GPIO(BOOT_6, 2, 6), 291 CBUS_GPIO(BOOT_7, 2, 7), 292 CBUS_GPIO(BOOT_8, 2, 8), 293 CBUS_GPIO(BOOT_9, 2, 9), 294 CBUS_GPIO(BOOT_10, 2, 10), 295 CBUS_GPIO(BOOT_11, 2, 11), 296 CBUS_GPIO(BOOT_12, 2, 12), 297 CBUS_GPIO(BOOT_13, 2, 13), 298 CBUS_GPIO(BOOT_14, 2, 14), 299 CBUS_GPIO(BOOT_15, 2, 15), 300 CBUS_GPIO(BOOT_16, 2, 16), 301 CBUS_GPIO(BOOT_17, 2, 17), 302 303 /* CARD */ 304 CBUS_GPIO(CARD_0, 2, 20), 305 CBUS_GPIO(CARD_1, 2, 21), 306 CBUS_GPIO(CARD_2, 2, 22), 307 CBUS_GPIO(CARD_3, 2, 23), 308 CBUS_GPIO(CARD_4, 2, 24), 309 CBUS_GPIO(CARD_5, 2, 25), 310 CBUS_GPIO(CARD_6, 2, 26), 311 312 /* CARD */ 313 CBUS_GPIO(GPIOCLK_0, 3, 28), 314 CBUS_GPIO(GPIOCLK_1, 3, 29), 315 CBUS_GPIO(GPIOCLK_2, 3, 30), 316 CBUS_GPIO(GPIOCLK_3, 3, 31), 317 318 /* GPIOX */ 319 CBUS_GPIO(GPIOX_0, 4, 0), 320 CBUS_GPIO(GPIOX_1, 4, 1), 321 CBUS_GPIO(GPIOX_2, 4, 2), 322 CBUS_GPIO(GPIOX_3, 4, 3), 323 CBUS_GPIO(GPIOX_4, 4, 4), 324 CBUS_GPIO(GPIOX_5, 4, 5), 325 CBUS_GPIO(GPIOX_6, 4, 6), 326 CBUS_GPIO(GPIOX_7, 4, 7), 327 CBUS_GPIO(GPIOX_8, 4, 8), 328 CBUS_GPIO(GPIOX_9, 4, 9), 329 CBUS_GPIO(GPIOX_10, 4, 10), 330 CBUS_GPIO(GPIOX_11, 4, 11), 331 CBUS_GPIO(GPIOX_12, 4, 12), 332 CBUS_GPIO(GPIOX_13, 4, 13), 333 CBUS_GPIO(GPIOX_14, 4, 14), 334 CBUS_GPIO(GPIOX_15, 4, 15), 335 CBUS_GPIO(GPIOX_16, 4, 16), 336 CBUS_GPIO(GPIOX_17, 4, 17), 337 CBUS_GPIO(GPIOX_18, 4, 18), 338 CBUS_GPIO(GPIOX_19, 4, 19), 339 CBUS_GPIO(GPIOX_20, 4, 20), 340 CBUS_GPIO(GPIOX_21, 4, 21), 341 CBUS_GPIO(GPIOX_22, 4, 22), 342 }; 343 344 #define AO_GPIO(_id, _bit) \ 345 [_id] = { \ 346 .id = (_id), \ 347 .name = __STRING(_id), \ 348 .oen = { \ 349 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 350 .reg = 0, \ 351 .mask = __BIT(_bit) \ 352 }, \ 353 .out = { \ 354 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 355 .reg = 0, \ 356 .mask = __BIT(_bit + 16) \ 357 }, \ 358 .in = { \ 359 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 360 .reg = 4, \ 361 .mask = __BIT(_bit) \ 362 }, \ 363 .pupden = { \ 364 .type = MESON_PINCTRL_REGTYPE_PULL, \ 365 .reg = 0, \ 366 .mask = __BIT(_bit) \ 367 }, \ 368 .pupd = { \ 369 .type = MESON_PINCTRL_REGTYPE_PULL, \ 370 .reg = 0, \ 371 .mask = __BIT(_bit + 16) \ 372 }, \ 373 } 374 375 static const struct meson_pinctrl_gpio mesongxbb_aobus_gpios[] = { 376 /* GPIOAO */ 377 AO_GPIO(GPIOAO_0, 0), 378 AO_GPIO(GPIOAO_1, 1), 379 AO_GPIO(GPIOAO_2, 2), 380 AO_GPIO(GPIOAO_3, 3), 381 AO_GPIO(GPIOAO_4, 4), 382 AO_GPIO(GPIOAO_5, 5), 383 AO_GPIO(GPIOAO_6, 6), 384 AO_GPIO(GPIOAO_7, 7), 385 AO_GPIO(GPIOAO_8, 8), 386 AO_GPIO(GPIOAO_9, 9), 387 AO_GPIO(GPIOAO_10, 10), 388 AO_GPIO(GPIOAO_11, 11), 389 AO_GPIO(GPIOAO_12, 12), 390 AO_GPIO(GPIOAO_13, 13), 391 }; 392 393 static const struct meson_pinctrl_group mesongxbb_periphs_groups[] = { 394 /* GPIOX */ 395 { "sdio_d0", REG8, 5, { GPIOX_0 }, 1 }, 396 { "sdio_d1", REG8, 4, { GPIOX_1 }, 1 }, 397 { "sdio_d2", REG8, 3, { GPIOX_2 }, 1 }, 398 { "sdio_d3", REG8, 2, { GPIOX_3 }, 1 }, 399 { "sdio_cmd", REG8, 1, { GPIOX_4 }, 1 }, 400 { "sdio_clk", REG8, 0, { GPIOX_5 }, 1 }, 401 { "sdio_irq", REG8, 11, { GPIOX_7 }, 1 }, 402 { "uart_tx_a", REG4, 13, { GPIOX_12 }, 1 }, 403 { "uart_rx_a", REG4, 12, { GPIOX_13 }, 1 }, 404 { "uart_cts_a", REG4, 11, { GPIOX_14 }, 1 }, 405 { "uart_rts_a", REG4, 10, { GPIOX_15 }, 1 }, 406 { "pwm_a_x", REG3, 17, { GPIOX_6 }, 1 }, 407 { "pwm_e", REG2, 30, { GPIOX_19 }, 1 }, 408 { "pwm_f_x", REG3, 18, { GPIOX_7 }, 1 }, 409 410 /* GPIOY */ 411 { "uart_cts_c", REG1, 19, { GPIOY_11 }, 1 }, 412 { "uart_rts_c", REG1, 18, { GPIOY_12 }, 1 }, 413 { "uart_tx_c", REG1, 17, { GPIOY_13 }, 1 }, 414 { "uart_rx_c", REG1, 16, { GPIOY_14 }, 1 }, 415 { "pwm_a_y", REG1, 21, { GPIOY_16 }, 1 }, 416 { "pwm_f_y", REG1, 20, { GPIOY_15 }, 1 }, 417 { "i2s_out_ch23_y", REG1, 5, { GPIOY_8 }, 1 }, 418 { "i2s_out_ch45_y", REG1, 6, { GPIOY_9 }, 1 }, 419 { "i2s_out_ch67_y", REG1, 7, { GPIOY_10 }, 1 }, 420 { "spdif_out_y", REG1, 9, { GPIOY_12 }, 1 }, 421 { "gen_clk_out", REG6, 15, { GPIOY_15 }, 1 }, 422 423 /* GPIOZ */ 424 { "eth_mdio", REG6, 1, { GPIOZ_0 }, 1 }, 425 { "eth_mdc", REG6, 0, { GPIOZ_1 }, 1 }, 426 { "eth_clk_rx_clk", REG6, 13, { GPIOZ_2 }, 1 }, 427 { "eth_rx_dv", REG6, 12, { GPIOZ_3 }, 1 }, 428 { "eth_rxd0", REG6, 11, { GPIOZ_4 }, 1 }, 429 { "eth_rxd1", REG6, 10, { GPIOZ_5 }, 1 }, 430 { "eth_rxd2", REG6, 9, { GPIOZ_6 }, 1 }, 431 { "eth_rxd3", REG6, 8, { GPIOZ_7 }, 1 }, 432 { "eth_rgmii_tx_clk", REG6, 7, { GPIOZ_8 }, 1 }, 433 { "eth_tx_en", REG6, 6, { GPIOZ_9 }, 1 }, 434 { "eth_txd0", REG6, 5, { GPIOZ_10 }, 1 }, 435 { "eth_txd1", REG6, 4, { GPIOZ_11 }, 1 }, 436 { "eth_txd2", REG6, 3, { GPIOZ_12 }, 1 }, 437 { "eth_txd3", REG6, 2, { GPIOZ_13 }, 1 }, 438 { "spi_ss0", REG5, 26, { GPIOZ_7 }, 1 }, 439 { "spi_sclk", REG5, 27, { GPIOZ_6 }, 1 }, 440 { "spi_miso", REG5, 28, { GPIOZ_12 }, 1 }, 441 { "spi_mosi", REG5, 29, { GPIOZ_13 }, 1 }, 442 443 /* GPIOH */ 444 { "hdmi_hpd", REG1, 26, { GPIOH_0 }, 1 }, 445 { "hdmi_sda", REG1, 25, { GPIOH_1 }, 1 }, 446 { "hdmi_scl", REG1, 24, { GPIOH_2 }, 1 }, 447 448 /* GPIODV */ 449 { "uart_tx_b", REG2, 29, { GPIODV_24 }, 1 }, 450 { "uart_rx_b", REG2, 28, { GPIODV_25 }, 1 }, 451 { "uart_cts_b", REG2, 27, { GPIODV_26 }, 1 }, 452 { "uart_rts_b", REG2, 26, { GPIODV_27 }, 1 }, 453 { "pwm_b", REG3, 21, { GPIODV_29 }, 1 }, 454 { "pwm_d", REG3, 20, { GPIODV_28 }, 1 }, 455 { "i2c_sck_a", REG7, 27, { GPIODV_25 }, 1 }, 456 { "i2c_sda_a", REG7, 26, { GPIODV_24 }, 1 }, 457 { "i2c_sck_b", REG7, 25, { GPIODV_27 }, 1 }, 458 { "i2c_sda_b", REG7, 24, { GPIODV_26 }, 1 }, 459 { "i2c_sck_c", REG7, 23, { GPIODV_29 }, 1 }, 460 { "i2c_sda_c", REG7, 22, { GPIODV_28 }, 1 }, 461 462 /* BOOT */ 463 { "emmc_nand_d07", REG4, 30, { BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 }, 8 }, 464 { "emmc_clk", REG4, 18, { BOOT_8 }, 1 }, 465 { "emmc_cmd", REG4, 19, { BOOT_10 }, 1 }, 466 { "emmc_ds", REG4, 31, { BOOT_15 }, 1 }, 467 { "nor_d", REG5, 1, { BOOT_11 }, 1 }, 468 { "nor_q", REG5, 3, { BOOT_12 }, 1 }, 469 { "nor_c", REG5, 2, { BOOT_13 }, 1 }, 470 { "nor_cs", REG5, 0, { BOOT_15 }, 1 }, 471 { "nand_ce0", REG4, 26, { BOOT_8 }, 1 }, 472 { "nand_ce1", REG4, 27, { BOOT_9 }, 1 }, 473 { "nand_rb0", REG4, 25, { BOOT_10 }, 1 }, 474 { "nand_ale", REG4, 24, { BOOT_11 }, 1 }, 475 { "nand_cle", REG4, 23, { BOOT_12 }, 1 }, 476 { "nand_wen_clk", REG4, 22, { BOOT_13 }, 1 }, 477 { "nand_ren_wr", REG4, 21, { BOOT_14 }, 1 }, 478 { "nand_dqs", REG4, 20, { BOOT_15 }, 1 }, 479 480 /* CARD */ 481 { "sdcard_d1", REG2, 14, { CARD_0 }, 1 }, 482 { "sdcard_d0", REG2, 15, { CARD_1 }, 1 }, 483 { "sdcard_d3", REG2, 12, { CARD_4 }, 1 }, 484 { "sdcard_d2", REG2, 13, { CARD_5 }, 1 }, 485 { "sdcard_cmd", REG2, 10, { CARD_3 }, 1 }, 486 { "sdcard_clk", REG2, 11, { CARD_2 }, 1 }, 487 }; 488 489 static const struct meson_pinctrl_group mesongxbb_aobus_groups[] = { 490 /* GPIOAO */ 491 { "uart_tx_ao_b", AOREG0, 24, { GPIOAO_4 }, 1 }, 492 { "uart_rx_ao_b", AOREG0, 25, { GPIOAO_5 }, 1 }, 493 { "uart_tx_ao_a", AOREG0, 12, { GPIOAO_0 }, 1 }, 494 { "uart_rx_ao_a", AOREG0, 11, { GPIOAO_1 }, 1 }, 495 { "uart_cts_ao_a", AOREG0, 10, { GPIOAO_2 }, 1 }, 496 { "uart_rts_ao_a", AOREG0, 9, { GPIOAO_3 }, 1 }, 497 { "uart_cts_ao_b", AOREG0, 8, { GPIOAO_2 }, 1 }, 498 { "uart_rts_ao_b", AOREG0, 7, { GPIOAO_3 }, 1 }, 499 { "i2c_sck_ao", AOREG0, 6, { GPIOAO_4 }, 1 }, 500 { "i2c_sda_ao", AOREG0, 5, { GPIOAO_5 }, 1 }, 501 { "i2c_slave_sck_ao", AOREG0, 2, { GPIOAO_4 }, 1 }, 502 { "i2c_slave_sda_ao", AOREG0, 1, { GPIOAO_5 }, 1 }, 503 { "remote_input_ao", AOREG0, 0, { GPIOAO_7 }, 1 }, 504 { "pwm_ao_a_3", AOREG0, 22, { GPIOAO_3 }, 1 }, 505 { "pwm_ao_a_6", AOREG0, 18, { GPIOAO_6 }, 1 }, 506 { "pwm_ao_a_12", AOREG0, 17, { GPIOAO_12 }, 1 }, 507 { "pwm_ao_b", AOREG0, 3, { GPIOAO_13 }, 1 }, 508 { "i2s_am_clk", AOREG0, 30, { GPIOAO_8 }, 1 }, 509 { "i2s_out_ao_clk", AOREG0, 29, { GPIOAO_9 }, 1 }, 510 { "i2s_out_lr_clk", AOREG0, 28, { GPIOAO_10 }, 1 }, 511 { "i2s_out_ch01_ao", AOREG0, 27, { GPIOAO_11 }, 1 }, 512 { "i2s_out_ch23_ao", AOREG1, 0, { GPIOAO_12 }, 1 }, 513 { "i2s_out_ch45_ao", AOREG1, 1, { GPIOAO_13 }, 1 }, 514 { "spdif_out_ao_6", AOREG0, 16, { GPIOAO_6 }, 1 }, 515 { "spdif_out_ao_13", AOREG0, 4, { GPIOAO_13 }, 1 }, 516 { "ao_cec", AOREG0, 15, { GPIOAO_12 }, 1 }, 517 { "ee_cec", AOREG0, 14, { GPIOAO_12 }, 1 }, 518 519 /* TEST_N */ 520 { "i2s_out_ch67_ao", AOREG1, 2, { GPIO_TEST_N }, 1 }, 521 522 }; 523 524 const struct meson_pinctrl_config mesongxbb_periphs_pinctrl_config = { 525 .name = "Meson GXBB periphs GPIO", 526 .groups = mesongxbb_periphs_groups, 527 .ngroups = __arraycount(mesongxbb_periphs_groups), 528 .gpios = mesongxbb_periphs_gpios, 529 .ngpios = __arraycount(mesongxbb_periphs_gpios), 530 }; 531 532 const struct meson_pinctrl_config mesongxbb_aobus_pinctrl_config = { 533 .name = "Meson GXBB AO GPIO", 534 .groups = mesongxbb_aobus_groups, 535 .ngroups = __arraycount(mesongxbb_aobus_groups), 536 .gpios = mesongxbb_aobus_gpios, 537 .ngpios = __arraycount(mesongxbb_aobus_gpios), 538 }; 539
Indexes created Mon Oct 20 11:09:49 GMT 2025