apple_intc.c revision 1.3
1 /* $NetBSD: apple_intc.c,v 1.3 2021/10/16 06:37:43 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2021 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 #include "opt_multiprocessor.h" 31 32 #define _INTR_PRIVATE 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: apple_intc.c,v 1.3 2021/10/16 06:37:43 ryo Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/device.h> 40 #include <sys/intr.h> 41 #include <sys/kernel.h> 42 #include <sys/lwp.h> 43 #include <sys/systm.h> 44 #include <sys/cpu.h> 45 #include <sys/kmem.h> 46 #include <sys/atomic.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <arm/cpu.h> 54 #include <arm/cpufunc.h> 55 #include <arm/armreg.h> 56 #include <arm/locore.h> 57 #include <arm/pic/picvar.h> 58 #include <arm/fdt/arm_fdtvar.h> 59 60 /* 61 * AIC registers 62 */ 63 #define AIC_INFO 0x0004 64 #define AIC_INFO_NIRQ __BITS(15,0) 65 #define AIC_WHOAMI 0x2000 66 #define AIC_EVENT 0x2004 67 #define AIC_EVENT_TYPE __BITS(31,16) 68 #define AIC_EVENT_TYPE_NONE 0 69 #define AIC_EVENT_TYPE_IRQ 1 70 #define AIC_EVENT_TYPE_IPI 4 71 #define AIC_EVENT_DATA __BITS(15,0) 72 #define AIC_EVENT_IPI_OTHER 1 73 #define AIC_IPI_SEND 0x2008 74 #define AIC_IPI_ACK 0x200c 75 #define AIC_IPI_MASK_CLR 0x2028 76 #define AIC_IPI_OTHER __BIT(0) 77 #define AIC_AFFINITY(irqno) (0x3000 + (irqno) * 4) 78 #define AIC_SW_SET(irqno) (0x4000 + (irqno) / 32 * 4) 79 #define AIC_SW_CLR(irqno) (0x4080 + (irqno) / 32 * 4) 80 #define AIC_MASK_SET(irqno) (0x4100 + (irqno) / 32 * 4) 81 #define AIC_MASK_CLR(irqno) (0x4180 + (irqno) / 32 * 4) 82 #define AIC_MASK_BIT(irqno) __BIT((irqno) & 0x1f) 83 84 static const struct device_compatible_entry compat_data[] = { 85 { .compat = "apple,aic" }, 86 DEVICE_COMPAT_EOL 87 }; 88 89 struct apple_intc_softc; 90 91 struct apple_intc_percpu { 92 struct apple_intc_softc *pc_sc; 93 u_int pc_cpuid; 94 u_int pc_ipimask; 95 96 struct pic_softc pc_pic; 97 }; 98 99 #define LOCALPIC_SOURCE_TIMER 0 100 #define LOCALPIC_SOURCE_IPI 1 101 102 struct apple_intc_softc { 103 device_t sc_dev; /* device handle */ 104 bus_space_tag_t sc_bst; /* mmio tag */ 105 bus_space_handle_t sc_bsh; /* mmio handle */ 106 u_int sc_nirq; /* number of supported IRQs */ 107 u_int *sc_cpuid; /* map of cpu index to AIC CPU ID */ 108 struct apple_intc_percpu *sc_pc; /* per-CPU data for timer and IPIs */ 109 110 struct pic_softc sc_pic; 111 }; 112 113 static struct apple_intc_softc *intc_softc; 114 115 #define PICTOSOFTC(pic) \ 116 ((void *)((uintptr_t)(pic) - offsetof(struct apple_intc_softc, sc_pic))) 117 #define PICTOPERCPU(pic) \ 118 ((void *)((uintptr_t)(pic) - offsetof(struct apple_intc_percpu, pc_pic))) 119 120 #define AIC_READ(sc, reg) \ 121 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 122 #define AIC_WRITE(sc, reg, val) \ 123 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 124 125 static void 126 apple_intc_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 127 { 128 struct apple_intc_softc * const sc = PICTOSOFTC(pic); 129 130 AIC_WRITE(sc, AIC_SW_SET(irqbase), mask); 131 AIC_WRITE(sc, AIC_MASK_CLR(irqbase), mask); 132 } 133 134 static void 135 apple_intc_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 136 { 137 } 138 139 static void 140 apple_intc_establish_irq(struct pic_softc *pic, struct intrsource *is) 141 { 142 struct apple_intc_softc * const sc = PICTOSOFTC(pic); 143 144 KASSERT(is->is_type == IST_LEVEL); 145 146 /* Route to primary PE by default */ 147 AIC_WRITE(sc, AIC_AFFINITY(is->is_irq), __BIT(0)); 148 AIC_WRITE(sc, AIC_MASK_CLR(is->is_irq), 149 AIC_MASK_BIT(is->is_irq)); 150 } 151 152 static void 153 apple_intc_set_priority(struct pic_softc *pic, int ipl) 154 { 155 } 156 157 static void 158 apple_intc_cpu_init(struct pic_softc *pic, struct cpu_info *ci) 159 { 160 struct apple_intc_softc * const sc = PICTOSOFTC(pic); 161 const u_int cpuno = cpu_index(ci); 162 163 sc->sc_cpuid[cpuno] = AIC_READ(sc, AIC_WHOAMI); 164 } 165 166 static const struct pic_ops apple_intc_picops = { 167 .pic_unblock_irqs = apple_intc_unblock_irqs, 168 .pic_block_irqs = apple_intc_block_irqs, 169 .pic_establish_irq = apple_intc_establish_irq, 170 .pic_set_priority = apple_intc_set_priority, 171 #ifdef MULTIPROCESSOR 172 .pic_cpu_init = apple_intc_cpu_init, 173 #endif 174 }; 175 176 static void 177 apple_intc_local_unblock_irqs(struct pic_softc *pic, size_t irqbase, 178 uint32_t mask) 179 { 180 KASSERT(irqbase == 0); 181 182 if ((mask & __BIT(LOCALPIC_SOURCE_TIMER)) != 0) { 183 gtmr_cntv_ctl_write(gtmr_cntv_ctl_read() & ~CNTCTL_IMASK); 184 isb(); 185 } 186 } 187 188 static void 189 apple_intc_local_block_irqs(struct pic_softc *pic, size_t irqbase, 190 uint32_t mask) 191 { 192 KASSERT(irqbase == 0); 193 194 if ((mask & __BIT(LOCALPIC_SOURCE_TIMER)) != 0) { 195 gtmr_cntv_ctl_write(gtmr_cntv_ctl_read() | CNTCTL_IMASK); 196 isb(); 197 } 198 } 199 200 static void 201 apple_intc_local_establish_irq(struct pic_softc *pic, struct intrsource *is) 202 { 203 } 204 205 #ifdef MULTIPROCESSOR 206 static void 207 apple_intc_local_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi) 208 { 209 struct apple_intc_percpu * const pc = PICTOPERCPU(pic); 210 struct apple_intc_softc * const sc = pc->pc_sc; 211 const u_int target = sc->sc_cpuid[pc->pc_cpuid]; 212 213 atomic_or_32(&pc->pc_ipimask, __BIT(ipi)); 214 AIC_WRITE(sc, AIC_IPI_SEND, __BIT(target)); 215 } 216 #endif /* MULTIPROCESSOR */ 217 218 static const struct pic_ops apple_intc_localpicops = { 219 .pic_unblock_irqs = apple_intc_local_unblock_irqs, 220 .pic_block_irqs = apple_intc_local_block_irqs, 221 .pic_establish_irq = apple_intc_local_establish_irq, 222 #ifdef MULTIPROCESSOR 223 .pic_ipi_send = apple_intc_local_ipi_send, 224 #endif 225 }; 226 227 static void * 228 apple_intc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 229 int (*func)(void *), void *arg, const char *xname) 230 { 231 struct apple_intc_softc * const sc = device_private(dev); 232 struct apple_intc_percpu * const pc = &sc->sc_pc[cpu_index(curcpu())]; 233 234 /* 1st cell is the interrupt type (0=IRQ, 1=FIQ) */ 235 const u_int type = be32toh(specifier[0]); 236 /* 2nd cell is the interrupt number */ 237 const u_int intno = be32toh(specifier[1]); 238 /* 3rd cell is the interrupt flags */ 239 240 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 241 const int irq = type == 0 ? 242 intno : pc->pc_pic.pic_irqbase + LOCALPIC_SOURCE_TIMER; 243 return intr_establish_xname(irq, ipl, IST_LEVEL | mpsafe, func, arg, 244 xname); 245 } 246 247 static void 248 apple_intc_fdt_disestablish(device_t dev, void *ih) 249 { 250 intr_disestablish(ih); 251 } 252 253 static bool 254 apple_intc_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 255 { 256 if (!specifier) 257 return false; 258 259 /* 1st cell is the interrupt type (0=IRQ, 1=FIQ) */ 260 const u_int type = be32toh(specifier[0]); 261 /* 2nd cell is the interrupt number */ 262 const u_int intno = be32toh(specifier[1]); 263 264 snprintf(buf, buflen, "%s %u", type == 0 ? "IRQ" : "FIQ", intno); 265 266 return true; 267 } 268 269 static const struct fdtbus_interrupt_controller_func apple_intc_fdt_funcs = { 270 .establish = apple_intc_fdt_establish, 271 .disestablish = apple_intc_fdt_disestablish, 272 .intrstr = apple_intc_fdt_intrstr, 273 }; 274 275 static void 276 apple_intc_mark_pending(struct pic_softc *pic, u_int intno) 277 { 278 const int group = intno / 32; 279 const uint32_t pending = __BIT(intno & 0x1f); 280 pic_mark_pending_sources(pic, group * 32, pending); 281 } 282 283 static void 284 apple_intc_irq_handler(void *frame) 285 { 286 struct cpu_info * const ci = curcpu(); 287 struct apple_intc_softc * const sc = intc_softc; 288 struct pic_softc *pic; 289 struct intrsource *is; 290 const int oldipl = ci->ci_cpl; 291 uint16_t evtype, evdata; 292 bus_size_t clr_reg; 293 uint32_t clr_val; 294 295 ci->ci_data.cpu_nintr++; 296 297 for (;;) { 298 const uint32_t ev = AIC_READ(sc, AIC_EVENT); 299 evtype = __SHIFTOUT(ev, AIC_EVENT_TYPE); 300 evdata = __SHIFTOUT(ev, AIC_EVENT_DATA); 301 302 dsb(sy); 303 isb(); 304 305 if (evtype == AIC_EVENT_TYPE_IRQ) { 306 KASSERT(evdata < sc->sc_nirq); 307 pic = &sc->sc_pic; 308 is = pic->pic_sources[evdata]; 309 KASSERT(is != NULL); 310 311 AIC_WRITE(sc, AIC_SW_CLR(evdata), 312 __BIT(evdata & 0x1f)); 313 314 clr_reg = AIC_MASK_CLR(evdata); 315 clr_val = AIC_MASK_BIT(evdata); 316 } else if (evtype == AIC_EVENT_TYPE_IPI) { 317 KASSERT(evdata == AIC_EVENT_IPI_OTHER); 318 pic = &sc->sc_pc[cpu_index(ci)].pc_pic; 319 is = pic->pic_sources[LOCALPIC_SOURCE_IPI]; 320 KASSERT(is != NULL); 321 322 AIC_WRITE(sc, AIC_IPI_ACK, AIC_IPI_OTHER); 323 324 clr_reg = 0; 325 clr_val = 0; 326 } else { 327 break; 328 } 329 330 if (ci->ci_cpl >= is->is_ipl) { 331 apple_intc_mark_pending(pic, is->is_irq); 332 } else { 333 pic_set_priority(ci, is->is_ipl); 334 ENABLE_INTERRUPT(); 335 pic_dispatch(is, frame); 336 DISABLE_INTERRUPT(); 337 338 if (clr_val != 0) { 339 AIC_WRITE(sc, clr_reg, clr_val); 340 } 341 } 342 } 343 344 if (oldipl != IPL_HIGH) { 345 pic_do_pending_ints(DAIF_I|DAIF_F, oldipl, frame); 346 } 347 } 348 349 static void 350 apple_intc_fiq_handler(void *frame) 351 { 352 struct cpu_info * const ci = curcpu(); 353 struct apple_intc_softc * const sc = intc_softc; 354 struct pic_softc * const pic = &sc->sc_pc[cpu_index(ci)].pc_pic; 355 const int oldipl = ci->ci_cpl; 356 357 ci->ci_data.cpu_nintr++; 358 359 struct intrsource * const is = pic->pic_sources[LOCALPIC_SOURCE_TIMER]; 360 361 dsb(sy); 362 isb(); 363 364 if (oldipl >= is->is_ipl) { 365 apple_intc_mark_pending(pic, LOCALPIC_SOURCE_TIMER); 366 } else { 367 pic_set_priority(ci, is->is_ipl); 368 pic_dispatch(is, frame); 369 } 370 371 if (oldipl != IPL_HIGH) { 372 pic_do_pending_ints(DAIF_I|DAIF_F, oldipl, frame); 373 } 374 } 375 376 #ifdef MULTIPROCESSOR 377 static int 378 apple_intc_ipi_handler(void *priv) 379 { 380 struct apple_intc_percpu * const pc = priv; 381 struct apple_intc_softc * const sc = pc->pc_sc; 382 uint32_t ipimask, bit; 383 384 AIC_WRITE(sc, AIC_IPI_MASK_CLR, AIC_IPI_OTHER); 385 ipimask = atomic_swap_32(&pc->pc_ipimask, 0); 386 387 while ((bit = ffs(ipimask)) > 0) { 388 const u_int ipi = bit - 1; 389 390 switch (ipi) { 391 case IPI_AST: 392 pic_ipi_ast(priv); 393 break; 394 case IPI_NOP: 395 pic_ipi_nop(priv); 396 break; 397 #ifdef __HAVE_PREEMPTION 398 case IPI_KPREEMPT: 399 pic_ipi_kpreempt(priv); 400 break; 401 #endif 402 case IPI_XCALL: 403 pic_ipi_xcall(priv); 404 break; 405 case IPI_GENERIC: 406 pic_ipi_generic(priv); 407 break; 408 case IPI_SHOOTDOWN: 409 pic_ipi_shootdown(priv); 410 break; 411 #ifdef DDB 412 case IPI_DDB: 413 pic_ipi_ddb(priv); 414 break; 415 #endif 416 } 417 ipimask &= ~__BIT(ipi); 418 } 419 420 return 1; 421 } 422 #endif /* MULTIPROCESSOR */ 423 424 static void 425 apple_intc_percpu_init(void *priv, struct cpu_info *ci) 426 { 427 struct apple_intc_softc * const sc = priv; 428 const u_int cpuno = cpu_index(ci); 429 struct apple_intc_percpu * const pc = &sc->sc_pc[cpuno]; 430 struct pic_softc * const pic = &pc->pc_pic; 431 432 #ifdef MULTIPROCESSOR 433 pic->pic_cpus = ci->ci_kcpuset; 434 #endif 435 436 pic_add(pic, PIC_IRQBASE_ALLOC); 437 438 #ifdef MULTIPROCESSOR 439 if (cpuno != 0) { 440 struct intrsource * const is = 441 sc->sc_pc[0].pc_pic.pic_sources[LOCALPIC_SOURCE_TIMER]; 442 KASSERT(is != NULL); 443 444 intr_establish_xname(pic->pic_irqbase + LOCALPIC_SOURCE_TIMER, 445 is->is_ipl, is->is_type | (is->is_mpsafe ? IST_MPSAFE : 0), 446 is->is_func, is->is_arg, is->is_xname); 447 } 448 449 intr_establish_xname(pic->pic_irqbase + LOCALPIC_SOURCE_IPI, IPL_HIGH, 450 IST_LEVEL | IST_MPSAFE, apple_intc_ipi_handler, pc, "ipi"); 451 #endif 452 } 453 454 static int 455 apple_intc_match(device_t parent, cfdata_t cf, void *aux) 456 { 457 struct fdt_attach_args * const faa = aux; 458 459 return of_compatible_match(faa->faa_phandle, compat_data); 460 } 461 462 static void 463 apple_intc_attach(device_t parent, device_t self, void *aux) 464 { 465 struct apple_intc_softc * const sc = device_private(self); 466 struct fdt_attach_args * const faa = aux; 467 const int phandle = faa->faa_phandle; 468 bus_addr_t addr; 469 bus_size_t size; 470 u_int cpuno; 471 int error; 472 473 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 474 aprint_error(": couldn't get registers\n"); 475 return; 476 } 477 478 sc->sc_dev = self; 479 sc->sc_bst = faa->faa_bst; 480 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 481 aprint_error(": couldn't map registers\n"); 482 return; 483 } 484 485 sc->sc_nirq = AIC_READ(sc, AIC_INFO) & AIC_INFO_NIRQ; 486 487 aprint_naive("\n"); 488 aprint_normal(": Apple AIC (%u IRQs, 1 FIQ)\n", sc->sc_nirq); 489 KASSERT(sc->sc_nirq % 32 == 0); 490 491 sc->sc_pic.pic_ops = &apple_intc_picops; 492 sc->sc_pic.pic_maxsources = sc->sc_nirq; 493 snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "AIC"); 494 pic_add(&sc->sc_pic, 0); 495 496 error = fdtbus_register_interrupt_controller(self, phandle, 497 &apple_intc_fdt_funcs); 498 if (error) { 499 aprint_error_dev(self, "couldn't register with fdtbus: %d\n", 500 error); 501 return; 502 } 503 504 KASSERT(intc_softc == NULL); 505 intc_softc = sc; 506 arm_fdt_irq_set_handler(apple_intc_irq_handler); 507 arm_fdt_fiq_set_handler(apple_intc_fiq_handler); 508 509 KASSERT(ncpu != 0); 510 sc->sc_cpuid = kmem_zalloc(sizeof(*sc->sc_cpuid) * ncpu, KM_SLEEP); 511 sc->sc_pc = kmem_zalloc(sizeof(*sc->sc_pc) * ncpu, KM_SLEEP); 512 for (cpuno = 0; cpuno < ncpu; cpuno++) { 513 sc->sc_pc[cpuno].pc_sc = sc; 514 sc->sc_pc[cpuno].pc_cpuid = cpuno; 515 sc->sc_pc[cpuno].pc_pic.pic_ops = &apple_intc_localpicops; 516 sc->sc_pc[cpuno].pc_pic.pic_maxsources = 2; 517 snprintf(sc->sc_pc[cpuno].pc_pic.pic_name, 518 sizeof(sc->sc_pc[cpuno].pc_pic.pic_name), "AIC/%u", cpuno); 519 } 520 521 apple_intc_cpu_init(&sc->sc_pic, curcpu()); 522 apple_intc_percpu_init(sc, curcpu()); 523 arm_fdt_cpu_hatch_register(sc, apple_intc_percpu_init); 524 } 525 526 CFATTACH_DECL_NEW(apple_intc, sizeof(struct apple_intc_softc), 527 apple_intc_match, apple_intc_attach, NULL, NULL); 528
Indexes created Thu Oct 02 01:09:59 GMT 2025