apple_pcie.c revision 1.6 1 1.6 skrll /* $NetBSD: apple_pcie.c,v 1.6 2022/04/27 08:03:06 skrll Exp $ */
2 1.6 skrll /* $OpenBSD: aplpcie.c,v 1.13 2022/04/06 18:59:26 naddy Exp $ */
3 1.1 jmcneill
4 1.1 jmcneill /*-
5 1.1 jmcneill * Copyright (c) 2021 Jared McNeill <jmcneill (at) invisible.ca>
6 1.1 jmcneill * All rights reserved.
7 1.1 jmcneill *
8 1.1 jmcneill * Redistribution and use in source and binary forms, with or without
9 1.1 jmcneill * modification, are permitted provided that the following conditions
10 1.1 jmcneill * are met:
11 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright
12 1.1 jmcneill * notice, this list of conditions and the following disclaimer.
13 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the
15 1.1 jmcneill * documentation and/or other materials provided with the distribution.
16 1.1 jmcneill *
17 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 1.1 jmcneill * SUCH DAMAGE.
28 1.1 jmcneill */
29 1.1 jmcneill
30 1.6 skrll /*
31 1.6 skrll * Copyright (c) 2021 Mark Kettenis <kettenis (at) openbsd.org>
32 1.6 skrll *
33 1.6 skrll * Permission to use, copy, modify, and distribute this software for any
34 1.6 skrll * purpose with or without fee is hereby granted, provided that the above
35 1.6 skrll * copyright notice and this permission notice appear in all copies.
36 1.6 skrll *
37 1.6 skrll * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
38 1.6 skrll * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
39 1.6 skrll * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
40 1.6 skrll * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
41 1.6 skrll * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
42 1.6 skrll * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
43 1.6 skrll * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
44 1.6 skrll */
45 1.6 skrll
46 1.6 skrll
47 1.1 jmcneill #include <sys/cdefs.h>
48 1.6 skrll __KERNEL_RCSID(0, "$NetBSD: apple_pcie.c,v 1.6 2022/04/27 08:03:06 skrll Exp $");
49 1.1 jmcneill
50 1.1 jmcneill #include <sys/param.h>
51 1.1 jmcneill #include <sys/device.h>
52 1.1 jmcneill #include <sys/kernel.h>
53 1.1 jmcneill #include <sys/systm.h>
54 1.1 jmcneill #include <sys/bus.h>
55 1.1 jmcneill #include <sys/kmem.h>
56 1.1 jmcneill #include <sys/bitops.h>
57 1.1 jmcneill
58 1.1 jmcneill #include <dev/pci/pcireg.h>
59 1.1 jmcneill #include <dev/pci/pcivar.h>
60 1.1 jmcneill #include <dev/pci/pciconf.h>
61 1.1 jmcneill
62 1.1 jmcneill #include <dev/fdt/fdtvar.h>
63 1.1 jmcneill
64 1.1 jmcneill #include <arm/pci/pci_msi_machdep.h>
65 1.1 jmcneill #include <arm/fdt/pcihost_fdtvar.h>
66 1.1 jmcneill
67 1.6 skrll #define PCIE_CORE_LANE_CONF(port) (0x84000 + (port) * 0x4000)
68 1.6 skrll #define PCIE_CORE_LANE_CONF_REFCLK0REQ __BIT(0)
69 1.6 skrll #define PCIE_CORE_LANE_CONF_REFCLK1REQ __BIT(1)
70 1.6 skrll #define PCIE_CORE_LANE_CONF_REFCLK0ACK __BIT(2)
71 1.6 skrll #define PCIE_CORE_LANE_CONF_REFCLK1ACK __BIT(3)
72 1.6 skrll #define PCIE_CORE_LANE_CONF_REFCLK0EN __BIT(9)
73 1.6 skrll #define PCIE_CORE_LANE_CONF_REFCLK1EN __BIT(10)
74 1.6 skrll #define PCIE_CORE_LANE_CTRL(port) (0x84004 + (port) * 0x4000)
75 1.6 skrll #define PCIE_CORE_LANE_CTRL_CFGACC __BIT(15)
76 1.6 skrll
77 1.6 skrll #define PCIE_PORT_LTSSM_CTRL 0x0080
78 1.6 skrll #define PCIE_PORT_LTSSM_CTRL_START __BIT(0)
79 1.6 skrll #define PCIE_PORT_MSI_CTRL 0x0124
80 1.6 skrll #define PCIE_PORT_MSI_CTRL_EN __BIT(0)
81 1.6 skrll #define PCIE_PORT_MSI_CTRL_32 __SHIFTIN(5U, __BITS(7,4))
82 1.6 skrll #define PCIE_PORT_MSI_REMAP 0x0128
83 1.6 skrll #define PCIE_PORT_MSI_DOORBELL 0x0168
84 1.6 skrll #define PCIE_PORT_LINK_STAT 0x0208
85 1.6 skrll #define PCIE_PORT_LINK_STAT_UP __BIT(0)
86 1.6 skrll #define PCIE_PORT_APPCLK 0x0800
87 1.6 skrll #define PCIE_PORT_APPCLK_EN __BIT(0)
88 1.6 skrll #define PCIE_PORT_APPCLK_CGDIS __BIT(8)
89 1.6 skrll #define PCIE_PORT_STAT 0x0804
90 1.6 skrll #define PCIE_PORT_STAT_READY __BIT(0)
91 1.6 skrll #define PCIE_PORT_REFCLK 0x0810
92 1.6 skrll #define PCIE_PORT_REFCLK_EN __BIT(0)
93 1.6 skrll #define PCIE_PORT_REFCLK_CGDIS __BIT(8)
94 1.6 skrll #define PCIE_PORT_PERST 0x0814
95 1.6 skrll #define PCIE_PORT_PERST_DIS __BIT(0)
96 1.1 jmcneill
97 1.4 jmcneill extern struct bus_space arm_generic_bs_tag;
98 1.4 jmcneill
99 1.1 jmcneill struct apple_pcie_softc {
100 1.1 jmcneill struct pcihost_softc sc_pcihost;
101 1.1 jmcneill
102 1.6 skrll bus_space_tag_t sc_rc_bst;
103 1.6 skrll bus_space_handle_t sc_rc_bsh;
104 1.6 skrll
105 1.1 jmcneill int sc_phandle;
106 1.1 jmcneill struct arm_pci_msi sc_msi;
107 1.1 jmcneill u_int sc_msi_start;
108 1.1 jmcneill u_int sc_nmsi;
109 1.1 jmcneill struct pci_attach_args **sc_msi_pa;
110 1.1 jmcneill void **sc_msi_ih;
111 1.1 jmcneill uint64_t sc_msi_addr;
112 1.1 jmcneill };
113 1.1 jmcneill
114 1.1 jmcneill static int apple_pcie_match(device_t, cfdata_t, void *);
115 1.1 jmcneill static void apple_pcie_attach(device_t, device_t, void *);
116 1.1 jmcneill
117 1.1 jmcneill static void apple_pcie_attach_hook(device_t, device_t,
118 1.1 jmcneill struct pcibus_attach_args *);
119 1.1 jmcneill static int apple_pcie_msi_init(struct apple_pcie_softc *);
120 1.1 jmcneill
121 1.1 jmcneill CFATTACH_DECL_NEW(apple_pcie, sizeof(struct apple_pcie_softc),
122 1.1 jmcneill apple_pcie_match, apple_pcie_attach, NULL, NULL);
123 1.1 jmcneill
124 1.1 jmcneill static const struct device_compatible_entry compat_data[] = {
125 1.1 jmcneill { .compat = "apple,pcie" },
126 1.1 jmcneill DEVICE_COMPAT_EOL
127 1.1 jmcneill };
128 1.1 jmcneill
129 1.6 skrll #define RREAD4(sc, reg) \
130 1.6 skrll (bus_space_read_4((sc)->sc_rc_bst, (sc)->sc_rc_bsh, (reg)))
131 1.6 skrll #define RWRITE4(sc, reg, val) \
132 1.6 skrll bus_space_write_4((sc)->sc_rc_bst, (sc)->sc_rc_bsh, (reg), (val))
133 1.6 skrll #define RSET4(sc, reg, bits) \
134 1.6 skrll RWRITE4((sc), (reg), RREAD4((sc), (reg)) | (bits))
135 1.6 skrll #define RCLR4(sc, reg, bits) \
136 1.6 skrll RWRITE4((sc), (reg), RREAD4((sc), (reg)) & ~(bits))
137 1.6 skrll
138 1.6 skrll
139 1.6 skrll static void
140 1.6 skrll apple_pcie_setup_port(struct apple_pcie_softc *sc, int phandle)
141 1.6 skrll {
142 1.6 skrll const bus_space_tag_t bst = sc->sc_pcihost.sc_bst;
143 1.6 skrll const device_t dev = sc->sc_pcihost.sc_dev;
144 1.6 skrll const int parent = sc->sc_pcihost.sc_phandle;
145 1.6 skrll char regname[sizeof("portX")];
146 1.6 skrll bus_space_handle_t bsh;
147 1.6 skrll bus_addr_t addr;
148 1.6 skrll bus_size_t size;
149 1.6 skrll int error;
150 1.6 skrll int timo;
151 1.6 skrll int len;
152 1.6 skrll
153 1.6 skrll const u_int *reg = fdtbus_get_prop(phandle, "reg", &len);
154 1.6 skrll if (len != 5 * sizeof(uint32_t)) {
155 1.6 skrll aprint_error(": couldn't get port number\n");
156 1.6 skrll }
157 1.6 skrll
158 1.6 skrll u_int portno = __SHIFTOUT(be32toh(reg[0]), __BITS(13,11));
159 1.6 skrll snprintf(regname, sizeof(regname), "port%u", portno);
160 1.6 skrll
161 1.6 skrll if (fdtbus_get_reg_byname(parent, regname, &addr, &size) != 0) {
162 1.6 skrll aprint_error(": couldn't get %s regs\n", regname);
163 1.6 skrll return;
164 1.6 skrll }
165 1.6 skrll error = bus_space_map(bst, addr, size, 0, &bsh);
166 1.6 skrll if (error != 0) {
167 1.6 skrll aprint_error(": couldn't map %s regs\n", regname);
168 1.6 skrll return;
169 1.6 skrll }
170 1.6 skrll
171 1.6 skrll #define PREAD4(bst, bsh, reg) \
172 1.6 skrll bus_space_read_4((bst), (bsh), (reg))
173 1.6 skrll #define PWRITE4(bst, bsh, reg, val) \
174 1.6 skrll bus_space_write_4((bst), (bsh), (reg), (val))
175 1.6 skrll #define PSET4(bst, bsh, reg, bits) \
176 1.6 skrll PWRITE4((bst), (bsh), (reg), PREAD4((bst), (bsh), (reg)) | (bits))
177 1.6 skrll #define PCLR4(bst, bsh, reg, bits) \
178 1.6 skrll PWRITE4((bst), (bsh), (reg), PREAD4((bst), (bsh), (reg)) & ~(bits))
179 1.6 skrll
180 1.6 skrll /* Doorbell address must be below 4GB */
181 1.6 skrll KASSERT((sc->sc_msi_addr & ~0xffffffffUL) == 0);
182 1.6 skrll
183 1.6 skrll int pwren_gpiolen, reset_gpiolen;
184 1.6 skrll
185 1.6 skrll pwren_gpiolen = OF_getproplen(phandle, "pwren-gpios");
186 1.6 skrll reset_gpiolen = OF_getproplen(phandle, "reset-gpios");
187 1.6 skrll if (reset_gpiolen <= 0)
188 1.6 skrll return;
189 1.6 skrll
190 1.6 skrll /*
191 1.6 skrll * Set things up such that we can share the 32 available MSIs
192 1.6 skrll * across all ports.
193 1.6 skrll */
194 1.6 skrll PWRITE4(bst, bsh, PCIE_PORT_MSI_CTRL,
195 1.6 skrll PCIE_PORT_MSI_CTRL_32 | PCIE_PORT_MSI_CTRL_EN);
196 1.6 skrll PWRITE4(bst, bsh, PCIE_PORT_MSI_REMAP, 0);
197 1.6 skrll PWRITE4(bst, bsh, PCIE_PORT_MSI_DOORBELL,
198 1.6 skrll __SHIFTOUT(sc->sc_msi_addr, __BITS(31, 0)));
199 1.6 skrll
200 1.6 skrll /* Check if the link is already up. */
201 1.6 skrll uint32_t stat = PREAD4(bst, bsh, PCIE_PORT_LINK_STAT);
202 1.6 skrll if (stat & PCIE_PORT_LINK_STAT_UP) {
203 1.6 skrll aprint_debug_dev(dev, "link already up\n");
204 1.6 skrll return;
205 1.6 skrll }
206 1.6 skrll aprint_debug_dev(dev, "bringing link up\n");
207 1.6 skrll
208 1.6 skrll PSET4(bst, bsh, PCIE_PORT_APPCLK, PCIE_PORT_APPCLK_EN);
209 1.6 skrll
210 1.6 skrll struct fdtbus_gpio_pin *gpio_reset = fdtbus_gpio_acquire(phandle,
211 1.6 skrll "reset-gpios", GPIO_PIN_OUTPUT);
212 1.6 skrll
213 1.6 skrll if (gpio_reset == NULL) {
214 1.6 skrll aprint_debug_dev(dev, "failed to get reset-gpios\n");
215 1.6 skrll return;
216 1.6 skrll }
217 1.6 skrll
218 1.6 skrll fdtbus_gpio_write(gpio_reset, 1);
219 1.6 skrll
220 1.6 skrll /* Power up the device if necessary. */
221 1.6 skrll if (pwren_gpiolen > 0) {
222 1.6 skrll struct fdtbus_gpio_pin *gpio_pwren = fdtbus_gpio_acquire(phandle,
223 1.6 skrll "pwren-gpios", GPIO_PIN_OUTPUT);
224 1.6 skrll
225 1.6 skrll if (gpio_pwren == NULL) {
226 1.6 skrll aprint_debug_dev(dev, "failed to get pwren-gpios\n");
227 1.6 skrll return;
228 1.6 skrll }
229 1.6 skrll
230 1.6 skrll fdtbus_gpio_write(gpio_pwren, 1);
231 1.6 skrll }
232 1.6 skrll
233 1.6 skrll /* Setup Refclk. */
234 1.6 skrll RSET4(sc, PCIE_CORE_LANE_CTRL(portno), PCIE_CORE_LANE_CTRL_CFGACC);
235 1.6 skrll RSET4(sc, PCIE_CORE_LANE_CONF(portno), PCIE_CORE_LANE_CONF_REFCLK0REQ);
236 1.6 skrll for (timo = 500; timo > 0; timo--) {
237 1.6 skrll stat = RREAD4(sc, PCIE_CORE_LANE_CONF(portno));
238 1.6 skrll if (stat & PCIE_CORE_LANE_CONF_REFCLK0ACK)
239 1.6 skrll break;
240 1.6 skrll delay(100);
241 1.6 skrll }
242 1.6 skrll RSET4(sc, PCIE_CORE_LANE_CONF(portno), PCIE_CORE_LANE_CONF_REFCLK1REQ);
243 1.6 skrll for (timo = 500; timo > 0; timo--) {
244 1.6 skrll stat = RREAD4(sc, PCIE_CORE_LANE_CONF(portno));
245 1.6 skrll if (stat & PCIE_CORE_LANE_CONF_REFCLK1ACK)
246 1.6 skrll break;
247 1.6 skrll delay(100);
248 1.6 skrll }
249 1.6 skrll RCLR4(sc, PCIE_CORE_LANE_CTRL(portno), PCIE_CORE_LANE_CTRL_CFGACC);
250 1.6 skrll RSET4(sc, PCIE_CORE_LANE_CONF(portno),
251 1.6 skrll PCIE_CORE_LANE_CONF_REFCLK0EN | PCIE_CORE_LANE_CONF_REFCLK1EN);
252 1.6 skrll PSET4(bst, bsh, PCIE_PORT_REFCLK, PCIE_PORT_REFCLK_EN);
253 1.6 skrll
254 1.6 skrll /*
255 1.6 skrll * PERST# must remain asserted for at least 100us after the
256 1.6 skrll * reference clock becomes stable. But also has to remain
257 1.6 skrll * active at least 100ms after power up.
258 1.6 skrll */
259 1.6 skrll if (pwren_gpiolen > 0)
260 1.6 skrll delay(100000);
261 1.6 skrll else
262 1.6 skrll delay(100);
263 1.6 skrll
264 1.6 skrll /* Deassert PERST#. */
265 1.6 skrll PSET4(bst, bsh, PCIE_PORT_PERST, PCIE_PORT_PERST_DIS);
266 1.6 skrll fdtbus_gpio_write(gpio_reset, 0);
267 1.6 skrll
268 1.6 skrll for (timo = 2500; timo > 0; timo--) {
269 1.6 skrll stat = PREAD4(bst, bsh, PCIE_PORT_STAT);
270 1.6 skrll if (stat & PCIE_PORT_STAT_READY)
271 1.6 skrll break;
272 1.6 skrll delay(100);
273 1.6 skrll }
274 1.6 skrll if ((stat & PCIE_PORT_STAT_READY) == 0) {
275 1.6 skrll aprint_debug_dev(dev, "link up\n");
276 1.6 skrll return;
277 1.6 skrll }
278 1.6 skrll
279 1.6 skrll PCLR4(bst, bsh, PCIE_PORT_REFCLK, PCIE_PORT_REFCLK_CGDIS);
280 1.6 skrll PCLR4(bst, bsh, PCIE_PORT_APPCLK, PCIE_PORT_APPCLK_CGDIS);
281 1.6 skrll
282 1.6 skrll /* Bring up the link. */
283 1.6 skrll PWRITE4(bst, bsh, PCIE_PORT_LTSSM_CTRL, PCIE_PORT_LTSSM_CTRL_START);
284 1.6 skrll for (timo = 1000; timo > 0; timo--) {
285 1.6 skrll stat = PREAD4(bst, bsh, PCIE_PORT_LINK_STAT);
286 1.6 skrll if (stat & PCIE_PORT_LINK_STAT_UP)
287 1.6 skrll break;
288 1.6 skrll delay(100);
289 1.6 skrll }
290 1.6 skrll
291 1.6 skrll #undef PREAD4
292 1.6 skrll #undef PWRITE4
293 1.6 skrll #undef PCLR4
294 1.6 skrll #undef PSET4
295 1.6 skrll
296 1.6 skrll bus_space_unmap(bst, bsh, size);
297 1.6 skrll }
298 1.6 skrll
299 1.1 jmcneill static int
300 1.1 jmcneill apple_pcie_match(device_t parent, cfdata_t cf, void *aux)
301 1.1 jmcneill {
302 1.1 jmcneill struct fdt_attach_args * const faa = aux;
303 1.1 jmcneill
304 1.1 jmcneill return of_compatible_match(faa->faa_phandle, compat_data);
305 1.1 jmcneill }
306 1.1 jmcneill
307 1.1 jmcneill static void
308 1.1 jmcneill apple_pcie_attach(device_t parent, device_t self, void *aux)
309 1.1 jmcneill {
310 1.1 jmcneill struct apple_pcie_softc * const asc = device_private(self);
311 1.1 jmcneill struct pcihost_softc * const sc = &asc->sc_pcihost;
312 1.1 jmcneill struct fdt_attach_args * const faa = aux;
313 1.1 jmcneill const int phandle = faa->faa_phandle;
314 1.6 skrll bus_addr_t cs_addr, rc_addr;
315 1.6 skrll bus_size_t cs_size, rc_size;
316 1.1 jmcneill int error;
317 1.1 jmcneill
318 1.6 skrll if (fdtbus_get_reg_byname(phandle, "config", &cs_addr, &cs_size) != 0) {
319 1.6 skrll aprint_error(": couldn't get registers (%s)\n", "config");
320 1.6 skrll return;
321 1.6 skrll }
322 1.6 skrll
323 1.6 skrll if (fdtbus_get_reg_byname(phandle, "rc", &rc_addr, &rc_size) != 0) {
324 1.6 skrll aprint_error(": couldn't get registers (%s)\n", "rc");
325 1.1 jmcneill return;
326 1.1 jmcneill }
327 1.1 jmcneill
328 1.1 jmcneill sc->sc_dev = self;
329 1.1 jmcneill sc->sc_dmat = faa->faa_dmat;
330 1.6 skrll sc->sc_bst = asc->sc_rc_bst = faa->faa_bst;
331 1.3 jmcneill /*
332 1.3 jmcneill * Create a new bus tag for PCIe devices that does not inherit the
333 1.3 jmcneill * nonposted MMIO flag from the host controller.
334 1.3 jmcneill */
335 1.4 jmcneill sc->sc_pci_bst = &arm_generic_bs_tag;
336 1.1 jmcneill sc->sc_phandle = phandle;
337 1.3 jmcneill error = bus_space_map(faa->faa_bst, cs_addr, cs_size, 0, &sc->sc_bsh);
338 1.1 jmcneill if (error) {
339 1.6 skrll aprint_error(": couldn't map registers (%s): %d\n", "config",
340 1.6 skrll error);
341 1.6 skrll return;
342 1.6 skrll }
343 1.6 skrll error = bus_space_map(asc->sc_rc_bst, rc_addr, rc_size, 0,
344 1.6 skrll &asc->sc_rc_bsh);
345 1.6 skrll if (error) {
346 1.6 skrll aprint_error(": couldn't map registers (%s): %d\n", "rc",
347 1.6 skrll error);
348 1.1 jmcneill return;
349 1.1 jmcneill }
350 1.1 jmcneill sc->sc_type = PCIHOST_ECAM;
351 1.1 jmcneill
352 1.1 jmcneill if (apple_pcie_msi_init(asc) == 0) {
353 1.1 jmcneill sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY;
354 1.1 jmcneill #if notyet
355 1.1 jmcneill sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY;
356 1.1 jmcneill #endif
357 1.1 jmcneill }
358 1.1 jmcneill
359 1.1 jmcneill aprint_naive("\n");
360 1.1 jmcneill aprint_normal(": Apple PCIe host controller\n");
361 1.1 jmcneill
362 1.6 skrll for (int node = OF_child(phandle); node; node = OF_peer(node))
363 1.6 skrll apple_pcie_setup_port(asc, node);
364 1.6 skrll
365 1.6 skrll /*
366 1.6 skrll * Must wait at least 100ms after link training completes
367 1.6 skrll * before sending a configuration request to a device
368 1.6 skrll * immediately below a port.
369 1.6 skrll */
370 1.6 skrll delay(100000);
371 1.6 skrll
372 1.1 jmcneill pcihost_init(&sc->sc_pc, sc);
373 1.6 skrll
374 1.1 jmcneill sc->sc_pc.pc_attach_hook = apple_pcie_attach_hook;
375 1.1 jmcneill pcihost_init2(sc);
376 1.1 jmcneill }
377 1.1 jmcneill
378 1.1 jmcneill
379 1.1 jmcneill
380 1.1 jmcneill static void
381 1.1 jmcneill apple_pcie_attach_hook(device_t parent, device_t self,
382 1.1 jmcneill struct pcibus_attach_args *pba)
383 1.1 jmcneill {
384 1.1 jmcneill struct apple_pcie_softc *sc = pba->pba_pc->pc_conf_v;
385 1.1 jmcneill const int phandle = sc->sc_pcihost.sc_phandle;
386 1.2 jmcneill bus_dma_tag_t dmat;
387 1.1 jmcneill
388 1.1 jmcneill KASSERT(device_is_a(sc->sc_pcihost.sc_dev, "applepcie"));
389 1.1 jmcneill
390 1.2 jmcneill /* XXX this should be per-device, not per-bus */
391 1.2 jmcneill const uint32_t rid = pba->pba_bus << 8;
392 1.1 jmcneill
393 1.2 jmcneill dmat = fdtbus_iommu_map_pci(phandle, rid, sc->sc_pcihost.sc_dmat);
394 1.6 skrll
395 1.2 jmcneill pba->pba_dmat = pba->pba_dmat64 = dmat;
396 1.1 jmcneill }
397 1.1 jmcneill
398 1.1 jmcneill static int
399 1.1 jmcneill apple_pcie_msi_alloc_msi(struct apple_pcie_softc *sc, int count,
400 1.1 jmcneill const struct pci_attach_args *pa)
401 1.1 jmcneill {
402 1.1 jmcneill struct pci_attach_args *new_pa;
403 1.1 jmcneill int msi, n;
404 1.1 jmcneill
405 1.6 skrll for (msi = 0; msi < sc->sc_nmsi; msi += n) {
406 1.6 skrll /* Look for first empty slot */
407 1.6 skrll if (sc->sc_msi_pa[msi] != NULL) {
408 1.6 skrll /* skip the used entry */
409 1.6 skrll n = 1;
410 1.6 skrll continue;
411 1.6 skrll }
412 1.1 jmcneill
413 1.6 skrll /* Now check that 'count' entries are also empty */
414 1.6 skrll for (n = 1; n < count && msi + n < sc->sc_nmsi; n++) {
415 1.6 skrll if (sc->sc_msi_pa[msi + n] != NULL) {
416 1.6 skrll break;
417 1.1 jmcneill }
418 1.6 skrll }
419 1.6 skrll /*
420 1.6 skrll * If 'count' empty entries weren't found then the search
421 1.6 skrll * continues.
422 1.6 skrll */
423 1.6 skrll if (n != count)
424 1.6 skrll continue;
425 1.6 skrll for (n = 0; n < count; n++) {
426 1.6 skrll new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP);
427 1.6 skrll memcpy(new_pa, pa, sizeof(*new_pa));
428 1.6 skrll sc->sc_msi_pa[msi + n] = new_pa;
429 1.6 skrll }
430 1.1 jmcneill
431 1.6 skrll return msi;
432 1.1 jmcneill }
433 1.1 jmcneill
434 1.1 jmcneill return -1;
435 1.1 jmcneill }
436 1.1 jmcneill
437 1.1 jmcneill static void
438 1.1 jmcneill apple_pcie_msi_free_msi(struct apple_pcie_softc *sc, int msi)
439 1.1 jmcneill {
440 1.1 jmcneill struct pci_attach_args *pa;
441 1.1 jmcneill
442 1.1 jmcneill pa = sc->sc_msi_pa[msi];
443 1.1 jmcneill sc->sc_msi_pa[msi] = NULL;
444 1.1 jmcneill
445 1.1 jmcneill if (pa != NULL) {
446 1.1 jmcneill kmem_free(pa, sizeof(*pa));
447 1.1 jmcneill }
448 1.1 jmcneill }
449 1.1 jmcneill
450 1.1 jmcneill static int
451 1.1 jmcneill apple_pcie_msi_available_msi(struct apple_pcie_softc *sc)
452 1.1 jmcneill {
453 1.1 jmcneill int msi, n;
454 1.1 jmcneill
455 1.1 jmcneill for (n = 0, msi = 0; msi < sc->sc_nmsi; msi++) {
456 1.1 jmcneill if (sc->sc_msi_pa[msi] == NULL) {
457 1.1 jmcneill n++;
458 1.1 jmcneill }
459 1.1 jmcneill }
460 1.1 jmcneill
461 1.1 jmcneill return n;
462 1.1 jmcneill }
463 1.1 jmcneill
464 1.1 jmcneill static void
465 1.1 jmcneill apple_pcie_msi_msi_enable(struct apple_pcie_softc *sc, int msi, int count)
466 1.1 jmcneill {
467 1.1 jmcneill const struct pci_attach_args *pa = sc->sc_msi_pa[msi];
468 1.1 jmcneill pci_chipset_tag_t pc = pa->pa_pc;
469 1.1 jmcneill pcitag_t tag = pa->pa_tag;
470 1.1 jmcneill pcireg_t ctl;
471 1.1 jmcneill int off;
472 1.1 jmcneill
473 1.1 jmcneill if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL))
474 1.1 jmcneill panic("apple_pcie_msi_msi_enable: device is not MSI-capable");
475 1.1 jmcneill
476 1.1 jmcneill ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
477 1.1 jmcneill ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
478 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
479 1.1 jmcneill
480 1.1 jmcneill ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
481 1.1 jmcneill ctl &= ~PCI_MSI_CTL_MME_MASK;
482 1.1 jmcneill ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
483 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
484 1.1 jmcneill
485 1.1 jmcneill const uint64_t addr = sc->sc_msi_addr;
486 1.1 jmcneill const uint32_t data = msi;
487 1.1 jmcneill
488 1.1 jmcneill ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
489 1.1 jmcneill if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
490 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO,
491 1.6 skrll __SHIFTOUT(addr, __BITS(31, 0)));
492 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI,
493 1.6 skrll __SHIFTOUT(addr, __BITS(63, 32)));
494 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, data);
495 1.1 jmcneill } else {
496 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSI_MADDR,
497 1.6 skrll __SHIFTOUT(addr, __BITS(31, 0)));
498 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSI_MDATA, data);
499 1.1 jmcneill }
500 1.1 jmcneill ctl |= PCI_MSI_CTL_MSI_ENABLE;
501 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
502 1.1 jmcneill }
503 1.1 jmcneill
504 1.1 jmcneill static void
505 1.1 jmcneill apple_pcie_msi_msi_disable(struct apple_pcie_softc *sc, int msi)
506 1.1 jmcneill {
507 1.1 jmcneill const struct pci_attach_args *pa = sc->sc_msi_pa[msi];
508 1.1 jmcneill pci_chipset_tag_t pc = pa->pa_pc;
509 1.1 jmcneill pcitag_t tag = pa->pa_tag;
510 1.1 jmcneill pcireg_t ctl;
511 1.1 jmcneill int off;
512 1.1 jmcneill
513 1.1 jmcneill if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL))
514 1.1 jmcneill panic("apple_pcie_msi_msi_disable: device is not MSI-capable");
515 1.1 jmcneill
516 1.1 jmcneill ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
517 1.1 jmcneill ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
518 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
519 1.1 jmcneill }
520 1.1 jmcneill
521 1.1 jmcneill static void
522 1.1 jmcneill apple_pcie_msi_msix_enable(struct apple_pcie_softc *sc, int msi, int msix_vec,
523 1.1 jmcneill bus_space_tag_t bst, bus_space_handle_t bsh)
524 1.1 jmcneill {
525 1.1 jmcneill const struct pci_attach_args *pa = sc->sc_msi_pa[msi];
526 1.1 jmcneill pci_chipset_tag_t pc = pa->pa_pc;
527 1.1 jmcneill pcitag_t tag = pa->pa_tag;
528 1.1 jmcneill pcireg_t ctl;
529 1.1 jmcneill uint32_t val;
530 1.1 jmcneill int off;
531 1.1 jmcneill
532 1.1 jmcneill if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL))
533 1.1 jmcneill panic("apple_pcie_msi_msix_enable: device is not MSI-X-capable");
534 1.1 jmcneill
535 1.1 jmcneill ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
536 1.1 jmcneill ctl &= ~PCI_MSIX_CTL_ENABLE;
537 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
538 1.1 jmcneill
539 1.1 jmcneill const uint64_t addr = sc->sc_msi_addr;
540 1.1 jmcneill const uint32_t data = msi;
541 1.1 jmcneill const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
542 1.1 jmcneill bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO,
543 1.6 skrll __SHIFTOUT(addr, __BITS(31, 0)));
544 1.1 jmcneill bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI,
545 1.6 skrll __SHIFTOUT(addr, __BITS(63, 32)));
546 1.1 jmcneill bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA,
547 1.1 jmcneill data);
548 1.1 jmcneill val = bus_space_read_4(bst, bsh,
549 1.1 jmcneill entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL);
550 1.1 jmcneill val &= ~PCI_MSIX_VECTCTL_MASK;
551 1.1 jmcneill bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL,
552 1.1 jmcneill val);
553 1.1 jmcneill
554 1.1 jmcneill ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
555 1.1 jmcneill ctl |= PCI_MSIX_CTL_ENABLE;
556 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
557 1.1 jmcneill }
558 1.1 jmcneill
559 1.1 jmcneill static void
560 1.1 jmcneill apple_pcie_msi_msix_disable(struct apple_pcie_softc *sc, int msi)
561 1.1 jmcneill {
562 1.1 jmcneill const struct pci_attach_args *pa = sc->sc_msi_pa[msi];
563 1.1 jmcneill pci_chipset_tag_t pc = pa->pa_pc;
564 1.1 jmcneill pcitag_t tag = pa->pa_tag;
565 1.1 jmcneill pcireg_t ctl;
566 1.1 jmcneill int off;
567 1.1 jmcneill
568 1.1 jmcneill if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL))
569 1.1 jmcneill panic("apple_pcie_msi_msix_disable: device is not MSI-X-capable");
570 1.1 jmcneill
571 1.1 jmcneill ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
572 1.1 jmcneill ctl &= ~PCI_MSIX_CTL_ENABLE;
573 1.1 jmcneill pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
574 1.1 jmcneill }
575 1.1 jmcneill
576 1.1 jmcneill static pci_intr_handle_t *
577 1.1 jmcneill apple_pcie_msi_msi_alloc(struct arm_pci_msi *msi, int *count,
578 1.1 jmcneill const struct pci_attach_args *pa, bool exact)
579 1.1 jmcneill {
580 1.1 jmcneill struct apple_pcie_softc * const sc = msi->msi_priv;
581 1.1 jmcneill pci_intr_handle_t *vectors;
582 1.1 jmcneill int n, off;
583 1.1 jmcneill
584 1.1 jmcneill if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &off, NULL))
585 1.1 jmcneill return NULL;
586 1.1 jmcneill
587 1.1 jmcneill const int avail = apple_pcie_msi_available_msi(sc);
588 1.6 skrll if (avail == 0)
589 1.6 skrll return NULL;
590 1.6 skrll
591 1.1 jmcneill if (exact && *count > avail)
592 1.1 jmcneill return NULL;
593 1.1 jmcneill
594 1.1 jmcneill while (*count > avail) {
595 1.6 skrll (*count) >>= 1;
596 1.1 jmcneill }
597 1.1 jmcneill if (*count == 0)
598 1.1 jmcneill return NULL;
599 1.1 jmcneill
600 1.1 jmcneill const int msi_base = apple_pcie_msi_alloc_msi(sc, *count, pa);
601 1.1 jmcneill if (msi_base == -1)
602 1.1 jmcneill return NULL;
603 1.1 jmcneill
604 1.1 jmcneill vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
605 1.1 jmcneill for (n = 0; n < *count; n++) {
606 1.1 jmcneill const int msino = msi_base + n;
607 1.1 jmcneill vectors[n] = ARM_PCI_INTR_MSI |
608 1.1 jmcneill __SHIFTIN(msino, ARM_PCI_INTR_IRQ) |
609 1.1 jmcneill __SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |
610 1.1 jmcneill __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
611 1.1 jmcneill }
612 1.1 jmcneill
613 1.1 jmcneill apple_pcie_msi_msi_enable(sc, msi_base, *count);
614 1.1 jmcneill
615 1.1 jmcneill return vectors;
616 1.1 jmcneill }
617 1.1 jmcneill
618 1.1 jmcneill static pci_intr_handle_t *
619 1.1 jmcneill apple_pcie_msi_msix_alloc(struct arm_pci_msi *msi, u_int *table_indexes,
620 1.1 jmcneill int *count, const struct pci_attach_args *pa, bool exact)
621 1.1 jmcneill {
622 1.1 jmcneill struct apple_pcie_softc * const sc = msi->msi_priv;
623 1.1 jmcneill pci_intr_handle_t *vectors;
624 1.1 jmcneill bus_space_tag_t bst;
625 1.1 jmcneill bus_space_handle_t bsh;
626 1.1 jmcneill bus_size_t bsz;
627 1.1 jmcneill uint32_t table_offset, table_size;
628 1.1 jmcneill int n, off, bar, error;
629 1.1 jmcneill pcireg_t tbl;
630 1.1 jmcneill
631 1.1 jmcneill if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &off, NULL))
632 1.1 jmcneill return NULL;
633 1.1 jmcneill
634 1.1 jmcneill const int avail = apple_pcie_msi_available_msi(sc);
635 1.1 jmcneill if (exact && *count > avail)
636 1.1 jmcneill return NULL;
637 1.1 jmcneill
638 1.1 jmcneill while (*count > avail) {
639 1.6 skrll (*count) >>= 1;
640 1.1 jmcneill }
641 1.1 jmcneill if (*count == 0)
642 1.1 jmcneill return NULL;
643 1.1 jmcneill
644 1.1 jmcneill tbl = pci_conf_read(pa->pa_pc, pa->pa_tag, off + PCI_MSIX_TBLOFFSET);
645 1.1 jmcneill bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_TBLBIR_MASK));
646 1.1 jmcneill table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK;
647 1.1 jmcneill table_size = pci_msix_count(pa->pa_pc, pa->pa_tag) * PCI_MSIX_TABLE_ENTRY_SIZE;
648 1.1 jmcneill if (table_size == 0)
649 1.1 jmcneill return NULL;
650 1.1 jmcneill
651 1.1 jmcneill error = pci_mapreg_submap(pa, bar, pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar),
652 1.1 jmcneill BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset,
653 1.1 jmcneill &bst, &bsh, NULL, &bsz);
654 1.1 jmcneill if (error)
655 1.1 jmcneill return NULL;
656 1.1 jmcneill
657 1.1 jmcneill const int msi_base = apple_pcie_msi_alloc_msi(sc, *count, pa);
658 1.1 jmcneill if (msi_base == -1) {
659 1.1 jmcneill bus_space_unmap(bst, bsh, bsz);
660 1.1 jmcneill return NULL;
661 1.1 jmcneill }
662 1.1 jmcneill
663 1.1 jmcneill vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
664 1.1 jmcneill for (n = 0; n < *count; n++) {
665 1.1 jmcneill const int msino = msi_base + n;
666 1.1 jmcneill const int msix_vec = table_indexes ? table_indexes[n] : n;
667 1.1 jmcneill vectors[msix_vec] = ARM_PCI_INTR_MSIX |
668 1.1 jmcneill __SHIFTIN(msino, ARM_PCI_INTR_IRQ) |
669 1.1 jmcneill __SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) |
670 1.1 jmcneill __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
671 1.1 jmcneill
672 1.1 jmcneill apple_pcie_msi_msix_enable(sc, msino, msix_vec, bst, bsh);
673 1.1 jmcneill }
674 1.1 jmcneill
675 1.1 jmcneill bus_space_unmap(bst, bsh, bsz);
676 1.1 jmcneill
677 1.1 jmcneill return vectors;
678 1.1 jmcneill }
679 1.1 jmcneill
680 1.1 jmcneill static void *
681 1.1 jmcneill apple_pcie_msi_intr_establish(struct arm_pci_msi *msi,
682 1.1 jmcneill pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg, const char *xname)
683 1.1 jmcneill {
684 1.1 jmcneill struct apple_pcie_softc * const sc = msi->msi_priv;
685 1.1 jmcneill
686 1.1 jmcneill const int msino = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);
687 1.1 jmcneill const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0;
688 1.1 jmcneill
689 1.1 jmcneill KASSERT(sc->sc_msi_ih[msino] == NULL);
690 1.1 jmcneill sc->sc_msi_ih[msino] = intr_establish_xname(sc->sc_msi_start + msino,
691 1.1 jmcneill ipl, IST_LEVEL | (mpsafe ? IST_MPSAFE : 0), func, arg, xname);
692 1.1 jmcneill
693 1.1 jmcneill return sc->sc_msi_ih[msino];
694 1.1 jmcneill }
695 1.1 jmcneill
696 1.1 jmcneill static void
697 1.1 jmcneill apple_pcie_msi_intr_release(struct arm_pci_msi *msi, pci_intr_handle_t *pih,
698 1.1 jmcneill int count)
699 1.1 jmcneill {
700 1.1 jmcneill struct apple_pcie_softc * const sc = msi->msi_priv;
701 1.1 jmcneill int n;
702 1.1 jmcneill
703 1.1 jmcneill for (n = 0; n < count; n++) {
704 1.1 jmcneill const int msino = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ);
705 1.1 jmcneill if (pih[n] & ARM_PCI_INTR_MSIX)
706 1.1 jmcneill apple_pcie_msi_msix_disable(sc, msino);
707 1.1 jmcneill if (pih[n] & ARM_PCI_INTR_MSI)
708 1.1 jmcneill apple_pcie_msi_msi_disable(sc, msino);
709 1.1 jmcneill apple_pcie_msi_free_msi(sc, msino);
710 1.1 jmcneill if (sc->sc_msi_ih[msino] != NULL) {
711 1.1 jmcneill intr_disestablish(sc->sc_msi_ih[msino]);
712 1.1 jmcneill sc->sc_msi_ih[msino] = NULL;
713 1.1 jmcneill }
714 1.1 jmcneill }
715 1.1 jmcneill }
716 1.1 jmcneill
717 1.1 jmcneill static int
718 1.1 jmcneill apple_pcie_msi_init(struct apple_pcie_softc *sc)
719 1.1 jmcneill {
720 1.1 jmcneill struct arm_pci_msi *msi = &sc->sc_msi;
721 1.1 jmcneill const int phandle = sc->sc_pcihost.sc_phandle;
722 1.1 jmcneill int len;
723 1.1 jmcneill
724 1.1 jmcneill const u_int *data = fdtbus_get_prop(phandle, "msi-ranges", &len);
725 1.5 jmcneill switch (len) {
726 1.5 jmcneill case 8:
727 1.5 jmcneill /* two cells: start and count */
728 1.5 jmcneill sc->sc_msi_start = be32toh(data[0]);
729 1.5 jmcneill sc->sc_nmsi = be32toh(data[1]);
730 1.5 jmcneill break;
731 1.5 jmcneill case 20:
732 1.5 jmcneill /* 5 cells: xref, specifier (3 cells), and count */
733 1.5 jmcneill sc->sc_msi_start = be32toh(data[2]);
734 1.5 jmcneill sc->sc_nmsi = be32toh(data[4]);
735 1.5 jmcneill break;
736 1.5 jmcneill default:
737 1.1 jmcneill aprint_error_dev(sc->sc_pcihost.sc_dev,
738 1.1 jmcneill "WARNING: bad msi-ranges property, MSI not enabled!\n");
739 1.1 jmcneill return ENXIO;
740 1.1 jmcneill }
741 1.1 jmcneill sc->sc_msi_pa = kmem_zalloc(sizeof(*sc->sc_msi_pa) * sc->sc_nmsi,
742 1.1 jmcneill KM_SLEEP);
743 1.1 jmcneill sc->sc_msi_ih = kmem_zalloc(sizeof(*sc->sc_msi_ih) * sc->sc_nmsi,
744 1.1 jmcneill KM_SLEEP);
745 1.1 jmcneill
746 1.1 jmcneill if (of_getprop_uint64(phandle, "msi-doorbell", &sc->sc_msi_addr)) {
747 1.1 jmcneill sc->sc_msi_addr = 0xffff000ULL;
748 1.1 jmcneill }
749 1.1 jmcneill
750 1.1 jmcneill msi->msi_dev = sc->sc_pcihost.sc_dev;
751 1.1 jmcneill msi->msi_priv = sc;
752 1.1 jmcneill msi->msi_alloc = apple_pcie_msi_msi_alloc;
753 1.1 jmcneill msi->msix_alloc = apple_pcie_msi_msix_alloc;
754 1.1 jmcneill msi->msi_intr_establish = apple_pcie_msi_intr_establish;
755 1.1 jmcneill msi->msi_intr_release = apple_pcie_msi_intr_release;
756 1.1 jmcneill
757 1.1 jmcneill return arm_pci_msi_add(msi);
758 1.1 jmcneill }
759