apple_pcie.c revision 1.3
1 /* $NetBSD: apple_pcie.c,v 1.3 2021/09/06 14:03:17 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2021 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: apple_pcie.c,v 1.3 2021/09/06 14:03:17 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kmem.h> 38 #include <sys/bitops.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pciconf.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/pci/pci_msi_machdep.h> 47 #include <arm/fdt/pcihost_fdtvar.h> 48 49 #define PCIE_MSI_CTRL 0x0124 50 #define PCIE_MSI_CTRL_EN (1U << 0) 51 #define PCIE_MSI_CTRL_32 (5U << 4) 52 #define PCIE_MSI_REMAP 0x0128 53 #define PCIE_MSI_DOORBELL 0x0168 54 55 struct apple_pcie_softc { 56 struct pcihost_softc sc_pcihost; 57 58 int sc_phandle; 59 struct arm_pci_msi sc_msi; 60 u_int sc_msi_start; 61 u_int sc_nmsi; 62 struct pci_attach_args **sc_msi_pa; 63 void **sc_msi_ih; 64 uint64_t sc_msi_addr; 65 }; 66 67 static int apple_pcie_match(device_t, cfdata_t, void *); 68 static void apple_pcie_attach(device_t, device_t, void *); 69 70 static void apple_pcie_attach_hook(device_t, device_t, 71 struct pcibus_attach_args *); 72 static int apple_pcie_msi_init(struct apple_pcie_softc *); 73 74 CFATTACH_DECL_NEW(apple_pcie, sizeof(struct apple_pcie_softc), 75 apple_pcie_match, apple_pcie_attach, NULL, NULL); 76 77 static const struct device_compatible_entry compat_data[] = { 78 { .compat = "apple,pcie" }, 79 DEVICE_COMPAT_EOL 80 }; 81 82 static int 83 apple_pcie_match(device_t parent, cfdata_t cf, void *aux) 84 { 85 struct fdt_attach_args * const faa = aux; 86 87 return of_compatible_match(faa->faa_phandle, compat_data); 88 } 89 90 static void 91 apple_pcie_attach(device_t parent, device_t self, void *aux) 92 { 93 struct apple_pcie_softc * const asc = device_private(self); 94 struct pcihost_softc * const sc = &asc->sc_pcihost; 95 struct fdt_attach_args * const faa = aux; 96 const int phandle = faa->faa_phandle; 97 bus_addr_t cs_addr; 98 bus_size_t cs_size; 99 int error; 100 101 if (fdtbus_get_reg(phandle, 0, &cs_addr, &cs_size) != 0) { 102 aprint_error(": couldn't get registers\n"); 103 return; 104 } 105 106 sc->sc_dev = self; 107 sc->sc_dmat = faa->faa_dmat; 108 sc->sc_bst = faa->faa_bst; 109 /* 110 * Create a new bus tag for PCIe devices that does not inherit the 111 * nonposted MMIO flag from the host controller. 112 */ 113 sc->sc_pci_bst = fdtbus_bus_tag_create(phandle, 0); 114 sc->sc_phandle = phandle; 115 error = bus_space_map(faa->faa_bst, cs_addr, cs_size, 0, &sc->sc_bsh); 116 if (error) { 117 aprint_error(": couldn't map registers: %d\n", error); 118 return; 119 } 120 sc->sc_type = PCIHOST_ECAM; 121 122 if (apple_pcie_msi_init(asc) == 0) { 123 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 124 #if notyet 125 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 126 #endif 127 } 128 129 aprint_naive("\n"); 130 aprint_normal(": Apple PCIe host controller\n"); 131 132 pcihost_init(&sc->sc_pc, sc); 133 sc->sc_pc.pc_attach_hook = apple_pcie_attach_hook; 134 pcihost_init2(sc); 135 } 136 137 static void 138 apple_pcie_setup_port(struct apple_pcie_softc *sc, u_int portno) 139 { 140 const int phandle = sc->sc_pcihost.sc_phandle; 141 bus_space_tag_t bst = sc->sc_pcihost.sc_bst; 142 char regname[sizeof("portX")]; 143 bus_space_handle_t bsh; 144 bus_addr_t addr; 145 bus_size_t size; 146 int error; 147 148 snprintf(regname, sizeof(regname), "port%u", portno); 149 if (fdtbus_get_reg_byname(phandle, regname, &addr, &size) != 0) { 150 aprint_error(": couldn't get %s regs\n", regname); 151 return; 152 } 153 error = bus_space_map(bst, addr, size, 0, &bsh); 154 if (error != 0) { 155 aprint_error(": couldn't map %s regs\n", regname); 156 return; 157 } 158 159 /* Doorbell address must be below 4GB */ 160 KASSERT((sc->sc_msi_addr & ~0xffffffffUL) == 0); 161 162 bus_space_write_4(bst, bsh, PCIE_MSI_CTRL, 163 PCIE_MSI_CTRL_32 | PCIE_MSI_CTRL_EN); 164 bus_space_write_4(bst, bsh, PCIE_MSI_REMAP, 0); 165 bus_space_write_4(bst, bsh, PCIE_MSI_DOORBELL, 166 (uint32_t)sc->sc_msi_addr); 167 168 bus_space_unmap(bst, bsh, size); 169 } 170 171 static void 172 apple_pcie_attach_hook(device_t parent, device_t self, 173 struct pcibus_attach_args *pba) 174 { 175 struct apple_pcie_softc *sc = pba->pba_pc->pc_conf_v; 176 const int phandle = sc->sc_pcihost.sc_phandle; 177 bus_dma_tag_t dmat; 178 179 KASSERT(device_is_a(sc->sc_pcihost.sc_dev, "applepcie")); 180 181 /* XXX this should be per-device, not per-bus */ 182 const uint32_t rid = pba->pba_bus << 8; 183 184 dmat = fdtbus_iommu_map_pci(phandle, rid, sc->sc_pcihost.sc_dmat); 185 pba->pba_dmat = pba->pba_dmat64 = dmat; 186 } 187 188 static int 189 apple_pcie_msi_alloc_msi(struct apple_pcie_softc *sc, int count, 190 const struct pci_attach_args *pa) 191 { 192 struct pci_attach_args *new_pa; 193 int msi, n; 194 195 for (msi = 0; msi < sc->sc_nmsi; msi += count) { 196 if (sc->sc_msi_pa[msi] == NULL) { 197 for (n = 1; n < count; n++) { 198 if (msi + n < sc->sc_nmsi && 199 sc->sc_msi_pa[msi + n] != NULL) { 200 continue; 201 } 202 } 203 204 for (n = 0; n < count; n++) { 205 new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP); 206 memcpy(new_pa, pa, sizeof(*new_pa)); 207 sc->sc_msi_pa[msi + n] = new_pa; 208 } 209 210 return msi; 211 } 212 } 213 214 return -1; 215 } 216 217 static void 218 apple_pcie_msi_free_msi(struct apple_pcie_softc *sc, int msi) 219 { 220 struct pci_attach_args *pa; 221 222 pa = sc->sc_msi_pa[msi]; 223 sc->sc_msi_pa[msi] = NULL; 224 225 if (pa != NULL) { 226 kmem_free(pa, sizeof(*pa)); 227 } 228 } 229 230 static int 231 apple_pcie_msi_available_msi(struct apple_pcie_softc *sc) 232 { 233 int msi, n; 234 235 for (n = 0, msi = 0; msi < sc->sc_nmsi; msi++) { 236 if (sc->sc_msi_pa[msi] == NULL) { 237 n++; 238 } 239 } 240 241 return n; 242 } 243 244 static void 245 apple_pcie_msi_msi_enable(struct apple_pcie_softc *sc, int msi, int count) 246 { 247 const struct pci_attach_args *pa = sc->sc_msi_pa[msi]; 248 pci_chipset_tag_t pc = pa->pa_pc; 249 pcitag_t tag = pa->pa_tag; 250 pcireg_t ctl; 251 int off; 252 253 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 254 panic("apple_pcie_msi_msi_enable: device is not MSI-capable"); 255 256 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 257 ctl &= ~PCI_MSI_CTL_MSI_ENABLE; 258 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 259 260 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 261 ctl &= ~PCI_MSI_CTL_MME_MASK; 262 ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK); 263 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 264 265 const uint64_t addr = sc->sc_msi_addr; 266 const uint32_t data = msi; 267 268 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 269 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 270 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO, 271 addr & 0xffffffff); 272 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI, 273 (addr >> 32) & 0xffffffff); 274 pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, data); 275 } else { 276 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, 277 addr & 0xffffffff); 278 pci_conf_write(pc, tag, off + PCI_MSI_MDATA, data); 279 } 280 ctl |= PCI_MSI_CTL_MSI_ENABLE; 281 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 282 } 283 284 static void 285 apple_pcie_msi_msi_disable(struct apple_pcie_softc *sc, int msi) 286 { 287 const struct pci_attach_args *pa = sc->sc_msi_pa[msi]; 288 pci_chipset_tag_t pc = pa->pa_pc; 289 pcitag_t tag = pa->pa_tag; 290 pcireg_t ctl; 291 int off; 292 293 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 294 panic("apple_pcie_msi_msi_disable: device is not MSI-capable"); 295 296 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 297 ctl &= ~PCI_MSI_CTL_MSI_ENABLE; 298 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 299 } 300 301 static void 302 apple_pcie_msi_msix_enable(struct apple_pcie_softc *sc, int msi, int msix_vec, 303 bus_space_tag_t bst, bus_space_handle_t bsh) 304 { 305 const struct pci_attach_args *pa = sc->sc_msi_pa[msi]; 306 pci_chipset_tag_t pc = pa->pa_pc; 307 pcitag_t tag = pa->pa_tag; 308 pcireg_t ctl; 309 uint32_t val; 310 int off; 311 312 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 313 panic("apple_pcie_msi_msix_enable: device is not MSI-X-capable"); 314 315 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 316 ctl &= ~PCI_MSIX_CTL_ENABLE; 317 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 318 319 const uint64_t addr = sc->sc_msi_addr; 320 const uint32_t data = msi; 321 const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; 322 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, 323 (uint32_t)addr); 324 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, 325 (uint32_t)(addr >> 32)); 326 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, 327 data); 328 val = bus_space_read_4(bst, bsh, 329 entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); 330 val &= ~PCI_MSIX_VECTCTL_MASK; 331 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 332 val); 333 334 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 335 ctl |= PCI_MSIX_CTL_ENABLE; 336 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 337 } 338 339 static void 340 apple_pcie_msi_msix_disable(struct apple_pcie_softc *sc, int msi) 341 { 342 const struct pci_attach_args *pa = sc->sc_msi_pa[msi]; 343 pci_chipset_tag_t pc = pa->pa_pc; 344 pcitag_t tag = pa->pa_tag; 345 pcireg_t ctl; 346 int off; 347 348 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 349 panic("apple_pcie_msi_msix_disable: device is not MSI-X-capable"); 350 351 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 352 ctl &= ~PCI_MSIX_CTL_ENABLE; 353 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 354 } 355 356 static pci_intr_handle_t * 357 apple_pcie_msi_msi_alloc(struct arm_pci_msi *msi, int *count, 358 const struct pci_attach_args *pa, bool exact) 359 { 360 struct apple_pcie_softc * const sc = msi->msi_priv; 361 pci_intr_handle_t *vectors; 362 int n, off; 363 364 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &off, NULL)) 365 return NULL; 366 367 const int avail = apple_pcie_msi_available_msi(sc); 368 if (exact && *count > avail) 369 return NULL; 370 371 while (*count > avail) { 372 if (avail < *count) 373 (*count) >>= 1; 374 } 375 if (*count == 0) 376 return NULL; 377 378 const int msi_base = apple_pcie_msi_alloc_msi(sc, *count, pa); 379 if (msi_base == -1) 380 return NULL; 381 382 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 383 for (n = 0; n < *count; n++) { 384 const int msino = msi_base + n; 385 vectors[n] = ARM_PCI_INTR_MSI | 386 __SHIFTIN(msino, ARM_PCI_INTR_IRQ) | 387 __SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) | 388 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 389 } 390 391 apple_pcie_msi_msi_enable(sc, msi_base, *count); 392 393 return vectors; 394 } 395 396 static pci_intr_handle_t * 397 apple_pcie_msi_msix_alloc(struct arm_pci_msi *msi, u_int *table_indexes, 398 int *count, const struct pci_attach_args *pa, bool exact) 399 { 400 struct apple_pcie_softc * const sc = msi->msi_priv; 401 pci_intr_handle_t *vectors; 402 bus_space_tag_t bst; 403 bus_space_handle_t bsh; 404 bus_size_t bsz; 405 uint32_t table_offset, table_size; 406 int n, off, bar, error; 407 pcireg_t tbl; 408 409 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &off, NULL)) 410 return NULL; 411 412 const int avail = apple_pcie_msi_available_msi(sc); 413 if (exact && *count > avail) 414 return NULL; 415 416 while (*count > avail) { 417 if (avail < *count) 418 (*count) >>= 1; 419 } 420 if (*count == 0) 421 return NULL; 422 423 tbl = pci_conf_read(pa->pa_pc, pa->pa_tag, off + PCI_MSIX_TBLOFFSET); 424 bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_TBLBIR_MASK)); 425 table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK; 426 table_size = pci_msix_count(pa->pa_pc, pa->pa_tag) * PCI_MSIX_TABLE_ENTRY_SIZE; 427 if (table_size == 0) 428 return NULL; 429 430 error = pci_mapreg_submap(pa, bar, pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar), 431 BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset, 432 &bst, &bsh, NULL, &bsz); 433 if (error) 434 return NULL; 435 436 const int msi_base = apple_pcie_msi_alloc_msi(sc, *count, pa); 437 if (msi_base == -1) { 438 bus_space_unmap(bst, bsh, bsz); 439 return NULL; 440 } 441 442 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 443 for (n = 0; n < *count; n++) { 444 const int msino = msi_base + n; 445 const int msix_vec = table_indexes ? table_indexes[n] : n; 446 vectors[msix_vec] = ARM_PCI_INTR_MSIX | 447 __SHIFTIN(msino, ARM_PCI_INTR_IRQ) | 448 __SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) | 449 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 450 451 apple_pcie_msi_msix_enable(sc, msino, msix_vec, bst, bsh); 452 } 453 454 bus_space_unmap(bst, bsh, bsz); 455 456 return vectors; 457 } 458 459 static void * 460 apple_pcie_msi_intr_establish(struct arm_pci_msi *msi, 461 pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg, const char *xname) 462 { 463 struct apple_pcie_softc * const sc = msi->msi_priv; 464 465 const int msino = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 466 const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 467 468 KASSERT(sc->sc_msi_ih[msino] == NULL); 469 sc->sc_msi_ih[msino] = intr_establish_xname(sc->sc_msi_start + msino, 470 ipl, IST_LEVEL | (mpsafe ? IST_MPSAFE : 0), func, arg, xname); 471 472 return sc->sc_msi_ih[msino]; 473 } 474 475 static void 476 apple_pcie_msi_intr_release(struct arm_pci_msi *msi, pci_intr_handle_t *pih, 477 int count) 478 { 479 struct apple_pcie_softc * const sc = msi->msi_priv; 480 int n; 481 482 for (n = 0; n < count; n++) { 483 const int msino = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ); 484 if (pih[n] & ARM_PCI_INTR_MSIX) 485 apple_pcie_msi_msix_disable(sc, msino); 486 if (pih[n] & ARM_PCI_INTR_MSI) 487 apple_pcie_msi_msi_disable(sc, msino); 488 apple_pcie_msi_free_msi(sc, msino); 489 if (sc->sc_msi_ih[msino] != NULL) { 490 intr_disestablish(sc->sc_msi_ih[msino]); 491 sc->sc_msi_ih[msino] = NULL; 492 } 493 } 494 } 495 496 static int 497 apple_pcie_msi_init(struct apple_pcie_softc *sc) 498 { 499 struct arm_pci_msi *msi = &sc->sc_msi; 500 const int phandle = sc->sc_pcihost.sc_phandle; 501 u_int portno; 502 int len; 503 504 const u_int *data = fdtbus_get_prop(phandle, "msi-ranges", &len); 505 if (len != 8) { 506 aprint_error_dev(sc->sc_pcihost.sc_dev, 507 "WARNING: bad msi-ranges property, MSI not enabled!\n"); 508 return ENXIO; 509 } 510 sc->sc_msi_start = be32toh(data[0]); 511 sc->sc_nmsi = be32toh(data[1]); 512 sc->sc_msi_pa = kmem_zalloc(sizeof(*sc->sc_msi_pa) * sc->sc_nmsi, 513 KM_SLEEP); 514 sc->sc_msi_ih = kmem_zalloc(sizeof(*sc->sc_msi_ih) * sc->sc_nmsi, 515 KM_SLEEP); 516 517 if (of_getprop_uint64(phandle, "msi-doorbell", &sc->sc_msi_addr)) { 518 sc->sc_msi_addr = 0xffff000ULL; 519 } 520 521 for (portno = 0; portno < 3; portno++) { 522 apple_pcie_setup_port(sc, portno); 523 } 524 525 msi->msi_dev = sc->sc_pcihost.sc_dev; 526 msi->msi_priv = sc; 527 msi->msi_alloc = apple_pcie_msi_msi_alloc; 528 msi->msix_alloc = apple_pcie_msi_msix_alloc; 529 msi->msi_intr_establish = apple_pcie_msi_intr_establish; 530 msi->msi_intr_release = apple_pcie_msi_intr_release; 531 532 return arm_pci_msi_add(msi); 533 } 534
Indexes created Wed Sep 24 15:09:51 GMT 2025