apple_pcie.c revision 1.5
1 /* $NetBSD: apple_pcie.c,v 1.5 2021/09/14 01:33:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2021 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: apple_pcie.c,v 1.5 2021/09/14 01:33:19 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kmem.h> 38 #include <sys/bitops.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pciconf.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/pci/pci_msi_machdep.h> 47 #include <arm/fdt/pcihost_fdtvar.h> 48 49 #define PCIE_MSI_CTRL 0x0124 50 #define PCIE_MSI_CTRL_EN (1U << 0) 51 #define PCIE_MSI_CTRL_32 (5U << 4) 52 #define PCIE_MSI_REMAP 0x0128 53 #define PCIE_MSI_DOORBELL 0x0168 54 55 extern struct bus_space arm_generic_bs_tag; 56 57 struct apple_pcie_softc { 58 struct pcihost_softc sc_pcihost; 59 60 int sc_phandle; 61 struct arm_pci_msi sc_msi; 62 u_int sc_msi_start; 63 u_int sc_nmsi; 64 struct pci_attach_args **sc_msi_pa; 65 void **sc_msi_ih; 66 uint64_t sc_msi_addr; 67 }; 68 69 static int apple_pcie_match(device_t, cfdata_t, void *); 70 static void apple_pcie_attach(device_t, device_t, void *); 71 72 static void apple_pcie_attach_hook(device_t, device_t, 73 struct pcibus_attach_args *); 74 static int apple_pcie_msi_init(struct apple_pcie_softc *); 75 76 CFATTACH_DECL_NEW(apple_pcie, sizeof(struct apple_pcie_softc), 77 apple_pcie_match, apple_pcie_attach, NULL, NULL); 78 79 static const struct device_compatible_entry compat_data[] = { 80 { .compat = "apple,pcie" }, 81 DEVICE_COMPAT_EOL 82 }; 83 84 static int 85 apple_pcie_match(device_t parent, cfdata_t cf, void *aux) 86 { 87 struct fdt_attach_args * const faa = aux; 88 89 return of_compatible_match(faa->faa_phandle, compat_data); 90 } 91 92 static void 93 apple_pcie_attach(device_t parent, device_t self, void *aux) 94 { 95 struct apple_pcie_softc * const asc = device_private(self); 96 struct pcihost_softc * const sc = &asc->sc_pcihost; 97 struct fdt_attach_args * const faa = aux; 98 const int phandle = faa->faa_phandle; 99 bus_addr_t cs_addr; 100 bus_size_t cs_size; 101 int error; 102 103 if (fdtbus_get_reg(phandle, 0, &cs_addr, &cs_size) != 0) { 104 aprint_error(": couldn't get registers\n"); 105 return; 106 } 107 108 sc->sc_dev = self; 109 sc->sc_dmat = faa->faa_dmat; 110 sc->sc_bst = faa->faa_bst; 111 /* 112 * Create a new bus tag for PCIe devices that does not inherit the 113 * nonposted MMIO flag from the host controller. 114 */ 115 sc->sc_pci_bst = &arm_generic_bs_tag; 116 sc->sc_phandle = phandle; 117 error = bus_space_map(faa->faa_bst, cs_addr, cs_size, 0, &sc->sc_bsh); 118 if (error) { 119 aprint_error(": couldn't map registers: %d\n", error); 120 return; 121 } 122 sc->sc_type = PCIHOST_ECAM; 123 124 if (apple_pcie_msi_init(asc) == 0) { 125 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 126 #if notyet 127 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 128 #endif 129 } 130 131 aprint_naive("\n"); 132 aprint_normal(": Apple PCIe host controller\n"); 133 134 pcihost_init(&sc->sc_pc, sc); 135 sc->sc_pc.pc_attach_hook = apple_pcie_attach_hook; 136 pcihost_init2(sc); 137 } 138 139 static void 140 apple_pcie_setup_port(struct apple_pcie_softc *sc, u_int portno) 141 { 142 const int phandle = sc->sc_pcihost.sc_phandle; 143 bus_space_tag_t bst = sc->sc_pcihost.sc_bst; 144 char regname[sizeof("portX")]; 145 bus_space_handle_t bsh; 146 bus_addr_t addr; 147 bus_size_t size; 148 int error; 149 150 snprintf(regname, sizeof(regname), "port%u", portno); 151 if (fdtbus_get_reg_byname(phandle, regname, &addr, &size) != 0) { 152 aprint_error(": couldn't get %s regs\n", regname); 153 return; 154 } 155 error = bus_space_map(bst, addr, size, 0, &bsh); 156 if (error != 0) { 157 aprint_error(": couldn't map %s regs\n", regname); 158 return; 159 } 160 161 /* Doorbell address must be below 4GB */ 162 KASSERT((sc->sc_msi_addr & ~0xffffffffUL) == 0); 163 164 bus_space_write_4(bst, bsh, PCIE_MSI_CTRL, 165 PCIE_MSI_CTRL_32 | PCIE_MSI_CTRL_EN); 166 bus_space_write_4(bst, bsh, PCIE_MSI_REMAP, 0); 167 bus_space_write_4(bst, bsh, PCIE_MSI_DOORBELL, 168 (uint32_t)sc->sc_msi_addr); 169 170 bus_space_unmap(bst, bsh, size); 171 } 172 173 static void 174 apple_pcie_attach_hook(device_t parent, device_t self, 175 struct pcibus_attach_args *pba) 176 { 177 struct apple_pcie_softc *sc = pba->pba_pc->pc_conf_v; 178 const int phandle = sc->sc_pcihost.sc_phandle; 179 bus_dma_tag_t dmat; 180 181 KASSERT(device_is_a(sc->sc_pcihost.sc_dev, "applepcie")); 182 183 /* XXX this should be per-device, not per-bus */ 184 const uint32_t rid = pba->pba_bus << 8; 185 186 dmat = fdtbus_iommu_map_pci(phandle, rid, sc->sc_pcihost.sc_dmat); 187 pba->pba_dmat = pba->pba_dmat64 = dmat; 188 } 189 190 static int 191 apple_pcie_msi_alloc_msi(struct apple_pcie_softc *sc, int count, 192 const struct pci_attach_args *pa) 193 { 194 struct pci_attach_args *new_pa; 195 int msi, n; 196 197 for (msi = 0; msi < sc->sc_nmsi; msi += count) { 198 if (sc->sc_msi_pa[msi] == NULL) { 199 for (n = 1; n < count; n++) { 200 if (msi + n < sc->sc_nmsi && 201 sc->sc_msi_pa[msi + n] != NULL) { 202 continue; 203 } 204 } 205 206 for (n = 0; n < count; n++) { 207 new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP); 208 memcpy(new_pa, pa, sizeof(*new_pa)); 209 sc->sc_msi_pa[msi + n] = new_pa; 210 } 211 212 return msi; 213 } 214 } 215 216 return -1; 217 } 218 219 static void 220 apple_pcie_msi_free_msi(struct apple_pcie_softc *sc, int msi) 221 { 222 struct pci_attach_args *pa; 223 224 pa = sc->sc_msi_pa[msi]; 225 sc->sc_msi_pa[msi] = NULL; 226 227 if (pa != NULL) { 228 kmem_free(pa, sizeof(*pa)); 229 } 230 } 231 232 static int 233 apple_pcie_msi_available_msi(struct apple_pcie_softc *sc) 234 { 235 int msi, n; 236 237 for (n = 0, msi = 0; msi < sc->sc_nmsi; msi++) { 238 if (sc->sc_msi_pa[msi] == NULL) { 239 n++; 240 } 241 } 242 243 return n; 244 } 245 246 static void 247 apple_pcie_msi_msi_enable(struct apple_pcie_softc *sc, int msi, int count) 248 { 249 const struct pci_attach_args *pa = sc->sc_msi_pa[msi]; 250 pci_chipset_tag_t pc = pa->pa_pc; 251 pcitag_t tag = pa->pa_tag; 252 pcireg_t ctl; 253 int off; 254 255 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 256 panic("apple_pcie_msi_msi_enable: device is not MSI-capable"); 257 258 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 259 ctl &= ~PCI_MSI_CTL_MSI_ENABLE; 260 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 261 262 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 263 ctl &= ~PCI_MSI_CTL_MME_MASK; 264 ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK); 265 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 266 267 const uint64_t addr = sc->sc_msi_addr; 268 const uint32_t data = msi; 269 270 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 271 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 272 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO, 273 addr & 0xffffffff); 274 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI, 275 (addr >> 32) & 0xffffffff); 276 pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, data); 277 } else { 278 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, 279 addr & 0xffffffff); 280 pci_conf_write(pc, tag, off + PCI_MSI_MDATA, data); 281 } 282 ctl |= PCI_MSI_CTL_MSI_ENABLE; 283 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 284 } 285 286 static void 287 apple_pcie_msi_msi_disable(struct apple_pcie_softc *sc, int msi) 288 { 289 const struct pci_attach_args *pa = sc->sc_msi_pa[msi]; 290 pci_chipset_tag_t pc = pa->pa_pc; 291 pcitag_t tag = pa->pa_tag; 292 pcireg_t ctl; 293 int off; 294 295 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 296 panic("apple_pcie_msi_msi_disable: device is not MSI-capable"); 297 298 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 299 ctl &= ~PCI_MSI_CTL_MSI_ENABLE; 300 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 301 } 302 303 static void 304 apple_pcie_msi_msix_enable(struct apple_pcie_softc *sc, int msi, int msix_vec, 305 bus_space_tag_t bst, bus_space_handle_t bsh) 306 { 307 const struct pci_attach_args *pa = sc->sc_msi_pa[msi]; 308 pci_chipset_tag_t pc = pa->pa_pc; 309 pcitag_t tag = pa->pa_tag; 310 pcireg_t ctl; 311 uint32_t val; 312 int off; 313 314 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 315 panic("apple_pcie_msi_msix_enable: device is not MSI-X-capable"); 316 317 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 318 ctl &= ~PCI_MSIX_CTL_ENABLE; 319 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 320 321 const uint64_t addr = sc->sc_msi_addr; 322 const uint32_t data = msi; 323 const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; 324 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, 325 (uint32_t)addr); 326 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, 327 (uint32_t)(addr >> 32)); 328 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, 329 data); 330 val = bus_space_read_4(bst, bsh, 331 entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); 332 val &= ~PCI_MSIX_VECTCTL_MASK; 333 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 334 val); 335 336 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 337 ctl |= PCI_MSIX_CTL_ENABLE; 338 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 339 } 340 341 static void 342 apple_pcie_msi_msix_disable(struct apple_pcie_softc *sc, int msi) 343 { 344 const struct pci_attach_args *pa = sc->sc_msi_pa[msi]; 345 pci_chipset_tag_t pc = pa->pa_pc; 346 pcitag_t tag = pa->pa_tag; 347 pcireg_t ctl; 348 int off; 349 350 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 351 panic("apple_pcie_msi_msix_disable: device is not MSI-X-capable"); 352 353 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 354 ctl &= ~PCI_MSIX_CTL_ENABLE; 355 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 356 } 357 358 static pci_intr_handle_t * 359 apple_pcie_msi_msi_alloc(struct arm_pci_msi *msi, int *count, 360 const struct pci_attach_args *pa, bool exact) 361 { 362 struct apple_pcie_softc * const sc = msi->msi_priv; 363 pci_intr_handle_t *vectors; 364 int n, off; 365 366 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &off, NULL)) 367 return NULL; 368 369 const int avail = apple_pcie_msi_available_msi(sc); 370 if (exact && *count > avail) 371 return NULL; 372 373 while (*count > avail) { 374 if (avail < *count) 375 (*count) >>= 1; 376 } 377 if (*count == 0) 378 return NULL; 379 380 const int msi_base = apple_pcie_msi_alloc_msi(sc, *count, pa); 381 if (msi_base == -1) 382 return NULL; 383 384 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 385 for (n = 0; n < *count; n++) { 386 const int msino = msi_base + n; 387 vectors[n] = ARM_PCI_INTR_MSI | 388 __SHIFTIN(msino, ARM_PCI_INTR_IRQ) | 389 __SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) | 390 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 391 } 392 393 apple_pcie_msi_msi_enable(sc, msi_base, *count); 394 395 return vectors; 396 } 397 398 static pci_intr_handle_t * 399 apple_pcie_msi_msix_alloc(struct arm_pci_msi *msi, u_int *table_indexes, 400 int *count, const struct pci_attach_args *pa, bool exact) 401 { 402 struct apple_pcie_softc * const sc = msi->msi_priv; 403 pci_intr_handle_t *vectors; 404 bus_space_tag_t bst; 405 bus_space_handle_t bsh; 406 bus_size_t bsz; 407 uint32_t table_offset, table_size; 408 int n, off, bar, error; 409 pcireg_t tbl; 410 411 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &off, NULL)) 412 return NULL; 413 414 const int avail = apple_pcie_msi_available_msi(sc); 415 if (exact && *count > avail) 416 return NULL; 417 418 while (*count > avail) { 419 if (avail < *count) 420 (*count) >>= 1; 421 } 422 if (*count == 0) 423 return NULL; 424 425 tbl = pci_conf_read(pa->pa_pc, pa->pa_tag, off + PCI_MSIX_TBLOFFSET); 426 bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_TBLBIR_MASK)); 427 table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK; 428 table_size = pci_msix_count(pa->pa_pc, pa->pa_tag) * PCI_MSIX_TABLE_ENTRY_SIZE; 429 if (table_size == 0) 430 return NULL; 431 432 error = pci_mapreg_submap(pa, bar, pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar), 433 BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset, 434 &bst, &bsh, NULL, &bsz); 435 if (error) 436 return NULL; 437 438 const int msi_base = apple_pcie_msi_alloc_msi(sc, *count, pa); 439 if (msi_base == -1) { 440 bus_space_unmap(bst, bsh, bsz); 441 return NULL; 442 } 443 444 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 445 for (n = 0; n < *count; n++) { 446 const int msino = msi_base + n; 447 const int msix_vec = table_indexes ? table_indexes[n] : n; 448 vectors[msix_vec] = ARM_PCI_INTR_MSIX | 449 __SHIFTIN(msino, ARM_PCI_INTR_IRQ) | 450 __SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) | 451 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 452 453 apple_pcie_msi_msix_enable(sc, msino, msix_vec, bst, bsh); 454 } 455 456 bus_space_unmap(bst, bsh, bsz); 457 458 return vectors; 459 } 460 461 static void * 462 apple_pcie_msi_intr_establish(struct arm_pci_msi *msi, 463 pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg, const char *xname) 464 { 465 struct apple_pcie_softc * const sc = msi->msi_priv; 466 467 const int msino = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 468 const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 469 470 KASSERT(sc->sc_msi_ih[msino] == NULL); 471 sc->sc_msi_ih[msino] = intr_establish_xname(sc->sc_msi_start + msino, 472 ipl, IST_LEVEL | (mpsafe ? IST_MPSAFE : 0), func, arg, xname); 473 474 return sc->sc_msi_ih[msino]; 475 } 476 477 static void 478 apple_pcie_msi_intr_release(struct arm_pci_msi *msi, pci_intr_handle_t *pih, 479 int count) 480 { 481 struct apple_pcie_softc * const sc = msi->msi_priv; 482 int n; 483 484 for (n = 0; n < count; n++) { 485 const int msino = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ); 486 if (pih[n] & ARM_PCI_INTR_MSIX) 487 apple_pcie_msi_msix_disable(sc, msino); 488 if (pih[n] & ARM_PCI_INTR_MSI) 489 apple_pcie_msi_msi_disable(sc, msino); 490 apple_pcie_msi_free_msi(sc, msino); 491 if (sc->sc_msi_ih[msino] != NULL) { 492 intr_disestablish(sc->sc_msi_ih[msino]); 493 sc->sc_msi_ih[msino] = NULL; 494 } 495 } 496 } 497 498 static int 499 apple_pcie_msi_init(struct apple_pcie_softc *sc) 500 { 501 struct arm_pci_msi *msi = &sc->sc_msi; 502 const int phandle = sc->sc_pcihost.sc_phandle; 503 u_int portno; 504 int len; 505 506 const u_int *data = fdtbus_get_prop(phandle, "msi-ranges", &len); 507 switch (len) { 508 case 8: 509 /* two cells: start and count */ 510 sc->sc_msi_start = be32toh(data[0]); 511 sc->sc_nmsi = be32toh(data[1]); 512 break; 513 case 20: 514 /* 5 cells: xref, specifier (3 cells), and count */ 515 sc->sc_msi_start = be32toh(data[2]); 516 sc->sc_nmsi = be32toh(data[4]); 517 break; 518 default: 519 aprint_error_dev(sc->sc_pcihost.sc_dev, 520 "WARNING: bad msi-ranges property, MSI not enabled!\n"); 521 return ENXIO; 522 } 523 sc->sc_msi_pa = kmem_zalloc(sizeof(*sc->sc_msi_pa) * sc->sc_nmsi, 524 KM_SLEEP); 525 sc->sc_msi_ih = kmem_zalloc(sizeof(*sc->sc_msi_ih) * sc->sc_nmsi, 526 KM_SLEEP); 527 528 if (of_getprop_uint64(phandle, "msi-doorbell", &sc->sc_msi_addr)) { 529 sc->sc_msi_addr = 0xffff000ULL; 530 } 531 532 for (portno = 0; portno < 3; portno++) { 533 apple_pcie_setup_port(sc, portno); 534 } 535 536 msi->msi_dev = sc->sc_pcihost.sc_dev; 537 msi->msi_priv = sc; 538 msi->msi_alloc = apple_pcie_msi_msi_alloc; 539 msi->msix_alloc = apple_pcie_msi_msix_alloc; 540 msi->msi_intr_establish = apple_pcie_msi_intr_establish; 541 msi->msi_intr_release = apple_pcie_msi_intr_release; 542 543 return arm_pci_msi_add(msi); 544 } 545
Indexes created Tue Sep 23 23:09:58 GMT 2025