cpufunc_asm_arm1136.S revision 1.2
1 /* $NetBSD: cpufunc_asm_arm1136.S,v 1.2 2008/04/27 18:58:43 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Microsoft 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Microsoft 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include "assym.h" 33 #include <machine/cpu.h> 34 #include <machine/asm.h> 35 36 RCSID("$NetBSD: cpufunc_asm_arm1136.S,v 1.2 2008/04/27 18:58:43 matt Exp $") 37 38 #if 0 39 #define Invalidate_I_cache(Rtmp1, Rtmp2) \ 40 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */ 41 #else 42 /* 43 * Workaround Erratum 411920 44 * 45 * - value of arg 'reg' Should Be Zero 46 */ 47 #define Invalidate_I_cache(Rtmp1, Rtmp2) \ 48 mov Rtmp1, #0; /* SBZ */ \ 49 mrs Rtmp2, cpsr; \ 50 cpsid ifa; \ 51 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 52 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 53 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 54 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 55 msr cpsr_cx, Rtmp2; \ 56 nop; \ 57 nop; \ 58 nop; \ 59 nop; \ 60 nop; \ 61 nop; \ 62 nop; \ 63 nop; \ 64 nop; \ 65 nop; \ 66 nop; 67 #endif 68 69 #if 1 70 #define Flush_D_cache(reg) \ 71 mov reg, #0; /* SBZ */ \ 72 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ 73 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ 74 #else 75 #define Flush_D_cache(reg) \ 76 1: mov reg, #0; /* SBZ */ \ 77 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ 78 mrc p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */ \ 79 ands reg, reg, #01; /* Check if it is clean */ \ 80 bne 1b; /* loop if not */ \ 81 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ 82 #endif 83 84 ENTRY(arm1136_setttb) 85 #ifdef PMAP_CACHE_VIVT 86 Flush_D_cache(r1) 87 Invalidate_I_cache(r1, r2) 88 #endif 89 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 90 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */ 91 mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */ 92 RET 93 94 ENTRY_NP(arm1136_idcache_wbinv_all) 95 Flush_D_cache(r0) 96 Invalidate_I_cache(r0, r1) 97 RET 98 99 ENTRY_NP(arm1136_dcache_wbinv_all) 100 Flush_D_cache(r0) 101 RET 102 103 ENTRY_NP(arm1136_icache_sync_all) 104 Flush_D_cache(r0) 105 Invalidate_I_cache(r0, r1) 106 RET 107 108 ENTRY_NP(arm1136_flush_prefetchbuf) 109 mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */ 110 RET 111 112 ENTRY_NP(arm1136_icache_sync_range) 113 add r1, r1, r0 114 sub r1, r1, #1 115 /* Erratum 371025, workaround #2 */ 116 mrs r2, cpsr /* save the CPSR */ 117 cpsid ifa /* disable interrupts (irq,fiq,abort) */ 118 mov r3, #0 119 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */ 120 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */ 121 add r3, pc, #0x24 122 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */ 123 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */ 124 msr cpsr_cx, r2 /* local_irq_restore */ 125 nop 126 nop 127 nop 128 nop 129 nop 130 nop 131 nop 132 133 mcrr p15, 0, r1, r0, c12 /* clean and invalidate D cache range */ 134 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 135 RET 136 137 ENTRY_NP(arm1136_idcache_wbinv_range) 138 add r1, r1, r0 139 sub r1, r1, #1 140 /* Erratum 371025, workaround #2 */ 141 mrs r2, cpsr /* save the CPSR */ 142 cpsid ifa /* disable interrupts (irq,fiq,abort) */ 143 mov r3, #0 144 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */ 145 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */ 146 add r3, pc, #0x24 147 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */ 148 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */ 149 msr cpsr_cx, r2 /* local_irq_restore */ 150 nop 151 nop 152 nop 153 nop 154 nop 155 nop 156 nop 157 158 mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */ 159 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 160 RET 161 162 ENTRY_NP(arm1136_sleep_rev0) /* errata 336501 */ 163 mov r0, #0 164 mcr p15, 0, r0, c7, c10, 2 /* clean data cache line (via index) */ 165 mcr p15, 0, r0, c7, c10, 5 /* data memory barrier */ 166 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ 167 RET 168
Indexes created Thu Oct 02 01:09:59 GMT 2025