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vectors.S revision 1.7 
      1 /*	$NetBSD: vectors.S,v 1.7 2013/06/12 21:34:12 matt Exp $	*/
      2 
      3 /*
      4  * Copyright (C) 1994-1997 Mark Brinicombe
      5  * Copyright (C) 1994 Brini
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed by Brini.
     19  * 4. The name of Brini may not be used to endorse or promote products
     20  *    derived from this software without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     27  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     28  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     29  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     30  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     31  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32  */
     33 
     34 #include "assym.h"
     35 #include "opt_cputypes.h"
     36 #include "opt_cpuoptions.h"
     37 #include <machine/asm.h>
     38 
     39 /*
     40  * These are the exception vectors copied down to page 0.
     41  *
     42  * Note that FIQs are special; rather than using a level of
     43  * indirection, we actually copy the FIQ code down into the
     44  * vector page.
     45  */
     46 
     47 	.text
     48 	.global _C_LABEL(fiqvector)
     49 
     50 #if defined(CPU_ARMV7) || defined(CPU_ARM11) || defined(ARM_HAS_VBAR)
     51 	/*
     52 	 * ARMv[67] processors with the Security Extension have the VBAR
     53 	 * which redirects the low vector to any 32-byte aligned address.
     54 	 * Since we are in kernel, we can just do a relative branch to the
     55 	 * exception code and avoid the intermediate load.
     56 	 */
     57 	.global	_C_LABEL(page0rel)
     58 	.p2align 5
     59 _C_LABEL(page0rel):
     60 	b	reset_entry
     61 	b	undefined_entry
     62 	b	swi_entry
     63 	b	prefetch_abort_entry
     64 	b	data_abort_entry
     65 	b	address_exception_entry
     66 	b	irq_entry
     67 #ifdef __ARM_FIQ_INDIRECT
     68 	b	_C_LABEL(fiqvector)
     69 #elif !defined(ARM_HAS_VBAR)
     70 	b	.Lfiqvector
     71 #endif
     72 #endif /* CPU_ARMV7 || CPU_ARM11 || ARM_HAS_VBAR */
     73 
     74 #ifndef ARM_HAS_VBAR
     75 	.global	_C_LABEL(page0), _C_LABEL(page0_data), _C_LABEL(page0_end)
     76 	.align	0
     77 _C_LABEL(page0):
     78 	ldr	pc, .Lreset_target
     79 	ldr	pc, .Lundefined_target
     80 	ldr	pc, .Lswi_target
     81 	ldr	pc, .Lprefetch_abort_target
     82 	ldr	pc, .Ldata_abort_target
     83 	ldr	pc, .Laddress_exception_target
     84 	ldr	pc, .Lirq_target
     85 #ifdef __ARM_FIQ_INDIRECT
     86 	ldr	pc, .Lfiq_target
     87 #endif
     88 #endif /* !ARM_HAS_VBAR */
     89 #ifndef __ARM_FIQ_INDIRECT
     90 .Lfiqvector:
     91 #ifdef ARM_HAS_VBAR
     92 	.set	_C_LABEL(fiqvector), . - _C_LABEL(page0rel)
     93 #else
     94 	.set	_C_LABEL(fiqvector), . - _C_LABEL(page0)
     95 #endif
     96 	subs	pc, lr, #4
     97 	.org	.Lfiqvector + 0x100
     98 #endif
     99 
    100 #ifndef ARM_HAS_VBAR
    101 _C_LABEL(page0_data):
    102 .Lreset_target:
    103 	.word	reset_entry
    104 
    105 .Lundefined_target:
    106 	.word	undefined_entry
    107 
    108 .Lswi_target:
    109 	.word	swi_entry
    110 
    111 .Lprefetch_abort_target:
    112 	.word	prefetch_abort_entry
    113 
    114 .Ldata_abort_target:
    115 	.word	data_abort_entry
    116 
    117 .Laddress_exception_target:
    118 	.word	address_exception_entry
    119 
    120 .Lirq_target:
    121 	.word	irq_entry
    122 
    123 #ifdef __ARM_FIQ_INDIRECT
    124 .Lfiq_target:
    125 	.word	_C_LABEL(fiqvector)
    126 #else
    127 	.word	0	/* pad it out */
    128 #endif
    129 _C_LABEL(page0_end):
    130 #endif /* ARM_HAS_VBAR */
    131 
    132 #ifdef __ARM_FIQ_INDIRECT
    133 	.data
    134 	.align	0
    135 _C_LABEL(fiqvector):
    136 	subs	pc, lr, #4
    137 	.org	_C_LABEL(fiqvector) + 0x100
    138 #endif
    139