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arm11_pmc.c revision 1.2.2.1
      1  1.2.2.1  wrstuden /*	$NetBSD: arm11_pmc.c,v 1.2.2.1 2008/09/18 04:33:18 wrstuden Exp $	*/
      2      1.2      matt 
      3      1.2      matt /* Copyright (c) 2007 Microsoft
      4      1.2      matt  * All rights reserved.
      5      1.2      matt  *
      6      1.2      matt  * Redistribution and use in source and binary forms, with or without
      7      1.2      matt  * modification, are permitted provided that the following conditions
      8      1.2      matt  * are met:
      9      1.2      matt  * 1. Redistributions of source code must retain the above copyright
     10      1.2      matt  *    notice, this list of conditions and the following disclaimer.
     11      1.2      matt  * 2. Redistributions in binary form must reproduce the above copyright
     12      1.2      matt  *    notice, this list of conditions and the following disclaimer in the
     13      1.2      matt  *    documentation and/or other materials provided with the distribution.
     14      1.2      matt  * 3. All advertising materials mentioning features or use of this software
     15      1.2      matt  *    must display the following acknowledgement:
     16      1.2      matt  *	This product includes software developed by Microsoft
     17      1.2      matt  *
     18      1.2      matt  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     19      1.2      matt  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20      1.2      matt  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21      1.2      matt  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     22      1.2      matt  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23      1.2      matt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24      1.2      matt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25      1.2      matt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26      1.2      matt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27      1.2      matt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28      1.2      matt  * POSSIBILITY OF SUCH DAMAGE.
     29      1.2      matt  */
     30      1.2      matt 
     31      1.2      matt 
     32      1.2      matt /*
     33      1.2      matt  * support for ARM 11 Performance Monitor Counters
     34      1.2      matt  */
     35      1.2      matt 
     36      1.2      matt #include <sys/cdefs.h>
     37  1.2.2.1  wrstuden __KERNEL_RCSID(0, "$NetBSD: arm11_pmc.c,v 1.2.2.1 2008/09/18 04:33:18 wrstuden Exp $");
     38      1.2      matt #include "opt_perfctrs.h"
     39      1.2      matt #include <sys/types.h>
     40      1.2      matt #include <sys/param.h>
     41      1.2      matt #include <sys/systm.h>
     42      1.2      matt #include <sys/kernel.h>
     43      1.2      matt #include <sys/time.h>
     44      1.2      matt #include <sys/timetc.h>
     45      1.2      matt #include <dev/clock_subr.h>
     46      1.2      matt #include <arm/armreg.h>
     47      1.2      matt #include <arm/cpufunc.h>
     48      1.2      matt 
     49      1.2      matt #ifndef ARM11_PMC_CCNT_HZ
     50      1.2      matt # define ARM11_PMC_CCNT_HZ	400000000	/* 400MHz */
     51      1.2      matt #endif
     52      1.2      matt 
     53      1.2      matt void arm11_pmc_ccnt_init(void);
     54      1.2      matt 
     55      1.2      matt #define COUNTS_PER_USEC	(ARM11_PMC_CCNT_HZ / 1000000)
     56      1.2      matt 
     57      1.2      matt static uint32_t counts_per_wrap = ~0UL;		/* XXX off by 1 */
     58      1.2      matt 
     59      1.2      matt static inline uint32_t
     60      1.2      matt arm11_pmc_ctrl_read(void)
     61      1.2      matt {
     62      1.2      matt 	uint32_t val;
     63      1.2      matt 
     64      1.2      matt 	__asm volatile ("mrc p15, 0, %0, c15, c12, 0" : "=r" (val));
     65      1.2      matt 
     66      1.2      matt 	return val;
     67      1.2      matt }
     68      1.2      matt 
     69      1.2      matt static inline void
     70      1.2      matt arm11_pmc_ctrl_write(uint32_t val)
     71      1.2      matt {
     72      1.2      matt 	__asm volatile ("mcr p15, 0, %0, c15, c12, 0" :: "r" (val));
     73      1.2      matt }
     74      1.2      matt 
     75      1.2      matt static inline uint32_t
     76      1.2      matt arm11_pmc_ccnt_read(void)
     77      1.2      matt {
     78      1.2      matt 	uint32_t val;
     79      1.2      matt 
     80      1.2      matt 	__asm volatile ("mrc p15, 0, %0, c15, c12, 1" : "=r" (val));
     81      1.2      matt 
     82      1.2      matt 	return val;
     83      1.2      matt }
     84      1.2      matt 
     85      1.2      matt static inline void
     86      1.2      matt arm11_pmc_ccnt_write(uint32_t val)
     87      1.2      matt {
     88      1.2      matt 	__asm volatile ("mcr p15, 0, %0, c15, c12, 1;" :: "r" (val));
     89      1.2      matt }
     90      1.2      matt 
     91      1.2      matt /*
     92      1.2      matt  * enable the PMC CCNT for delay()
     93      1.2      matt  */
     94      1.2      matt void
     95      1.2      matt arm11_pmc_ccnt_init(void)
     96      1.2      matt {
     97      1.2      matt 	uint32_t val;
     98      1.2      matt 
     99      1.2      matt 	val = ARM11_PMCCTL_E | ARM11_PMCCTL_P | ARM11_PMCCTL_C;
    100      1.2      matt 
    101      1.2      matt 	arm11_pmc_ctrl_write(val);
    102      1.2      matt }
    103      1.2      matt 
    104      1.2      matt /*
    105      1.2      matt  * delay - for "at least" arg usec
    106      1.2      matt  *
    107      1.2      matt  *	NOTE: at 400MHz we are restricted to (uint32_t)~0 "counts"
    108      1.2      matt  *	if this is a problem, accumulate counts in LL vars
    109      1.2      matt  */
    110      1.2      matt #define DELAY_ARG_LIMIT (((uint32_t)~0) / COUNTS_PER_USEC)	/* about 10 sec */
    111      1.2      matt void
    112      1.2      matt delay(u_int arg)
    113      1.2      matt {
    114      1.2      matt 	uint32_t ctrl;
    115      1.2      matt 	uint32_t cur;
    116      1.2      matt 	uint32_t last;
    117      1.2      matt 	uint32_t delta = 0;
    118      1.2      matt 	uint32_t usecs = 0;
    119      1.2      matt 
    120      1.2      matt 	if (arg > DELAY_ARG_LIMIT)
    121      1.2      matt 		panic("delay: arg %u overflow, limit is %d usec\n", arg, DELAY_ARG_LIMIT);
    122      1.2      matt 
    123      1.2      matt 	last = arm11_pmc_ccnt_read();
    124      1.2      matt 	delta = usecs = 0;
    125      1.2      matt 
    126      1.2      matt 	while (arg > usecs) {
    127      1.2      matt 		cur  = arm11_pmc_ccnt_read();
    128      1.2      matt 		ctrl = arm11_pmc_ctrl_read();
    129      1.2      matt 		if (ctrl & ARM11_PMCCTL_CCR) {
    130      1.2      matt 			/*
    131      1.2      matt 			 * reset CCR, do not reset other write-to-clear flags;
    132  1.2.2.1  wrstuden 			 * keep the rest of the PMC Control Reg configuration
    133      1.2      matt 			 */
    134      1.2      matt 			ctrl &= ~(ARM11_PMCCTL_CR0|ARM11_PMCCTL_CR1);
    135      1.2      matt 			arm11_pmc_ctrl_write(ctrl);
    136      1.2      matt 			delta += (last + (counts_per_wrap - cur));
    137      1.2      matt 		} else {
    138  1.2.2.1  wrstuden 			delta += (cur - last);
    139      1.2      matt 		}
    140      1.2      matt 		last = cur;
    141      1.2      matt 		if (delta >= COUNTS_PER_USEC) {
    142      1.2      matt 			usecs += delta / COUNTS_PER_USEC;
    143      1.2      matt 			delta %= COUNTS_PER_USEC;
    144      1.2      matt 		}
    145      1.2      matt 	}
    146      1.2      matt }
    147