arm32_machdep.c revision 1.123
1 /* $NetBSD: arm32_machdep.c,v 1.123 2018/10/18 09:01:52 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * Machine dependent functions for kernel setup 39 * 40 * Created : 17/09/94 41 * Updated : 18/04/01 updated for new wscons 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.123 2018/10/18 09:01:52 skrll Exp $"); 46 47 #include "opt_arm_debug.h" 48 #include "opt_arm_start.h" 49 #include "opt_fdt.h" 50 #include "opt_modular.h" 51 #include "opt_md.h" 52 #include "opt_multiprocessor.h" 53 #include "opt_pmap_debug.h" 54 55 #include <sys/param.h> 56 #include <sys/atomic.h> 57 #include <sys/systm.h> 58 #include <sys/reboot.h> 59 #include <sys/proc.h> 60 #include <sys/kauth.h> 61 #include <sys/kernel.h> 62 #include <sys/mbuf.h> 63 #include <sys/mount.h> 64 #include <sys/buf.h> 65 #include <sys/msgbuf.h> 66 #include <sys/device.h> 67 #include <sys/sysctl.h> 68 #include <sys/cpu.h> 69 #include <sys/intr.h> 70 #include <sys/module.h> 71 #include <sys/atomic.h> 72 #include <sys/xcall.h> 73 #include <sys/ipi.h> 74 75 #include <uvm/uvm_extern.h> 76 77 #include <dev/cons.h> 78 #include <dev/mm.h> 79 80 #include <arm/locore.h> 81 82 #include <arm/arm32/machdep.h> 83 84 #include <machine/bootconfig.h> 85 #include <machine/pcb.h> 86 87 #if defined(FDT) 88 #include <arm/fdt/arm_fdtvar.h> 89 #include <arch/evbarm/fdt/platform.h> 90 #endif 91 92 #ifdef VERBOSE_INIT_ARM 93 void generic_prints(const char *); 94 void generic_printx(int); 95 #define VPRINTF(...) printf(__VA_ARGS__) 96 #define VPRINTS(s) generic_prints(s) 97 #define VPRINTX(x) generic_printx(x) 98 #else 99 #define VPRINTF(...) __nothing 100 #define VPRINTS(s) __nothing 101 #define VPRINTX(x) __nothing 102 #endif 103 104 void (*cpu_reset_address)(void); /* Used by locore */ 105 paddr_t cpu_reset_address_paddr; /* Used by locore */ 106 107 struct vm_map *phys_map = NULL; 108 109 #if defined(MEMORY_DISK_HOOKS) && !defined(MEMORY_DISK_ROOT_SIZE) 110 extern size_t md_root_size; /* Memory disc size */ 111 #endif /* MEMORY_DISK_HOOKS && !MEMORY_DISK_ROOT_SIZE */ 112 113 pv_addr_t kernelstack; 114 pv_addr_t abtstack; 115 pv_addr_t fiqstack; 116 pv_addr_t irqstack; 117 pv_addr_t undstack; 118 pv_addr_t idlestack; 119 120 void * msgbufaddr; 121 extern paddr_t msgbufphys; 122 123 int kernel_debug = 0; 124 int cpu_printfataltraps = 0; 125 int cpu_fpu_present; 126 int cpu_hwdiv_present; 127 int cpu_neon_present; 128 int cpu_simd_present; 129 int cpu_simdex_present; 130 int cpu_umull_present; 131 int cpu_synchprim_present; 132 int cpu_unaligned_sigbus; 133 const char *cpu_arch = ""; 134 135 int cpu_instruction_set_attributes[6]; 136 int cpu_memory_model_features[4]; 137 int cpu_processor_features[2]; 138 int cpu_media_and_vfp_features[2]; 139 140 /* exported variable to be filled in by the bootloaders */ 141 char *booted_kernel; 142 143 /* Prototypes */ 144 145 void data_abort_handler(trapframe_t *frame); 146 void prefetch_abort_handler(trapframe_t *frame); 147 extern void configure(void); 148 149 /* 150 * arm32_vector_init: 151 * 152 * Initialize the vector page, and select whether or not to 153 * relocate the vectors. 154 * 155 * NOTE: We expect the vector page to be mapped at its expected 156 * destination. 157 */ 158 void 159 arm32_vector_init(vaddr_t va, int which) 160 { 161 #if defined(CPU_ARMV7) || defined(CPU_ARM11) || defined(ARM_HAS_VBAR) 162 /* 163 * If this processor has the security extension, don't bother 164 * to move/map the vector page. Simply point VBAR to the copy 165 * that exists in the .text segment. 166 */ 167 #ifndef ARM_HAS_VBAR 168 if (va == ARM_VECTORS_LOW 169 && (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0) { 170 #endif 171 extern const uint32_t page0rel[]; 172 vector_page = (vaddr_t)page0rel; 173 KASSERT((vector_page & 0x1f) == 0); 174 armreg_vbar_write(vector_page); 175 VPRINTF(" vbar=%p", page0rel); 176 cpu_control(CPU_CONTROL_VECRELOC, 0); 177 return; 178 #ifndef ARM_HAS_VBAR 179 } 180 #endif 181 #endif 182 #ifndef ARM_HAS_VBAR 183 if (CPU_IS_PRIMARY(curcpu())) { 184 extern unsigned int page0[], page0_data[]; 185 unsigned int *vectors = (int *) va; 186 unsigned int *vectors_data = vectors + (page0_data - page0); 187 int vec; 188 189 /* 190 * Loop through the vectors we're taking over, and copy the 191 * vector's insn and data word. 192 */ 193 for (vec = 0; vec < ARM_NVEC; vec++) { 194 if ((which & (1 << vec)) == 0) { 195 /* Don't want to take over this vector. */ 196 continue; 197 } 198 vectors[vec] = page0[vec]; 199 vectors_data[vec] = page0_data[vec]; 200 } 201 202 /* Now sync the vectors. */ 203 cpu_icache_sync_range(va, (ARM_NVEC * 2) * sizeof(u_int)); 204 205 vector_page = va; 206 } 207 208 if (va == ARM_VECTORS_HIGH) { 209 /* 210 * Assume the MD caller knows what it's doing here, and 211 * really does want the vector page relocated. 212 * 213 * Note: This has to be done here (and not just in 214 * cpu_setup()) because the vector page needs to be 215 * accessible *before* cpu_startup() is called. 216 * Think ddb(9) ... 217 * 218 * NOTE: If the CPU control register is not readable, 219 * this will totally fail! We'll just assume that 220 * any system that has high vector support has a 221 * readable CPU control register, for now. If we 222 * ever encounter one that does not, we'll have to 223 * rethink this. 224 */ 225 cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC); 226 } 227 #endif 228 } 229 230 /* 231 * Debug function just to park the CPU 232 */ 233 234 void 235 halt(void) 236 { 237 while (1) 238 cpu_sleep(0); 239 } 240 241 242 /* Sync the discs, unmount the filesystems, and adjust the todr */ 243 244 void 245 bootsync(void) 246 { 247 static bool bootsyncdone = false; 248 249 if (bootsyncdone) return; 250 251 bootsyncdone = true; 252 253 /* Make sure we can still manage to do things */ 254 if (GetCPSR() & I32_bit) { 255 /* 256 * If we get here then boot has been called without RB_NOSYNC 257 * and interrupts were disabled. This means the boot() call 258 * did not come from a user process e.g. shutdown, but must 259 * have come from somewhere in the kernel. 260 */ 261 IRQenable; 262 printf("Warning IRQ's disabled during boot()\n"); 263 } 264 265 vfs_shutdown(); 266 267 resettodr(); 268 } 269 270 /* 271 * void cpu_startup(void) 272 * 273 * Machine dependent startup code. 274 * 275 */ 276 void 277 cpu_startup(void) 278 { 279 vaddr_t minaddr; 280 vaddr_t maxaddr; 281 282 #ifndef __HAVE_GENERIC_START 283 /* Set the CPU control register */ 284 cpu_setup(boot_args); 285 #endif 286 287 #ifndef ARM_HAS_VBAR 288 /* Lock down zero page */ 289 vector_page_setprot(VM_PROT_READ); 290 #endif 291 292 /* 293 * Give pmap a chance to set up a few more things now the vm 294 * is initialised 295 */ 296 pmap_postinit(); 297 298 #ifdef FDT 299 if (arm_fdt_platform()->ap_startup != NULL) 300 arm_fdt_platform()->ap_startup(); 301 #endif 302 303 /* 304 * Initialize error message buffer (at end of core). 305 */ 306 307 /* msgbufphys was setup during the secondary boot strap */ 308 if (!pmap_extract(pmap_kernel(), (vaddr_t)msgbufaddr, NULL)) { 309 for (u_int loop = 0; loop < btoc(MSGBUFSIZE); ++loop) { 310 pmap_kenter_pa((vaddr_t)msgbufaddr + loop * PAGE_SIZE, 311 msgbufphys + loop * PAGE_SIZE, 312 VM_PROT_READ|VM_PROT_WRITE, 0); 313 } 314 } 315 pmap_update(pmap_kernel()); 316 initmsgbuf(msgbufaddr, round_page(MSGBUFSIZE)); 317 318 /* 319 * Allocate a submap for physio 320 */ 321 minaddr = 0; 322 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 323 VM_PHYS_SIZE, 0, false, NULL); 324 325 banner(); 326 327 /* 328 * This is actually done by initarm_common, but not all ports use it 329 * yet so do it here to catch them as well 330 */ 331 struct lwp * const l = &lwp0; 332 struct pcb * const pcb = lwp_getpcb(l); 333 334 /* Zero out the PCB. */ 335 memset(pcb, 0, sizeof(*pcb)); 336 337 pcb->pcb_ksp = uvm_lwp_getuarea(l) + USPACE_SVC_STACK_TOP; 338 pcb->pcb_ksp -= sizeof(struct trapframe); 339 340 struct trapframe * tf = (struct trapframe *)pcb->pcb_ksp; 341 342 /* Zero out the trapframe. */ 343 memset(tf, 0, sizeof(*tf)); 344 lwp_settrapframe(l, tf); 345 346 #if defined(__ARMEB__) 347 tf->tf_spsr = PSR_USR32_MODE | (CPU_IS_ARMV7_P() ? PSR_E_BIT : 0); 348 #else 349 tf->tf_spsr = PSR_USR32_MODE; 350 #endif 351 } 352 353 /* 354 * machine dependent system variables. 355 */ 356 static int 357 sysctl_machdep_booted_device(SYSCTLFN_ARGS) 358 { 359 struct sysctlnode node; 360 361 if (booted_device == NULL) 362 return (EOPNOTSUPP); 363 364 node = *rnode; 365 node.sysctl_data = __UNCONST(device_xname(booted_device)); 366 node.sysctl_size = strlen(device_xname(booted_device)) + 1; 367 return (sysctl_lookup(SYSCTLFN_CALL(&node))); 368 } 369 370 static int 371 sysctl_machdep_booted_kernel(SYSCTLFN_ARGS) 372 { 373 struct sysctlnode node; 374 375 if (booted_kernel == NULL || booted_kernel[0] == '\0') 376 return (EOPNOTSUPP); 377 378 node = *rnode; 379 node.sysctl_data = booted_kernel; 380 node.sysctl_size = strlen(booted_kernel) + 1; 381 return (sysctl_lookup(SYSCTLFN_CALL(&node))); 382 } 383 384 static int 385 sysctl_machdep_cpu_arch(SYSCTLFN_ARGS) 386 { 387 struct sysctlnode node = *rnode; 388 node.sysctl_data = __UNCONST(cpu_arch); 389 node.sysctl_size = strlen(cpu_arch) + 1; 390 return sysctl_lookup(SYSCTLFN_CALL(&node)); 391 } 392 393 static int 394 sysctl_machdep_powersave(SYSCTLFN_ARGS) 395 { 396 struct sysctlnode node = *rnode; 397 int error, newval; 398 399 newval = cpu_do_powersave; 400 node.sysctl_data = &newval; 401 if (cpufuncs.cf_sleep == (void *) cpufunc_nullop) 402 node.sysctl_flags &= ~CTLFLAG_READWRITE; 403 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 404 if (error || newp == NULL || newval == cpu_do_powersave) 405 return (error); 406 407 if (newval < 0 || newval > 1) 408 return (EINVAL); 409 cpu_do_powersave = newval; 410 411 return (0); 412 } 413 414 SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup") 415 { 416 417 sysctl_createv(clog, 0, NULL, NULL, 418 CTLFLAG_PERMANENT, 419 CTLTYPE_NODE, "machdep", NULL, 420 NULL, 0, NULL, 0, 421 CTL_MACHDEP, CTL_EOL); 422 423 sysctl_createv(clog, 0, NULL, NULL, 424 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 425 CTLTYPE_INT, "debug", NULL, 426 NULL, 0, &kernel_debug, 0, 427 CTL_MACHDEP, CPU_DEBUG, CTL_EOL); 428 sysctl_createv(clog, 0, NULL, NULL, 429 CTLFLAG_PERMANENT, 430 CTLTYPE_STRING, "booted_device", NULL, 431 sysctl_machdep_booted_device, 0, NULL, 0, 432 CTL_MACHDEP, CPU_BOOTED_DEVICE, CTL_EOL); 433 sysctl_createv(clog, 0, NULL, NULL, 434 CTLFLAG_PERMANENT, 435 CTLTYPE_STRING, "booted_kernel", NULL, 436 sysctl_machdep_booted_kernel, 0, NULL, 0, 437 CTL_MACHDEP, CPU_BOOTED_KERNEL, CTL_EOL); 438 sysctl_createv(clog, 0, NULL, NULL, 439 CTLFLAG_PERMANENT, 440 CTLTYPE_STRUCT, "console_device", NULL, 441 sysctl_consdev, 0, NULL, sizeof(dev_t), 442 CTL_MACHDEP, CPU_CONSDEV, CTL_EOL); 443 sysctl_createv(clog, 0, NULL, NULL, 444 CTLFLAG_PERMANENT, 445 CTLTYPE_STRING, "cpu_arch", NULL, 446 sysctl_machdep_cpu_arch, 0, NULL, 0, 447 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 448 sysctl_createv(clog, 0, NULL, NULL, 449 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 450 CTLTYPE_INT, "powersave", NULL, 451 sysctl_machdep_powersave, 0, &cpu_do_powersave, 0, 452 CTL_MACHDEP, CPU_POWERSAVE, CTL_EOL); 453 sysctl_createv(clog, 0, NULL, NULL, 454 CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE, 455 CTLTYPE_INT, "cpu_id", NULL, 456 NULL, curcpu()->ci_arm_cpuid, NULL, 0, 457 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 458 #ifdef FPU_VFP 459 sysctl_createv(clog, 0, NULL, NULL, 460 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 461 CTLTYPE_INT, "fpu_id", NULL, 462 NULL, 0, &cpu_info_store.ci_vfp_id, 0, 463 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 464 #endif 465 sysctl_createv(clog, 0, NULL, NULL, 466 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 467 CTLTYPE_INT, "fpu_present", NULL, 468 NULL, 0, &cpu_fpu_present, 0, 469 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 470 sysctl_createv(clog, 0, NULL, NULL, 471 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 472 CTLTYPE_INT, "hwdiv_present", NULL, 473 NULL, 0, &cpu_hwdiv_present, 0, 474 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 475 sysctl_createv(clog, 0, NULL, NULL, 476 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 477 CTLTYPE_INT, "neon_present", NULL, 478 NULL, 0, &cpu_neon_present, 0, 479 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 480 sysctl_createv(clog, 0, NULL, NULL, 481 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 482 CTLTYPE_STRUCT, "id_isar", NULL, 483 NULL, 0, 484 cpu_instruction_set_attributes, 485 sizeof(cpu_instruction_set_attributes), 486 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 487 sysctl_createv(clog, 0, NULL, NULL, 488 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 489 CTLTYPE_STRUCT, "id_mmfr", NULL, 490 NULL, 0, 491 cpu_memory_model_features, 492 sizeof(cpu_memory_model_features), 493 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 494 sysctl_createv(clog, 0, NULL, NULL, 495 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 496 CTLTYPE_STRUCT, "id_pfr", NULL, 497 NULL, 0, 498 cpu_processor_features, 499 sizeof(cpu_processor_features), 500 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 501 sysctl_createv(clog, 0, NULL, NULL, 502 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 503 CTLTYPE_STRUCT, "id_mvfr", NULL, 504 NULL, 0, 505 cpu_media_and_vfp_features, 506 sizeof(cpu_media_and_vfp_features), 507 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 508 sysctl_createv(clog, 0, NULL, NULL, 509 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 510 CTLTYPE_INT, "simd_present", NULL, 511 NULL, 0, &cpu_simd_present, 0, 512 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 513 sysctl_createv(clog, 0, NULL, NULL, 514 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 515 CTLTYPE_INT, "simdex_present", NULL, 516 NULL, 0, &cpu_simdex_present, 0, 517 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 518 sysctl_createv(clog, 0, NULL, NULL, 519 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 520 CTLTYPE_INT, "synchprim_present", NULL, 521 NULL, 0, &cpu_synchprim_present, 0, 522 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 523 sysctl_createv(clog, 0, NULL, NULL, 524 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 525 CTLTYPE_INT, "printfataltraps", NULL, 526 NULL, 0, &cpu_printfataltraps, 0, 527 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 528 cpu_unaligned_sigbus = !CPU_IS_ARMV6_P() && !CPU_IS_ARMV7_P(); 529 sysctl_createv(clog, 0, NULL, NULL, 530 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 531 CTLTYPE_INT, "unaligned_sigbus", 532 SYSCTL_DESCR("Do SIGBUS for fixed unaligned accesses"), 533 NULL, 0, &cpu_unaligned_sigbus, 0, 534 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 535 } 536 537 void 538 parse_mi_bootargs(char *args) 539 { 540 int integer; 541 542 if (get_bootconf_option(args, "single", BOOTOPT_TYPE_BOOLEAN, &integer) 543 || get_bootconf_option(args, "-s", BOOTOPT_TYPE_BOOLEAN, &integer)) 544 if (integer) 545 boothowto |= RB_SINGLE; 546 if (get_bootconf_option(args, "kdb", BOOTOPT_TYPE_BOOLEAN, &integer) 547 || get_bootconf_option(args, "-k", BOOTOPT_TYPE_BOOLEAN, &integer) 548 || get_bootconf_option(args, "-d", BOOTOPT_TYPE_BOOLEAN, &integer)) 549 if (integer) 550 boothowto |= RB_KDB; 551 if (get_bootconf_option(args, "ask", BOOTOPT_TYPE_BOOLEAN, &integer) 552 || get_bootconf_option(args, "-a", BOOTOPT_TYPE_BOOLEAN, &integer)) 553 if (integer) 554 boothowto |= RB_ASKNAME; 555 556 #ifdef PMAP_DEBUG 557 if (get_bootconf_option(args, "pmapdebug", BOOTOPT_TYPE_INT, &integer)) { 558 pmap_debug_level = integer; 559 pmap_debug(pmap_debug_level); 560 } 561 #endif /* PMAP_DEBUG */ 562 563 /* if (get_bootconf_option(args, "nbuf", BOOTOPT_TYPE_INT, &integer)) 564 bufpages = integer;*/ 565 566 #if defined(MEMORY_DISK_HOOKS) && !defined(MEMORY_DISK_ROOT_SIZE) 567 if (get_bootconf_option(args, "memorydisc", BOOTOPT_TYPE_INT, &integer) 568 || get_bootconf_option(args, "memorydisk", BOOTOPT_TYPE_INT, &integer)) { 569 md_root_size = integer; 570 md_root_size *= 1024; 571 if (md_root_size < 32*1024) 572 md_root_size = 32*1024; 573 if (md_root_size > 2048*1024) 574 md_root_size = 2048*1024; 575 } 576 #endif /* MEMORY_DISK_HOOKS && !MEMORY_DISK_ROOT_SIZE */ 577 578 if (get_bootconf_option(args, "quiet", BOOTOPT_TYPE_BOOLEAN, &integer) 579 || get_bootconf_option(args, "-q", BOOTOPT_TYPE_BOOLEAN, &integer)) 580 if (integer) 581 boothowto |= AB_QUIET; 582 if (get_bootconf_option(args, "verbose", BOOTOPT_TYPE_BOOLEAN, &integer) 583 || get_bootconf_option(args, "-v", BOOTOPT_TYPE_BOOLEAN, &integer)) 584 if (integer) 585 boothowto |= AB_VERBOSE; 586 if (get_bootconf_option(args, "debug", BOOTOPT_TYPE_BOOLEAN, &integer) 587 || get_bootconf_option(args, "-x", BOOTOPT_TYPE_BOOLEAN, &integer)) 588 if (integer) 589 boothowto |= AB_DEBUG; 590 } 591 592 #ifdef __HAVE_FAST_SOFTINTS 593 #if IPL_SOFTSERIAL != IPL_SOFTNET + 1 594 #error IPLs are screwed up 595 #elif IPL_SOFTNET != IPL_SOFTBIO + 1 596 #error IPLs are screwed up 597 #elif IPL_SOFTBIO != IPL_SOFTCLOCK + 1 598 #error IPLs are screwed up 599 #elif !(IPL_SOFTCLOCK > IPL_NONE) 600 #error IPLs are screwed up 601 #elif (IPL_NONE != 0) 602 #error IPLs are screwed up 603 #endif 604 605 #ifndef __HAVE_PIC_FAST_SOFTINTS 606 #define SOFTINT2IPLMAP \ 607 (((IPL_SOFTSERIAL - IPL_SOFTCLOCK) << (SOFTINT_SERIAL * 4)) | \ 608 ((IPL_SOFTNET - IPL_SOFTCLOCK) << (SOFTINT_NET * 4)) | \ 609 ((IPL_SOFTBIO - IPL_SOFTCLOCK) << (SOFTINT_BIO * 4)) | \ 610 ((IPL_SOFTCLOCK - IPL_SOFTCLOCK) << (SOFTINT_CLOCK * 4))) 611 #define SOFTINT2IPL(l) ((SOFTINT2IPLMAP >> ((l) * 4)) & 0x0f) 612 613 /* 614 * This returns a mask of softint IPLs that be dispatch at <ipl> 615 * SOFTIPLMASK(IPL_NONE) = 0x0000000f 616 * SOFTIPLMASK(IPL_SOFTCLOCK) = 0x0000000e 617 * SOFTIPLMASK(IPL_SOFTBIO) = 0x0000000c 618 * SOFTIPLMASK(IPL_SOFTNET) = 0x00000008 619 * SOFTIPLMASK(IPL_SOFTSERIAL) = 0x00000000 620 */ 621 #define SOFTIPLMASK(ipl) ((0x0f << (ipl)) & 0x0f) 622 623 void softint_switch(lwp_t *, int); 624 625 void 626 softint_trigger(uintptr_t mask) 627 { 628 curcpu()->ci_softints |= mask; 629 } 630 631 void 632 softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep) 633 { 634 lwp_t ** lp = &l->l_cpu->ci_softlwps[level]; 635 KASSERT(*lp == NULL || *lp == l); 636 *lp = l; 637 *machdep = 1 << SOFTINT2IPL(level); 638 KASSERT(level != SOFTINT_CLOCK || *machdep == (1 << (IPL_SOFTCLOCK - IPL_SOFTCLOCK))); 639 KASSERT(level != SOFTINT_BIO || *machdep == (1 << (IPL_SOFTBIO - IPL_SOFTCLOCK))); 640 KASSERT(level != SOFTINT_NET || *machdep == (1 << (IPL_SOFTNET - IPL_SOFTCLOCK))); 641 KASSERT(level != SOFTINT_SERIAL || *machdep == (1 << (IPL_SOFTSERIAL - IPL_SOFTCLOCK))); 642 } 643 644 void 645 dosoftints(void) 646 { 647 struct cpu_info * const ci = curcpu(); 648 const int opl = ci->ci_cpl; 649 const uint32_t softiplmask = SOFTIPLMASK(opl); 650 651 splhigh(); 652 for (;;) { 653 u_int softints = ci->ci_softints & softiplmask; 654 KASSERT((softints != 0) == ((ci->ci_softints >> opl) != 0)); 655 KASSERT(opl == IPL_NONE || (softints & (1 << (opl - IPL_SOFTCLOCK))) == 0); 656 if (softints == 0) { 657 splx(opl); 658 return; 659 } 660 #define DOSOFTINT(n) \ 661 if (ci->ci_softints & (1 << (IPL_SOFT ## n - IPL_SOFTCLOCK))) { \ 662 ci->ci_softints &= \ 663 ~(1 << (IPL_SOFT ## n - IPL_SOFTCLOCK)); \ 664 softint_switch(ci->ci_softlwps[SOFTINT_ ## n], \ 665 IPL_SOFT ## n); \ 666 continue; \ 667 } 668 DOSOFTINT(SERIAL); 669 DOSOFTINT(NET); 670 DOSOFTINT(BIO); 671 DOSOFTINT(CLOCK); 672 panic("dosoftints wtf (softints=%u?, ipl=%d)", softints, opl); 673 } 674 } 675 #endif /* !__HAVE_PIC_FAST_SOFTINTS */ 676 #endif /* __HAVE_FAST_SOFTINTS */ 677 678 #ifdef MODULAR 679 /* 680 * Push any modules loaded by the boot loader. 681 */ 682 void 683 module_init_md(void) 684 { 685 } 686 #endif /* MODULAR */ 687 688 int 689 mm_md_physacc(paddr_t pa, vm_prot_t prot) 690 { 691 if (pa >= physical_start && pa < physical_end) 692 return 0; 693 694 return kauth_authorize_machdep(kauth_cred_get(), 695 KAUTH_MACHDEP_UNMANAGEDMEM, NULL, NULL, NULL, NULL); 696 } 697 698 #ifdef __HAVE_CPU_UAREA_ALLOC_IDLELWP 699 vaddr_t 700 cpu_uarea_alloc_idlelwp(struct cpu_info *ci) 701 { 702 const vaddr_t va = idlestack.pv_va + ci->ci_cpuid * USPACE; 703 // printf("%s: %s: va=%lx\n", __func__, ci->ci_data.cpu_name, va); 704 return va; 705 } 706 #endif 707 708 #ifdef MULTIPROCESSOR 709 /* 710 * Initialise a secondary processor. 711 * 712 * printf isn't available to us for a number of reasons. 713 * 714 * - kprint_init has been called and printf will try to take locks which we can't 715 * do just yet because bootstrap translation tables do not allowing caching. 716 * 717 * - kmutex(9) relies on curcpu which isn't setup yet. 718 * 719 */ 720 void 721 cpu_init_secondary_processor(int cpuno) 722 { 723 // pmap_kernel has been sucessfully built and we can switch to it 724 725 cpu_domains(DOMAIN_DEFAULT); 726 cpu_idcache_wbinv_all(); 727 728 VPRINTS(" ttb"); 729 730 cpu_setup(boot_args); 731 732 #ifdef ARM_MMU_EXTENDED 733 /* 734 * TTBCR should have been initialized by the MD start code. 735 */ 736 KASSERT((armreg_contextidr_read() & 0xff) == 0); 737 KASSERT(armreg_ttbcr_read() == __SHIFTIN(1, TTBCR_S_N)); 738 /* 739 * Disable lookups via TTBR0 until there is an activated pmap. 740 */ 741 742 armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0); 743 cpu_setttb(pmap_kernel()->pm_l1_pa , KERNEL_PID); 744 arm_isb(); 745 #else 746 cpu_setttb(pmap_kernel()->pm_l1->l1_physaddr, true); 747 #endif 748 749 cpu_tlb_flushID(); 750 751 VPRINTS(" (TTBR0="); 752 VPRINTX(armreg_ttbr_read()); 753 VPRINTS(")"); 754 755 #ifdef ARM_MMU_EXTENDED 756 VPRINTS(" (TTBR1="); 757 VPRINTX(armreg_ttbr1_read()); 758 VPRINTS(")"); 759 VPRINTS(" (TTBCR="); 760 VPRINTX(armreg_ttbcr_read()); 761 #endif 762 763 atomic_or_uint(&arm_cpu_hatched, __BIT(cpuno)); 764 765 /* return to assembly to Wait for cpu_boot_secondary_processors */ 766 } 767 768 void 769 cpu_boot_secondary_processors(void) 770 { 771 VPRINTF("%s: writing mbox with %#x\n", __func__, arm_cpu_hatched); 772 arm_cpu_mbox = arm_cpu_hatched; 773 membar_producer(); 774 #ifdef _ARM_ARCH_7 775 __asm __volatile("sev; sev; sev"); 776 #endif 777 while (membar_consumer(), arm_cpu_mbox) { 778 __asm __volatile("wfe" ::: "memory"); 779 } 780 } 781 782 void 783 xc_send_ipi(struct cpu_info *ci) 784 { 785 KASSERT(kpreempt_disabled()); 786 KASSERT(curcpu() != ci); 787 788 intr_ipi_send(ci != NULL ? ci->ci_kcpuset : NULL, IPI_XCALL); 789 } 790 791 void 792 cpu_ipi(struct cpu_info *ci) 793 { 794 KASSERT(kpreempt_disabled()); 795 KASSERT(curcpu() != ci); 796 797 intr_ipi_send(ci != NULL ? ci->ci_kcpuset : NULL, IPI_GENERIC); 798 } 799 800 #endif /* MULTIPROCESSOR */ 801 802 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 803 bool 804 mm_md_direct_mapped_phys(paddr_t pa, vaddr_t *vap) 805 { 806 bool rv; 807 vaddr_t va = pmap_direct_mapped_phys(pa, &rv, 0); 808 if (rv) { 809 *vap = va; 810 } 811 return rv; 812 } 813 #endif 814 815 bool 816 mm_md_page_color(paddr_t pa, int *colorp) 817 { 818 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 819 *colorp = atop(pa & arm_cache_prefer_mask); 820 821 return arm_cache_prefer_mask ? false : true; 822 #else 823 *colorp = 0; 824 825 return true; 826 #endif 827 } 828 829 #if defined(FDT) 830 extern char KERNEL_BASE_phys[]; 831 #define KERNEL_BASE_PHYS ((paddr_t)KERNEL_BASE_phys) 832 833 void 834 cpu_kernel_vm_init(paddr_t memory_start, psize_t memory_size) 835 { 836 const struct arm_platform *plat = arm_fdt_platform(); 837 838 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 839 const bool mapallmem_p = true; 840 #ifndef PMAP_NEED_ALLOC_POOLPAGE 841 if (memory_size > KERNEL_VM_BASE - KERNEL_BASE) { 842 VPRINTF("%s: dropping RAM size from %luMB to %uMB\n", 843 __func__, (unsigned long) (memory_size >> 20), 844 (KERNEL_VM_BASE - KERNEL_BASE) >> 20); 845 memory_size = KERNEL_VM_BASE - KERNEL_BASE; 846 } 847 #endif 848 #else 849 const bool mapallmem_p = false; 850 #endif 851 852 VPRINTF("%s: kernel phys start %" PRIxPADDR " end %" PRIxPADDR "\n", 853 __func__, memory_start, memory_size); 854 855 arm32_bootmem_init(memory_start, memory_size, KERNEL_BASE_PHYS); 856 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 857 plat->ap_devmap(), mapallmem_p); 858 } 859 #endif 860 861
Indexes created Mon Sep 29 21:09:56 GMT 2025