arm32_machdep.c revision 1.128
1 /* $NetBSD: arm32_machdep.c,v 1.128 2019/05/10 16:43:09 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * Machine dependent functions for kernel setup 39 * 40 * Created : 17/09/94 41 * Updated : 18/04/01 updated for new wscons 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.128 2019/05/10 16:43:09 skrll Exp $"); 46 47 #include "opt_arm_debug.h" 48 #include "opt_arm_start.h" 49 #include "opt_fdt.h" 50 #include "opt_modular.h" 51 #include "opt_md.h" 52 #include "opt_multiprocessor.h" 53 #include "opt_pmap_debug.h" 54 55 #include <sys/param.h> 56 #include <sys/atomic.h> 57 #include <sys/systm.h> 58 #include <sys/reboot.h> 59 #include <sys/proc.h> 60 #include <sys/kauth.h> 61 #include <sys/kernel.h> 62 #include <sys/mbuf.h> 63 #include <sys/mount.h> 64 #include <sys/buf.h> 65 #include <sys/msgbuf.h> 66 #include <sys/device.h> 67 #include <sys/sysctl.h> 68 #include <sys/cpu.h> 69 #include <sys/intr.h> 70 #include <sys/module.h> 71 #include <sys/atomic.h> 72 #include <sys/xcall.h> 73 #include <sys/ipi.h> 74 75 #include <uvm/uvm_extern.h> 76 77 #include <dev/cons.h> 78 #include <dev/mm.h> 79 80 #include <arm/locore.h> 81 82 #include <arm/arm32/machdep.h> 83 84 #include <machine/bootconfig.h> 85 #include <machine/pcb.h> 86 87 #if defined(FDT) 88 #include <arm/fdt/arm_fdtvar.h> 89 #include <arch/evbarm/fdt/platform.h> 90 #endif 91 92 #ifdef VERBOSE_INIT_ARM 93 #define VPRINTF(...) printf(__VA_ARGS__) 94 #ifdef __HAVE_GENERIC_START 95 void generic_prints(const char *); 96 void generic_printx(int); 97 #define VPRINTS(s) generic_prints(s) 98 #define VPRINTX(x) generic_printx(x) 99 #else 100 #define VPRINTS(s) __nothing 101 #define VPRINTX(x) __nothing 102 #endif 103 #else 104 #define VPRINTF(...) __nothing 105 #define VPRINTS(s) __nothing 106 #define VPRINTX(x) __nothing 107 #endif 108 109 void (*cpu_reset_address)(void); /* Used by locore */ 110 paddr_t cpu_reset_address_paddr; /* Used by locore */ 111 112 struct vm_map *phys_map = NULL; 113 114 #if defined(MEMORY_DISK_HOOKS) && !defined(MEMORY_DISK_ROOT_SIZE) 115 extern size_t md_root_size; /* Memory disc size */ 116 #endif /* MEMORY_DISK_HOOKS && !MEMORY_DISK_ROOT_SIZE */ 117 118 pv_addr_t kernelstack; 119 pv_addr_t abtstack; 120 pv_addr_t fiqstack; 121 pv_addr_t irqstack; 122 pv_addr_t undstack; 123 pv_addr_t idlestack; 124 125 void * msgbufaddr; 126 extern paddr_t msgbufphys; 127 128 int kernel_debug = 0; 129 int cpu_printfataltraps = 0; 130 int cpu_fpu_present; 131 int cpu_hwdiv_present; 132 int cpu_neon_present; 133 int cpu_simd_present; 134 int cpu_simdex_present; 135 int cpu_umull_present; 136 int cpu_synchprim_present; 137 int cpu_unaligned_sigbus; 138 const char *cpu_arch = ""; 139 140 int cpu_instruction_set_attributes[6]; 141 int cpu_memory_model_features[4]; 142 int cpu_processor_features[2]; 143 int cpu_media_and_vfp_features[2]; 144 145 /* exported variable to be filled in by the bootloaders */ 146 char *booted_kernel; 147 148 /* Prototypes */ 149 150 void data_abort_handler(trapframe_t *frame); 151 void prefetch_abort_handler(trapframe_t *frame); 152 extern void configure(void); 153 154 /* 155 * arm32_vector_init: 156 * 157 * Initialize the vector page, and select whether or not to 158 * relocate the vectors. 159 * 160 * NOTE: We expect the vector page to be mapped at its expected 161 * destination. 162 */ 163 void 164 arm32_vector_init(vaddr_t va, int which) 165 { 166 #if defined(CPU_ARMV7) || defined(CPU_ARM11) || defined(ARM_HAS_VBAR) 167 /* 168 * If this processor has the security extension, don't bother 169 * to move/map the vector page. Simply point VBAR to the copy 170 * that exists in the .text segment. 171 */ 172 #ifndef ARM_HAS_VBAR 173 if (va == ARM_VECTORS_LOW 174 && (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0) { 175 #endif 176 extern const uint32_t page0rel[]; 177 vector_page = (vaddr_t)page0rel; 178 KASSERT((vector_page & 0x1f) == 0); 179 armreg_vbar_write(vector_page); 180 VPRINTF(" vbar=%p", page0rel); 181 cpu_control(CPU_CONTROL_VECRELOC, 0); 182 return; 183 #ifndef ARM_HAS_VBAR 184 } 185 #endif 186 #endif 187 #ifndef ARM_HAS_VBAR 188 if (CPU_IS_PRIMARY(curcpu())) { 189 extern unsigned int page0[], page0_data[]; 190 unsigned int *vectors = (int *) va; 191 unsigned int *vectors_data = vectors + (page0_data - page0); 192 int vec; 193 194 /* 195 * Loop through the vectors we're taking over, and copy the 196 * vector's insn and data word. 197 */ 198 for (vec = 0; vec < ARM_NVEC; vec++) { 199 if ((which & (1 << vec)) == 0) { 200 /* Don't want to take over this vector. */ 201 continue; 202 } 203 vectors[vec] = page0[vec]; 204 vectors_data[vec] = page0_data[vec]; 205 } 206 207 /* Now sync the vectors. */ 208 cpu_icache_sync_range(va, (ARM_NVEC * 2) * sizeof(u_int)); 209 210 vector_page = va; 211 } 212 213 if (va == ARM_VECTORS_HIGH) { 214 /* 215 * Assume the MD caller knows what it's doing here, and 216 * really does want the vector page relocated. 217 * 218 * Note: This has to be done here (and not just in 219 * cpu_setup()) because the vector page needs to be 220 * accessible *before* cpu_startup() is called. 221 * Think ddb(9) ... 222 * 223 * NOTE: If the CPU control register is not readable, 224 * this will totally fail! We'll just assume that 225 * any system that has high vector support has a 226 * readable CPU control register, for now. If we 227 * ever encounter one that does not, we'll have to 228 * rethink this. 229 */ 230 cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC); 231 } 232 #endif 233 } 234 235 /* 236 * Debug function just to park the CPU 237 */ 238 239 void 240 halt(void) 241 { 242 while (1) 243 cpu_sleep(0); 244 } 245 246 247 /* Sync the discs, unmount the filesystems, and adjust the todr */ 248 249 void 250 bootsync(void) 251 { 252 static bool bootsyncdone = false; 253 254 if (bootsyncdone) return; 255 256 bootsyncdone = true; 257 258 /* Make sure we can still manage to do things */ 259 if (GetCPSR() & I32_bit) { 260 /* 261 * If we get here then boot has been called without RB_NOSYNC 262 * and interrupts were disabled. This means the boot() call 263 * did not come from a user process e.g. shutdown, but must 264 * have come from somewhere in the kernel. 265 */ 266 IRQenable; 267 printf("Warning IRQ's disabled during boot()\n"); 268 } 269 270 vfs_shutdown(); 271 272 resettodr(); 273 } 274 275 /* 276 * void cpu_startup(void) 277 * 278 * Machine dependent startup code. 279 * 280 */ 281 void 282 cpu_startup(void) 283 { 284 vaddr_t minaddr; 285 vaddr_t maxaddr; 286 287 #ifndef __HAVE_GENERIC_START 288 /* Set the CPU control register */ 289 cpu_setup(boot_args); 290 #endif 291 292 #ifndef ARM_HAS_VBAR 293 /* Lock down zero page */ 294 vector_page_setprot(VM_PROT_READ); 295 #endif 296 297 /* 298 * Give pmap a chance to set up a few more things now the vm 299 * is initialised 300 */ 301 pmap_postinit(); 302 303 #ifdef FDT 304 if (arm_fdt_platform()->ap_startup != NULL) 305 arm_fdt_platform()->ap_startup(); 306 #endif 307 308 /* 309 * Initialize error message buffer (at end of core). 310 */ 311 312 /* msgbufphys was setup during the secondary boot strap */ 313 if (!pmap_extract(pmap_kernel(), (vaddr_t)msgbufaddr, NULL)) { 314 for (u_int loop = 0; loop < btoc(MSGBUFSIZE); ++loop) { 315 pmap_kenter_pa((vaddr_t)msgbufaddr + loop * PAGE_SIZE, 316 msgbufphys + loop * PAGE_SIZE, 317 VM_PROT_READ|VM_PROT_WRITE, 0); 318 } 319 } 320 pmap_update(pmap_kernel()); 321 initmsgbuf(msgbufaddr, round_page(MSGBUFSIZE)); 322 323 /* 324 * Allocate a submap for physio 325 */ 326 minaddr = 0; 327 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 328 VM_PHYS_SIZE, 0, false, NULL); 329 330 banner(); 331 332 /* 333 * This is actually done by initarm_common, but not all ports use it 334 * yet so do it here to catch them as well 335 */ 336 struct lwp * const l = &lwp0; 337 struct pcb * const pcb = lwp_getpcb(l); 338 339 /* Zero out the PCB. */ 340 memset(pcb, 0, sizeof(*pcb)); 341 342 pcb->pcb_ksp = uvm_lwp_getuarea(l) + USPACE_SVC_STACK_TOP; 343 pcb->pcb_ksp -= sizeof(struct trapframe); 344 345 struct trapframe * tf = (struct trapframe *)pcb->pcb_ksp; 346 347 /* Zero out the trapframe. */ 348 memset(tf, 0, sizeof(*tf)); 349 lwp_settrapframe(l, tf); 350 351 #if defined(__ARMEB__) 352 tf->tf_spsr = PSR_USR32_MODE | (CPU_IS_ARMV7_P() ? PSR_E_BIT : 0); 353 #else 354 tf->tf_spsr = PSR_USR32_MODE; 355 #endif 356 } 357 358 /* 359 * machine dependent system variables. 360 */ 361 static int 362 sysctl_machdep_booted_device(SYSCTLFN_ARGS) 363 { 364 struct sysctlnode node; 365 366 if (booted_device == NULL) 367 return (EOPNOTSUPP); 368 369 node = *rnode; 370 node.sysctl_data = __UNCONST(device_xname(booted_device)); 371 node.sysctl_size = strlen(device_xname(booted_device)) + 1; 372 return (sysctl_lookup(SYSCTLFN_CALL(&node))); 373 } 374 375 static int 376 sysctl_machdep_booted_kernel(SYSCTLFN_ARGS) 377 { 378 struct sysctlnode node; 379 380 if (booted_kernel == NULL || booted_kernel[0] == '\0') 381 return (EOPNOTSUPP); 382 383 node = *rnode; 384 node.sysctl_data = booted_kernel; 385 node.sysctl_size = strlen(booted_kernel) + 1; 386 return (sysctl_lookup(SYSCTLFN_CALL(&node))); 387 } 388 389 static int 390 sysctl_machdep_cpu_arch(SYSCTLFN_ARGS) 391 { 392 struct sysctlnode node = *rnode; 393 node.sysctl_data = __UNCONST(cpu_arch); 394 node.sysctl_size = strlen(cpu_arch) + 1; 395 return sysctl_lookup(SYSCTLFN_CALL(&node)); 396 } 397 398 static int 399 sysctl_machdep_powersave(SYSCTLFN_ARGS) 400 { 401 struct sysctlnode node = *rnode; 402 int error, newval; 403 404 newval = cpu_do_powersave; 405 node.sysctl_data = &newval; 406 if (cpufuncs.cf_sleep == (void *) cpufunc_nullop) 407 node.sysctl_flags &= ~CTLFLAG_READWRITE; 408 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 409 if (error || newp == NULL || newval == cpu_do_powersave) 410 return (error); 411 412 if (newval < 0 || newval > 1) 413 return (EINVAL); 414 cpu_do_powersave = newval; 415 416 return (0); 417 } 418 419 SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup") 420 { 421 422 sysctl_createv(clog, 0, NULL, NULL, 423 CTLFLAG_PERMANENT, 424 CTLTYPE_NODE, "machdep", NULL, 425 NULL, 0, NULL, 0, 426 CTL_MACHDEP, CTL_EOL); 427 428 sysctl_createv(clog, 0, NULL, NULL, 429 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 430 CTLTYPE_INT, "debug", NULL, 431 NULL, 0, &kernel_debug, 0, 432 CTL_MACHDEP, CPU_DEBUG, CTL_EOL); 433 sysctl_createv(clog, 0, NULL, NULL, 434 CTLFLAG_PERMANENT, 435 CTLTYPE_STRING, "booted_device", NULL, 436 sysctl_machdep_booted_device, 0, NULL, 0, 437 CTL_MACHDEP, CPU_BOOTED_DEVICE, CTL_EOL); 438 sysctl_createv(clog, 0, NULL, NULL, 439 CTLFLAG_PERMANENT, 440 CTLTYPE_STRING, "booted_kernel", NULL, 441 sysctl_machdep_booted_kernel, 0, NULL, 0, 442 CTL_MACHDEP, CPU_BOOTED_KERNEL, CTL_EOL); 443 sysctl_createv(clog, 0, NULL, NULL, 444 CTLFLAG_PERMANENT, 445 CTLTYPE_STRUCT, "console_device", NULL, 446 sysctl_consdev, 0, NULL, sizeof(dev_t), 447 CTL_MACHDEP, CPU_CONSDEV, CTL_EOL); 448 sysctl_createv(clog, 0, NULL, NULL, 449 CTLFLAG_PERMANENT, 450 CTLTYPE_STRING, "cpu_arch", NULL, 451 sysctl_machdep_cpu_arch, 0, NULL, 0, 452 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 453 sysctl_createv(clog, 0, NULL, NULL, 454 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 455 CTLTYPE_INT, "powersave", NULL, 456 sysctl_machdep_powersave, 0, &cpu_do_powersave, 0, 457 CTL_MACHDEP, CPU_POWERSAVE, CTL_EOL); 458 sysctl_createv(clog, 0, NULL, NULL, 459 CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE, 460 CTLTYPE_INT, "cpu_id", NULL, 461 NULL, curcpu()->ci_arm_cpuid, NULL, 0, 462 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 463 #ifdef FPU_VFP 464 sysctl_createv(clog, 0, NULL, NULL, 465 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 466 CTLTYPE_INT, "fpu_id", NULL, 467 NULL, 0, &cpu_info_store.ci_vfp_id, 0, 468 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 469 #endif 470 sysctl_createv(clog, 0, NULL, NULL, 471 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 472 CTLTYPE_INT, "fpu_present", NULL, 473 NULL, 0, &cpu_fpu_present, 0, 474 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 475 sysctl_createv(clog, 0, NULL, NULL, 476 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 477 CTLTYPE_INT, "hwdiv_present", NULL, 478 NULL, 0, &cpu_hwdiv_present, 0, 479 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 480 sysctl_createv(clog, 0, NULL, NULL, 481 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 482 CTLTYPE_INT, "neon_present", NULL, 483 NULL, 0, &cpu_neon_present, 0, 484 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 485 sysctl_createv(clog, 0, NULL, NULL, 486 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 487 CTLTYPE_STRUCT, "id_isar", NULL, 488 NULL, 0, 489 cpu_instruction_set_attributes, 490 sizeof(cpu_instruction_set_attributes), 491 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 492 sysctl_createv(clog, 0, NULL, NULL, 493 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 494 CTLTYPE_STRUCT, "id_mmfr", NULL, 495 NULL, 0, 496 cpu_memory_model_features, 497 sizeof(cpu_memory_model_features), 498 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 499 sysctl_createv(clog, 0, NULL, NULL, 500 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 501 CTLTYPE_STRUCT, "id_pfr", NULL, 502 NULL, 0, 503 cpu_processor_features, 504 sizeof(cpu_processor_features), 505 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 506 sysctl_createv(clog, 0, NULL, NULL, 507 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 508 CTLTYPE_STRUCT, "id_mvfr", NULL, 509 NULL, 0, 510 cpu_media_and_vfp_features, 511 sizeof(cpu_media_and_vfp_features), 512 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 513 sysctl_createv(clog, 0, NULL, NULL, 514 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 515 CTLTYPE_INT, "simd_present", NULL, 516 NULL, 0, &cpu_simd_present, 0, 517 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 518 sysctl_createv(clog, 0, NULL, NULL, 519 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 520 CTLTYPE_INT, "simdex_present", NULL, 521 NULL, 0, &cpu_simdex_present, 0, 522 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 523 sysctl_createv(clog, 0, NULL, NULL, 524 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 525 CTLTYPE_INT, "synchprim_present", NULL, 526 NULL, 0, &cpu_synchprim_present, 0, 527 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 528 sysctl_createv(clog, 0, NULL, NULL, 529 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 530 CTLTYPE_INT, "printfataltraps", NULL, 531 NULL, 0, &cpu_printfataltraps, 0, 532 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 533 cpu_unaligned_sigbus = !CPU_IS_ARMV6_P() && !CPU_IS_ARMV7_P(); 534 sysctl_createv(clog, 0, NULL, NULL, 535 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 536 CTLTYPE_INT, "unaligned_sigbus", 537 SYSCTL_DESCR("Do SIGBUS for fixed unaligned accesses"), 538 NULL, 0, &cpu_unaligned_sigbus, 0, 539 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 540 } 541 542 void 543 parse_mi_bootargs(char *args) 544 { 545 int integer; 546 547 if (get_bootconf_option(args, "single", BOOTOPT_TYPE_BOOLEAN, &integer) 548 || get_bootconf_option(args, "-s", BOOTOPT_TYPE_BOOLEAN, &integer)) 549 if (integer) 550 boothowto |= RB_SINGLE; 551 if (get_bootconf_option(args, "kdb", BOOTOPT_TYPE_BOOLEAN, &integer) 552 || get_bootconf_option(args, "-k", BOOTOPT_TYPE_BOOLEAN, &integer) 553 || get_bootconf_option(args, "-d", BOOTOPT_TYPE_BOOLEAN, &integer)) 554 if (integer) 555 boothowto |= RB_KDB; 556 if (get_bootconf_option(args, "ask", BOOTOPT_TYPE_BOOLEAN, &integer) 557 || get_bootconf_option(args, "-a", BOOTOPT_TYPE_BOOLEAN, &integer)) 558 if (integer) 559 boothowto |= RB_ASKNAME; 560 561 #ifdef PMAP_DEBUG 562 if (get_bootconf_option(args, "pmapdebug", BOOTOPT_TYPE_INT, &integer)) { 563 pmap_debug_level = integer; 564 pmap_debug(pmap_debug_level); 565 } 566 #endif /* PMAP_DEBUG */ 567 568 /* if (get_bootconf_option(args, "nbuf", BOOTOPT_TYPE_INT, &integer)) 569 bufpages = integer;*/ 570 571 #if defined(MEMORY_DISK_HOOKS) && !defined(MEMORY_DISK_ROOT_SIZE) 572 if (get_bootconf_option(args, "memorydisc", BOOTOPT_TYPE_INT, &integer) 573 || get_bootconf_option(args, "memorydisk", BOOTOPT_TYPE_INT, &integer)) { 574 md_root_size = integer; 575 md_root_size *= 1024; 576 if (md_root_size < 32*1024) 577 md_root_size = 32*1024; 578 if (md_root_size > 2048*1024) 579 md_root_size = 2048*1024; 580 } 581 #endif /* MEMORY_DISK_HOOKS && !MEMORY_DISK_ROOT_SIZE */ 582 583 if (get_bootconf_option(args, "quiet", BOOTOPT_TYPE_BOOLEAN, &integer) 584 || get_bootconf_option(args, "-q", BOOTOPT_TYPE_BOOLEAN, &integer)) 585 if (integer) 586 boothowto |= AB_QUIET; 587 if (get_bootconf_option(args, "verbose", BOOTOPT_TYPE_BOOLEAN, &integer) 588 || get_bootconf_option(args, "-v", BOOTOPT_TYPE_BOOLEAN, &integer)) 589 if (integer) 590 boothowto |= AB_VERBOSE; 591 if (get_bootconf_option(args, "debug", BOOTOPT_TYPE_BOOLEAN, &integer) 592 || get_bootconf_option(args, "-x", BOOTOPT_TYPE_BOOLEAN, &integer)) 593 if (integer) 594 boothowto |= AB_DEBUG; 595 } 596 597 #ifdef __HAVE_FAST_SOFTINTS 598 #if IPL_SOFTSERIAL != IPL_SOFTNET + 1 599 #error IPLs are screwed up 600 #elif IPL_SOFTNET != IPL_SOFTBIO + 1 601 #error IPLs are screwed up 602 #elif IPL_SOFTBIO != IPL_SOFTCLOCK + 1 603 #error IPLs are screwed up 604 #elif !(IPL_SOFTCLOCK > IPL_NONE) 605 #error IPLs are screwed up 606 #elif (IPL_NONE != 0) 607 #error IPLs are screwed up 608 #endif 609 610 #ifndef __HAVE_PIC_FAST_SOFTINTS 611 #define SOFTINT2IPLMAP \ 612 (((IPL_SOFTSERIAL - IPL_SOFTCLOCK) << (SOFTINT_SERIAL * 4)) | \ 613 ((IPL_SOFTNET - IPL_SOFTCLOCK) << (SOFTINT_NET * 4)) | \ 614 ((IPL_SOFTBIO - IPL_SOFTCLOCK) << (SOFTINT_BIO * 4)) | \ 615 ((IPL_SOFTCLOCK - IPL_SOFTCLOCK) << (SOFTINT_CLOCK * 4))) 616 #define SOFTINT2IPL(l) ((SOFTINT2IPLMAP >> ((l) * 4)) & 0x0f) 617 618 /* 619 * This returns a mask of softint IPLs that be dispatch at <ipl> 620 * SOFTIPLMASK(IPL_NONE) = 0x0000000f 621 * SOFTIPLMASK(IPL_SOFTCLOCK) = 0x0000000e 622 * SOFTIPLMASK(IPL_SOFTBIO) = 0x0000000c 623 * SOFTIPLMASK(IPL_SOFTNET) = 0x00000008 624 * SOFTIPLMASK(IPL_SOFTSERIAL) = 0x00000000 625 */ 626 #define SOFTIPLMASK(ipl) ((0x0f << (ipl)) & 0x0f) 627 628 void softint_switch(lwp_t *, int); 629 630 void 631 softint_trigger(uintptr_t mask) 632 { 633 curcpu()->ci_softints |= mask; 634 } 635 636 void 637 softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep) 638 { 639 lwp_t ** lp = &l->l_cpu->ci_softlwps[level]; 640 KASSERT(*lp == NULL || *lp == l); 641 *lp = l; 642 *machdep = 1 << SOFTINT2IPL(level); 643 KASSERT(level != SOFTINT_CLOCK || *machdep == (1 << (IPL_SOFTCLOCK - IPL_SOFTCLOCK))); 644 KASSERT(level != SOFTINT_BIO || *machdep == (1 << (IPL_SOFTBIO - IPL_SOFTCLOCK))); 645 KASSERT(level != SOFTINT_NET || *machdep == (1 << (IPL_SOFTNET - IPL_SOFTCLOCK))); 646 KASSERT(level != SOFTINT_SERIAL || *machdep == (1 << (IPL_SOFTSERIAL - IPL_SOFTCLOCK))); 647 } 648 649 void 650 dosoftints(void) 651 { 652 struct cpu_info * const ci = curcpu(); 653 const int opl = ci->ci_cpl; 654 const uint32_t softiplmask = SOFTIPLMASK(opl); 655 656 splhigh(); 657 for (;;) { 658 u_int softints = ci->ci_softints & softiplmask; 659 KASSERT((softints != 0) == ((ci->ci_softints >> opl) != 0)); 660 KASSERT(opl == IPL_NONE || (softints & (1 << (opl - IPL_SOFTCLOCK))) == 0); 661 if (softints == 0) { 662 splx(opl); 663 return; 664 } 665 #define DOSOFTINT(n) \ 666 if (ci->ci_softints & (1 << (IPL_SOFT ## n - IPL_SOFTCLOCK))) { \ 667 ci->ci_softints &= \ 668 ~(1 << (IPL_SOFT ## n - IPL_SOFTCLOCK)); \ 669 softint_switch(ci->ci_softlwps[SOFTINT_ ## n], \ 670 IPL_SOFT ## n); \ 671 continue; \ 672 } 673 DOSOFTINT(SERIAL); 674 DOSOFTINT(NET); 675 DOSOFTINT(BIO); 676 DOSOFTINT(CLOCK); 677 panic("dosoftints wtf (softints=%u?, ipl=%d)", softints, opl); 678 } 679 } 680 #endif /* !__HAVE_PIC_FAST_SOFTINTS */ 681 #endif /* __HAVE_FAST_SOFTINTS */ 682 683 #ifdef MODULAR 684 /* 685 * Push any modules loaded by the boot loader. 686 */ 687 void 688 module_init_md(void) 689 { 690 } 691 #endif /* MODULAR */ 692 693 int 694 mm_md_physacc(paddr_t pa, vm_prot_t prot) 695 { 696 if (pa >= physical_start && pa < physical_end) 697 return 0; 698 699 return kauth_authorize_machdep(kauth_cred_get(), 700 KAUTH_MACHDEP_UNMANAGEDMEM, NULL, NULL, NULL, NULL); 701 } 702 703 #ifdef __HAVE_CPU_UAREA_ALLOC_IDLELWP 704 vaddr_t 705 cpu_uarea_alloc_idlelwp(struct cpu_info *ci) 706 { 707 const vaddr_t va = idlestack.pv_va + cpu_index(ci) * USPACE; 708 // printf("%s: %s: va=%lx\n", __func__, ci->ci_data.cpu_name, va); 709 return va; 710 } 711 #endif 712 713 #ifdef MULTIPROCESSOR 714 /* 715 * Initialise a secondary processor. 716 * 717 * printf isn't available to us for a number of reasons. 718 * 719 * - kprint_init has been called and printf will try to take locks which we 720 * can't do just yet because bootstrap translation tables do not allowing 721 * caching. 722 * 723 * - kmutex(9) relies on curcpu which isn't setup yet. 724 * 725 */ 726 void 727 cpu_init_secondary_processor(int cpuindex) 728 { 729 // pmap_kernel has been sucessfully built and we can switch to it 730 731 cpu_domains(DOMAIN_DEFAULT); 732 cpu_idcache_wbinv_all(); 733 734 VPRINTS("index: "); 735 VPRINTX(cpuindex); 736 VPRINTS(" ttb"); 737 738 cpu_setup(boot_args); 739 740 #ifdef ARM_MMU_EXTENDED 741 /* 742 * TTBCR should have been initialized by the MD start code. 743 */ 744 KASSERT((armreg_contextidr_read() & 0xff) == 0); 745 KASSERT(armreg_ttbcr_read() == __SHIFTIN(1, TTBCR_S_N)); 746 /* 747 * Disable lookups via TTBR0 until there is an activated pmap. 748 */ 749 750 armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0); 751 cpu_setttb(pmap_kernel()->pm_l1_pa , KERNEL_PID); 752 arm_isb(); 753 #else 754 cpu_setttb(pmap_kernel()->pm_l1->l1_physaddr, true); 755 #endif 756 757 cpu_tlb_flushID(); 758 759 VPRINTS(" (TTBR0="); 760 VPRINTX(armreg_ttbr_read()); 761 VPRINTS(")"); 762 763 #ifdef ARM_MMU_EXTENDED 764 VPRINTS(" (TTBR1="); 765 VPRINTX(armreg_ttbr1_read()); 766 VPRINTS(")"); 767 VPRINTS(" (TTBCR="); 768 VPRINTX(armreg_ttbcr_read()); 769 VPRINTS(")"); 770 #endif 771 772 VPRINTS(" hatched="); 773 VPRINTX(arm_cpu_hatched | __BIT(cpuindex)); 774 VPRINTS("\n\r"); 775 776 atomic_or_uint(&arm_cpu_hatched, __BIT(cpuindex)); 777 778 /* return to assembly to wait for cpu_boot_secondary_processors */ 779 } 780 781 void 782 cpu_boot_secondary_processors(void) 783 { 784 VPRINTF("%s: writing mbox with %#x\n", __func__, arm_cpu_hatched); 785 arm_cpu_mbox = arm_cpu_hatched; 786 membar_producer(); 787 #ifdef _ARM_ARCH_7 788 __asm __volatile("sev; sev; sev"); 789 #endif 790 while (membar_consumer(), arm_cpu_mbox) { 791 __asm __volatile("wfe" ::: "memory"); 792 } 793 } 794 795 void 796 xc_send_ipi(struct cpu_info *ci) 797 { 798 KASSERT(kpreempt_disabled()); 799 KASSERT(curcpu() != ci); 800 801 intr_ipi_send(ci != NULL ? ci->ci_kcpuset : NULL, IPI_XCALL); 802 } 803 804 void 805 cpu_ipi(struct cpu_info *ci) 806 { 807 KASSERT(kpreempt_disabled()); 808 KASSERT(curcpu() != ci); 809 810 intr_ipi_send(ci != NULL ? ci->ci_kcpuset : NULL, IPI_GENERIC); 811 } 812 813 #endif /* MULTIPROCESSOR */ 814 815 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 816 bool 817 mm_md_direct_mapped_phys(paddr_t pa, vaddr_t *vap) 818 { 819 bool rv; 820 vaddr_t va = pmap_direct_mapped_phys(pa, &rv, 0); 821 if (rv) { 822 *vap = va; 823 } 824 return rv; 825 } 826 #endif 827 828 bool 829 mm_md_page_color(paddr_t pa, int *colorp) 830 { 831 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 832 *colorp = atop(pa & arm_cache_prefer_mask); 833 834 return arm_cache_prefer_mask ? false : true; 835 #else 836 *colorp = 0; 837 838 return true; 839 #endif 840 } 841 842 #if defined(FDT) 843 extern char KERNEL_BASE_phys[]; 844 #define KERNEL_BASE_PHYS ((paddr_t)KERNEL_BASE_phys) 845 846 void 847 cpu_kernel_vm_init(paddr_t memory_start, psize_t memory_size) 848 { 849 const struct arm_platform *plat = arm_fdt_platform(); 850 851 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 852 const bool mapallmem_p = true; 853 #ifndef PMAP_NEED_ALLOC_POOLPAGE 854 if (memory_size > KERNEL_VM_BASE - KERNEL_BASE) { 855 VPRINTF("%s: dropping RAM size from %luMB to %uMB\n", 856 __func__, (unsigned long) (memory_size >> 20), 857 (KERNEL_VM_BASE - KERNEL_BASE) >> 20); 858 memory_size = KERNEL_VM_BASE - KERNEL_BASE; 859 } 860 #endif 861 #else 862 const bool mapallmem_p = false; 863 #endif 864 865 VPRINTF("%s: kernel phys start %" PRIxPADDR " end %" PRIxPADDR "\n", 866 __func__, memory_start, memory_start + memory_size); 867 868 arm32_bootmem_init(memory_start, memory_size, KERNEL_BASE_PHYS); 869 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 870 plat->ap_devmap(), mapallmem_p); 871 } 872 #endif 873 874
Indexes created Thu Sep 25 16:09:42 GMT 2025