arm32_machdep.c revision 1.141
1 /* $NetBSD: arm32_machdep.c,v 1.141 2021/10/31 16:23:47 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * Machine dependent functions for kernel setup 39 * 40 * Created : 17/09/94 41 * Updated : 18/04/01 updated for new wscons 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.141 2021/10/31 16:23:47 skrll Exp $"); 46 47 #include "opt_arm_debug.h" 48 #include "opt_arm_start.h" 49 #include "opt_fdt.h" 50 #include "opt_modular.h" 51 #include "opt_md.h" 52 #include "opt_multiprocessor.h" 53 54 #include <sys/param.h> 55 56 #include <sys/atomic.h> 57 #include <sys/buf.h> 58 #include <sys/cpu.h> 59 #include <sys/device.h> 60 #include <sys/intr.h> 61 #include <sys/ipi.h> 62 #include <sys/kauth.h> 63 #include <sys/kernel.h> 64 #include <sys/mbuf.h> 65 #include <sys/module.h> 66 #include <sys/mount.h> 67 #include <sys/msgbuf.h> 68 #include <sys/proc.h> 69 #include <sys/reboot.h> 70 #include <sys/sysctl.h> 71 #include <sys/systm.h> 72 #include <sys/xcall.h> 73 74 #include <uvm/uvm_extern.h> 75 76 #include <dev/cons.h> 77 #include <dev/mm.h> 78 79 #include <arm/locore.h> 80 81 #include <arm/cpu_topology.h> 82 #include <arm/arm32/machdep.h> 83 84 #include <machine/bootconfig.h> 85 #include <machine/pcb.h> 86 87 #if defined(FDT) 88 #include <arm/fdt/arm_fdtvar.h> 89 #include <arch/evbarm/fdt/platform.h> 90 #endif 91 92 #ifdef VERBOSE_INIT_ARM 93 #define VPRINTF(...) printf(__VA_ARGS__) 94 #ifdef __HAVE_GENERIC_START 95 void generic_prints(const char *); 96 void generic_printx(int); 97 #define VPRINTS(s) generic_prints(s) 98 #define VPRINTX(x) generic_printx(x) 99 #else 100 #define VPRINTS(s) __nothing 101 #define VPRINTX(x) __nothing 102 #endif 103 #else 104 #define VPRINTF(...) __nothing 105 #define VPRINTS(s) __nothing 106 #define VPRINTX(x) __nothing 107 #endif 108 109 void (*cpu_reset_address)(void); /* Used by locore */ 110 paddr_t cpu_reset_address_paddr; /* Used by locore */ 111 112 struct vm_map *phys_map = NULL; 113 114 #if defined(MEMORY_DISK_HOOKS) && !defined(MEMORY_DISK_ROOT_SIZE) 115 extern size_t md_root_size; /* Memory disc size */ 116 #endif /* MEMORY_DISK_HOOKS && !MEMORY_DISK_ROOT_SIZE */ 117 118 pv_addr_t kernelstack; 119 pv_addr_t abtstack; 120 pv_addr_t fiqstack; 121 pv_addr_t irqstack; 122 pv_addr_t undstack; 123 pv_addr_t idlestack; 124 125 void * msgbufaddr; 126 extern paddr_t msgbufphys; 127 128 int kernel_debug = 0; 129 int cpu_printfataltraps = 0; 130 int cpu_fpu_present; 131 int cpu_hwdiv_present; 132 int cpu_neon_present; 133 int cpu_simd_present; 134 int cpu_simdex_present; 135 int cpu_umull_present; 136 int cpu_synchprim_present; 137 int cpu_unaligned_sigbus; 138 const char *cpu_arch = ""; 139 140 int cpu_instruction_set_attributes[6]; 141 int cpu_memory_model_features[4]; 142 int cpu_processor_features[2]; 143 int cpu_media_and_vfp_features[2]; 144 145 /* exported variable to be filled in by the bootloaders */ 146 char *booted_kernel; 147 148 /* Prototypes */ 149 150 void data_abort_handler(trapframe_t *frame); 151 void prefetch_abort_handler(trapframe_t *frame); 152 extern void configure(void); 153 154 /* 155 * arm32_vector_init: 156 * 157 * Initialize the vector page, and select whether or not to 158 * relocate the vectors. 159 * 160 * NOTE: We expect the vector page to be mapped at its expected 161 * destination. 162 */ 163 void 164 arm32_vector_init(vaddr_t va, int which) 165 { 166 #if defined(CPU_ARMV7) || defined(CPU_ARM11) || defined(ARM_HAS_VBAR) 167 /* 168 * If this processor has the security extension, don't bother 169 * to move/map the vector page. Simply point VBAR to the copy 170 * that exists in the .text segment. 171 */ 172 #ifndef ARM_HAS_VBAR 173 if (va == ARM_VECTORS_LOW 174 && (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0) { 175 #endif 176 extern const uint32_t page0rel[]; 177 vector_page = (vaddr_t)page0rel; 178 KASSERT((vector_page & 0x1f) == 0); 179 armreg_vbar_write(vector_page); 180 VPRINTF(" vbar=%p", page0rel); 181 cpu_control(CPU_CONTROL_VECRELOC, 0); 182 return; 183 #ifndef ARM_HAS_VBAR 184 } 185 #endif 186 #endif 187 #ifndef ARM_HAS_VBAR 188 if (CPU_IS_PRIMARY(curcpu())) { 189 extern unsigned int page0[], page0_data[]; 190 unsigned int *vectors = (int *) va; 191 unsigned int *vectors_data = vectors + (page0_data - page0); 192 int vec; 193 194 /* 195 * Loop through the vectors we're taking over, and copy the 196 * vector's insn and data word. 197 */ 198 for (vec = 0; vec < ARM_NVEC; vec++) { 199 if ((which & (1 << vec)) == 0) { 200 /* Don't want to take over this vector. */ 201 continue; 202 } 203 vectors[vec] = page0[vec]; 204 vectors_data[vec] = page0_data[vec]; 205 } 206 207 /* Now sync the vectors. */ 208 cpu_icache_sync_range(va, (ARM_NVEC * 2) * sizeof(u_int)); 209 210 vector_page = va; 211 } 212 213 if (va == ARM_VECTORS_HIGH) { 214 /* 215 * Assume the MD caller knows what it's doing here, and 216 * really does want the vector page relocated. 217 * 218 * Note: This has to be done here (and not just in 219 * cpu_setup()) because the vector page needs to be 220 * accessible *before* cpu_startup() is called. 221 * Think ddb(9) ... 222 * 223 * NOTE: If the CPU control register is not readable, 224 * this will totally fail! We'll just assume that 225 * any system that has high vector support has a 226 * readable CPU control register, for now. If we 227 * ever encounter one that does not, we'll have to 228 * rethink this. 229 */ 230 cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC); 231 } 232 #endif 233 } 234 235 /* 236 * Debug function just to park the CPU 237 */ 238 239 void 240 halt(void) 241 { 242 while (1) 243 cpu_sleep(0); 244 } 245 246 247 /* Sync the discs, unmount the filesystems, and adjust the todr */ 248 249 void 250 bootsync(void) 251 { 252 static bool bootsyncdone = false; 253 254 if (bootsyncdone) return; 255 256 bootsyncdone = true; 257 258 /* Make sure we can still manage to do things */ 259 if (GetCPSR() & I32_bit) { 260 /* 261 * If we get here then boot has been called without RB_NOSYNC 262 * and interrupts were disabled. This means the boot() call 263 * did not come from a user process e.g. shutdown, but must 264 * have come from somewhere in the kernel. 265 */ 266 IRQenable; 267 printf("Warning IRQ's disabled during boot()\n"); 268 } 269 270 vfs_shutdown(); 271 272 resettodr(); 273 } 274 275 /* 276 * void cpu_startup(void) 277 * 278 * Machine dependent startup code. 279 * 280 */ 281 void 282 cpu_startup(void) 283 { 284 vaddr_t minaddr; 285 vaddr_t maxaddr; 286 287 #ifndef __HAVE_GENERIC_START 288 /* Set the CPU control register */ 289 cpu_setup(boot_args); 290 #endif 291 292 #ifndef ARM_HAS_VBAR 293 /* Lock down zero page */ 294 vector_page_setprot(VM_PROT_READ); 295 #endif 296 297 /* 298 * Give pmap a chance to set up a few more things now the vm 299 * is initialised 300 */ 301 pmap_postinit(); 302 303 #ifdef FDT 304 if (arm_fdt_platform()->ap_startup != NULL) 305 arm_fdt_platform()->ap_startup(); 306 #endif 307 308 /* 309 * Initialize error message buffer (at end of core). 310 */ 311 312 /* msgbufphys was setup during the secondary boot strap */ 313 if (!pmap_extract(pmap_kernel(), (vaddr_t)msgbufaddr, NULL)) { 314 for (u_int loop = 0; loop < btoc(MSGBUFSIZE); ++loop) { 315 pmap_kenter_pa((vaddr_t)msgbufaddr + loop * PAGE_SIZE, 316 msgbufphys + loop * PAGE_SIZE, 317 VM_PROT_READ|VM_PROT_WRITE, 0); 318 } 319 } 320 pmap_update(pmap_kernel()); 321 initmsgbuf(msgbufaddr, round_page(MSGBUFSIZE)); 322 323 /* 324 * Allocate a submap for physio 325 */ 326 minaddr = 0; 327 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 328 VM_PHYS_SIZE, 0, false, NULL); 329 330 banner(); 331 332 /* 333 * This is actually done by initarm_common, but not all ports use it 334 * yet so do it here to catch them as well 335 */ 336 struct lwp * const l = &lwp0; 337 struct pcb * const pcb = lwp_getpcb(l); 338 339 /* Zero out the PCB. */ 340 memset(pcb, 0, sizeof(*pcb)); 341 342 pcb->pcb_ksp = uvm_lwp_getuarea(l) + USPACE_SVC_STACK_TOP; 343 pcb->pcb_ksp -= sizeof(struct trapframe); 344 345 struct trapframe * tf = (struct trapframe *)pcb->pcb_ksp; 346 347 /* Zero out the trapframe. */ 348 memset(tf, 0, sizeof(*tf)); 349 lwp_settrapframe(l, tf); 350 351 tf->tf_spsr = PSR_USR32_MODE; 352 #ifdef _ARM_ARCH_BE8 353 tf->tf_spsr |= PSR_E_BIT; 354 #endif 355 356 cpu_startup_hook(); 357 } 358 359 __weak_alias(cpu_startup_hook,cpu_startup_default) 360 void 361 cpu_startup_default(void) 362 { 363 } 364 365 /* 366 * machine dependent system variables. 367 */ 368 static int 369 sysctl_machdep_booted_device(SYSCTLFN_ARGS) 370 { 371 struct sysctlnode node; 372 373 if (booted_device == NULL) 374 return EOPNOTSUPP; 375 376 node = *rnode; 377 node.sysctl_data = __UNCONST(device_xname(booted_device)); 378 node.sysctl_size = strlen(device_xname(booted_device)) + 1; 379 return sysctl_lookup(SYSCTLFN_CALL(&node)); 380 } 381 382 static int 383 sysctl_machdep_booted_kernel(SYSCTLFN_ARGS) 384 { 385 struct sysctlnode node; 386 387 if (booted_kernel == NULL || booted_kernel[0] == '\0') 388 return EOPNOTSUPP; 389 390 node = *rnode; 391 node.sysctl_data = booted_kernel; 392 node.sysctl_size = strlen(booted_kernel) + 1; 393 return sysctl_lookup(SYSCTLFN_CALL(&node)); 394 } 395 396 static int 397 sysctl_machdep_cpu_arch(SYSCTLFN_ARGS) 398 { 399 struct sysctlnode node = *rnode; 400 node.sysctl_data = __UNCONST(cpu_arch); 401 node.sysctl_size = strlen(cpu_arch) + 1; 402 return sysctl_lookup(SYSCTLFN_CALL(&node)); 403 } 404 405 static int 406 sysctl_machdep_powersave(SYSCTLFN_ARGS) 407 { 408 struct sysctlnode node = *rnode; 409 int error, newval; 410 411 newval = cpu_do_powersave; 412 node.sysctl_data = &newval; 413 if (cpufuncs.cf_sleep == (void *) cpufunc_nullop) 414 node.sysctl_flags &= ~CTLFLAG_READWRITE; 415 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 416 if (error || newp == NULL || newval == cpu_do_powersave) 417 return error; 418 419 if (newval < 0 || newval > 1) 420 return EINVAL; 421 cpu_do_powersave = newval; 422 423 return 0; 424 } 425 426 SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup") 427 { 428 429 sysctl_createv(clog, 0, NULL, NULL, 430 CTLFLAG_PERMANENT, 431 CTLTYPE_NODE, "machdep", NULL, 432 NULL, 0, NULL, 0, 433 CTL_MACHDEP, CTL_EOL); 434 435 sysctl_createv(clog, 0, NULL, NULL, 436 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 437 CTLTYPE_INT, "debug", NULL, 438 NULL, 0, &kernel_debug, 0, 439 CTL_MACHDEP, CPU_DEBUG, CTL_EOL); 440 sysctl_createv(clog, 0, NULL, NULL, 441 CTLFLAG_PERMANENT, 442 CTLTYPE_STRING, "booted_device", NULL, 443 sysctl_machdep_booted_device, 0, NULL, 0, 444 CTL_MACHDEP, CPU_BOOTED_DEVICE, CTL_EOL); 445 sysctl_createv(clog, 0, NULL, NULL, 446 CTLFLAG_PERMANENT, 447 CTLTYPE_STRING, "booted_kernel", NULL, 448 sysctl_machdep_booted_kernel, 0, NULL, 0, 449 CTL_MACHDEP, CPU_BOOTED_KERNEL, CTL_EOL); 450 sysctl_createv(clog, 0, NULL, NULL, 451 CTLFLAG_PERMANENT, 452 CTLTYPE_STRUCT, "console_device", NULL, 453 sysctl_consdev, 0, NULL, sizeof(dev_t), 454 CTL_MACHDEP, CPU_CONSDEV, CTL_EOL); 455 sysctl_createv(clog, 0, NULL, NULL, 456 CTLFLAG_PERMANENT, 457 CTLTYPE_STRING, "cpu_arch", NULL, 458 sysctl_machdep_cpu_arch, 0, NULL, 0, 459 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 460 sysctl_createv(clog, 0, NULL, NULL, 461 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 462 CTLTYPE_INT, "powersave", NULL, 463 sysctl_machdep_powersave, 0, &cpu_do_powersave, 0, 464 CTL_MACHDEP, CPU_POWERSAVE, CTL_EOL); 465 sysctl_createv(clog, 0, NULL, NULL, 466 CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE, 467 CTLTYPE_INT, "cpu_id", NULL, 468 NULL, curcpu()->ci_arm_cpuid, NULL, 0, 469 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 470 #ifdef FPU_VFP 471 sysctl_createv(clog, 0, NULL, NULL, 472 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 473 CTLTYPE_INT, "fpu_id", NULL, 474 NULL, 0, &cpu_info_store[0].ci_vfp_id, 0, 475 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 476 #endif 477 sysctl_createv(clog, 0, NULL, NULL, 478 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 479 CTLTYPE_INT, "fpu_present", NULL, 480 NULL, 0, &cpu_fpu_present, 0, 481 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 482 sysctl_createv(clog, 0, NULL, NULL, 483 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 484 CTLTYPE_INT, "hwdiv_present", NULL, 485 NULL, 0, &cpu_hwdiv_present, 0, 486 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 487 sysctl_createv(clog, 0, NULL, NULL, 488 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 489 CTLTYPE_INT, "neon_present", NULL, 490 NULL, 0, &cpu_neon_present, 0, 491 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 492 sysctl_createv(clog, 0, NULL, NULL, 493 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 494 CTLTYPE_STRUCT, "id_isar", NULL, 495 NULL, 0, 496 cpu_instruction_set_attributes, 497 sizeof(cpu_instruction_set_attributes), 498 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 499 sysctl_createv(clog, 0, NULL, NULL, 500 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 501 CTLTYPE_STRUCT, "id_mmfr", NULL, 502 NULL, 0, 503 cpu_memory_model_features, 504 sizeof(cpu_memory_model_features), 505 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 506 sysctl_createv(clog, 0, NULL, NULL, 507 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 508 CTLTYPE_STRUCT, "id_pfr", NULL, 509 NULL, 0, 510 cpu_processor_features, 511 sizeof(cpu_processor_features), 512 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 513 sysctl_createv(clog, 0, NULL, NULL, 514 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 515 CTLTYPE_STRUCT, "id_mvfr", NULL, 516 NULL, 0, 517 cpu_media_and_vfp_features, 518 sizeof(cpu_media_and_vfp_features), 519 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 520 sysctl_createv(clog, 0, NULL, NULL, 521 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 522 CTLTYPE_INT, "simd_present", NULL, 523 NULL, 0, &cpu_simd_present, 0, 524 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 525 sysctl_createv(clog, 0, NULL, NULL, 526 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 527 CTLTYPE_INT, "simdex_present", NULL, 528 NULL, 0, &cpu_simdex_present, 0, 529 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 530 sysctl_createv(clog, 0, NULL, NULL, 531 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 532 CTLTYPE_INT, "synchprim_present", NULL, 533 NULL, 0, &cpu_synchprim_present, 0, 534 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 535 sysctl_createv(clog, 0, NULL, NULL, 536 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 537 CTLTYPE_INT, "printfataltraps", NULL, 538 NULL, 0, &cpu_printfataltraps, 0, 539 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 540 cpu_unaligned_sigbus = 541 #if defined(__ARMEL__) 542 !CPU_IS_ARMV6_P() && !CPU_IS_ARMV7_P(); 543 #elif defined(_ARM_ARCH_BE8) 544 0; 545 #else 546 1; 547 #endif 548 sysctl_createv(clog, 0, NULL, NULL, 549 CTLFLAG_PERMANENT|CTLFLAG_READONLY, 550 CTLTYPE_INT, "unaligned_sigbus", 551 SYSCTL_DESCR("Do SIGBUS for fixed unaligned accesses"), 552 NULL, 0, &cpu_unaligned_sigbus, 0, 553 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 554 } 555 556 void 557 parse_mi_bootargs(char *args) 558 { 559 int integer; 560 561 if (get_bootconf_option(args, "single", BOOTOPT_TYPE_BOOLEAN, &integer) 562 || get_bootconf_option(args, "-s", BOOTOPT_TYPE_BOOLEAN, &integer)) 563 if (integer) 564 boothowto |= RB_SINGLE; 565 if (get_bootconf_option(args, "kdb", BOOTOPT_TYPE_BOOLEAN, &integer) 566 || get_bootconf_option(args, "-k", BOOTOPT_TYPE_BOOLEAN, &integer) 567 || get_bootconf_option(args, "-d", BOOTOPT_TYPE_BOOLEAN, &integer)) 568 if (integer) 569 boothowto |= RB_KDB; 570 if (get_bootconf_option(args, "ask", BOOTOPT_TYPE_BOOLEAN, &integer) 571 || get_bootconf_option(args, "-a", BOOTOPT_TYPE_BOOLEAN, &integer)) 572 if (integer) 573 boothowto |= RB_ASKNAME; 574 575 /* if (get_bootconf_option(args, "nbuf", BOOTOPT_TYPE_INT, &integer)) 576 bufpages = integer;*/ 577 578 #if defined(MEMORY_DISK_HOOKS) && !defined(MEMORY_DISK_ROOT_SIZE) 579 if (get_bootconf_option(args, "memorydisc", BOOTOPT_TYPE_INT, &integer) 580 || get_bootconf_option(args, "memorydisk", BOOTOPT_TYPE_INT, &integer)) { 581 md_root_size = integer; 582 md_root_size *= 1024; 583 if (md_root_size < 32*1024) 584 md_root_size = 32*1024; 585 if (md_root_size > 2048*1024) 586 md_root_size = 2048*1024; 587 } 588 #endif /* MEMORY_DISK_HOOKS && !MEMORY_DISK_ROOT_SIZE */ 589 590 if (get_bootconf_option(args, "quiet", BOOTOPT_TYPE_BOOLEAN, &integer) 591 || get_bootconf_option(args, "-q", BOOTOPT_TYPE_BOOLEAN, &integer)) 592 if (integer) 593 boothowto |= AB_QUIET; 594 if (get_bootconf_option(args, "verbose", BOOTOPT_TYPE_BOOLEAN, &integer) 595 || get_bootconf_option(args, "-v", BOOTOPT_TYPE_BOOLEAN, &integer)) 596 if (integer) 597 boothowto |= AB_VERBOSE; 598 if (get_bootconf_option(args, "debug", BOOTOPT_TYPE_BOOLEAN, &integer) 599 || get_bootconf_option(args, "-x", BOOTOPT_TYPE_BOOLEAN, &integer)) 600 if (integer) 601 boothowto |= AB_DEBUG; 602 } 603 604 #ifdef __HAVE_FAST_SOFTINTS 605 #if IPL_SOFTSERIAL != IPL_SOFTNET + 1 606 #error IPLs are screwed up 607 #elif IPL_SOFTNET != IPL_SOFTBIO + 1 608 #error IPLs are screwed up 609 #elif IPL_SOFTBIO != IPL_SOFTCLOCK + 1 610 #error IPLs are screwed up 611 #elif !(IPL_SOFTCLOCK > IPL_NONE) 612 #error IPLs are screwed up 613 #elif (IPL_NONE != 0) 614 #error IPLs are screwed up 615 #endif 616 617 #ifndef __HAVE_PIC_FAST_SOFTINTS 618 #define SOFTINT2IPLMAP \ 619 (((IPL_SOFTSERIAL - IPL_SOFTCLOCK) << (SOFTINT_SERIAL * 4)) | \ 620 ((IPL_SOFTNET - IPL_SOFTCLOCK) << (SOFTINT_NET * 4)) | \ 621 ((IPL_SOFTBIO - IPL_SOFTCLOCK) << (SOFTINT_BIO * 4)) | \ 622 ((IPL_SOFTCLOCK - IPL_SOFTCLOCK) << (SOFTINT_CLOCK * 4))) 623 #define SOFTINT2IPL(l) ((SOFTINT2IPLMAP >> ((l) * 4)) & 0x0f) 624 625 /* 626 * This returns a mask of softint IPLs that be dispatch at <ipl> 627 * SOFTIPLMASK(IPL_NONE) = 0x0000000f 628 * SOFTIPLMASK(IPL_SOFTCLOCK) = 0x0000000e 629 * SOFTIPLMASK(IPL_SOFTBIO) = 0x0000000c 630 * SOFTIPLMASK(IPL_SOFTNET) = 0x00000008 631 * SOFTIPLMASK(IPL_SOFTSERIAL) = 0x00000000 632 */ 633 #define SOFTIPLMASK(ipl) ((0x0f << (ipl)) & 0x0f) 634 635 void softint_switch(lwp_t *, int); 636 637 void 638 softint_trigger(uintptr_t mask) 639 { 640 curcpu()->ci_softints |= mask; 641 } 642 643 void 644 softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep) 645 { 646 lwp_t ** lp = &l->l_cpu->ci_softlwps[level]; 647 KASSERT(*lp == NULL || *lp == l); 648 *lp = l; 649 *machdep = 1 << SOFTINT2IPL(level); 650 KASSERT(level != SOFTINT_CLOCK || *machdep == (1 << (IPL_SOFTCLOCK - IPL_SOFTCLOCK))); 651 KASSERT(level != SOFTINT_BIO || *machdep == (1 << (IPL_SOFTBIO - IPL_SOFTCLOCK))); 652 KASSERT(level != SOFTINT_NET || *machdep == (1 << (IPL_SOFTNET - IPL_SOFTCLOCK))); 653 KASSERT(level != SOFTINT_SERIAL || *machdep == (1 << (IPL_SOFTSERIAL - IPL_SOFTCLOCK))); 654 } 655 656 void 657 dosoftints(void) 658 { 659 struct cpu_info * const ci = curcpu(); 660 const int opl = ci->ci_cpl; 661 const uint32_t softiplmask = SOFTIPLMASK(opl); 662 663 splhigh(); 664 for (;;) { 665 u_int softints = ci->ci_softints & softiplmask; 666 KASSERT((softints != 0) == ((ci->ci_softints >> opl) != 0)); 667 KASSERT(opl == IPL_NONE || (softints & (1 << (opl - IPL_SOFTCLOCK))) == 0); 668 if (softints == 0) { 669 splx(opl); 670 return; 671 } 672 #define DOSOFTINT(n) \ 673 if (ci->ci_softints & (1 << (IPL_SOFT ## n - IPL_SOFTCLOCK))) { \ 674 ci->ci_softints &= \ 675 ~(1 << (IPL_SOFT ## n - IPL_SOFTCLOCK)); \ 676 softint_switch(ci->ci_softlwps[SOFTINT_ ## n], \ 677 IPL_SOFT ## n); \ 678 continue; \ 679 } 680 DOSOFTINT(SERIAL); 681 DOSOFTINT(NET); 682 DOSOFTINT(BIO); 683 DOSOFTINT(CLOCK); 684 panic("dosoftints wtf (softints=%u?, ipl=%d)", softints, opl); 685 } 686 } 687 #endif /* !__HAVE_PIC_FAST_SOFTINTS */ 688 #endif /* __HAVE_FAST_SOFTINTS */ 689 690 #ifdef MODULAR 691 /* 692 * Push any modules loaded by the boot loader. 693 */ 694 void 695 module_init_md(void) 696 { 697 #ifdef FDT 698 arm_fdt_module_init(); 699 #endif 700 } 701 #endif /* MODULAR */ 702 703 int 704 mm_md_physacc(paddr_t pa, vm_prot_t prot) 705 { 706 if (pa >= physical_start && pa < physical_end) 707 return 0; 708 709 return kauth_authorize_machdep(kauth_cred_get(), 710 KAUTH_MACHDEP_UNMANAGEDMEM, NULL, NULL, NULL, NULL); 711 } 712 713 #ifdef __HAVE_CPU_UAREA_ALLOC_IDLELWP 714 vaddr_t 715 cpu_uarea_alloc_idlelwp(struct cpu_info *ci) 716 { 717 const vaddr_t va = idlestack.pv_va + cpu_index(ci) * USPACE; 718 // printf("%s: %s: va=%lx\n", __func__, ci->ci_data.cpu_name, va); 719 return va; 720 } 721 #endif 722 723 #ifdef MULTIPROCESSOR 724 /* 725 * Initialise a secondary processor. 726 * 727 * printf isn't available to us for a number of reasons. 728 * 729 * - kprint_init has been called and printf will try to take locks which we 730 * can't do just yet because bootstrap translation tables do not allowing 731 * caching. 732 * 733 * - kmutex(9) relies on curcpu which isn't setup yet. 734 * 735 */ 736 void __noasan 737 cpu_init_secondary_processor(int cpuindex) 738 { 739 // pmap_kernel has been successfully built and we can switch to it 740 cpu_domains(DOMAIN_DEFAULT); 741 cpu_idcache_wbinv_all(); 742 743 VPRINTS("index: "); 744 VPRINTX(cpuindex); 745 VPRINTS(" ttb"); 746 747 cpu_setup(boot_args); 748 749 #ifdef ARM_MMU_EXTENDED 750 /* 751 * TTBCR should have been initialized by the MD start code. 752 */ 753 KASSERT((armreg_contextidr_read() & 0xff) == 0); 754 KASSERT(armreg_ttbcr_read() == __SHIFTIN(1, TTBCR_S_N)); 755 /* 756 * Disable lookups via TTBR0 until there is an activated pmap. 757 */ 758 759 armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0); 760 cpu_setttb(pmap_kernel()->pm_l1_pa , KERNEL_PID); 761 isb(); 762 #else 763 cpu_setttb(pmap_kernel()->pm_l1->l1_physaddr, true); 764 #endif 765 766 cpu_tlb_flushID(); 767 768 VPRINTS(" (TTBR0="); 769 VPRINTX(armreg_ttbr_read()); 770 VPRINTS(")"); 771 772 #ifdef ARM_MMU_EXTENDED 773 VPRINTS(" (TTBR1="); 774 VPRINTX(armreg_ttbr1_read()); 775 VPRINTS(")"); 776 VPRINTS(" (TTBCR="); 777 VPRINTX(armreg_ttbcr_read()); 778 VPRINTS(")"); 779 #endif 780 781 struct cpu_info * ci = &cpu_info_store[cpuindex]; 782 783 VPRINTS(" ci = "); 784 VPRINTX((int)ci); 785 786 ci->ci_ctrl = armreg_sctlr_read(); 787 ci->ci_arm_cpuid = cpu_idnum(); 788 ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK; 789 ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK; 790 791 ci->ci_midr = armreg_midr_read(); 792 ci->ci_actlr = armreg_auxctl_read(); 793 ci->ci_revidr = armreg_revidr_read(); 794 ci->ci_mpidr = armreg_mpidr_read(); 795 796 arm_cpu_topology_set(ci, ci->ci_mpidr); 797 798 VPRINTS(" vfp"); 799 vfp_detect(ci); 800 801 VPRINTS(" hatched |="); 802 VPRINTX(__BIT(cpuindex)); 803 VPRINTS("\n\r"); 804 805 cpu_set_hatched(cpuindex); 806 807 /* 808 * return to assembly to wait for cpu_boot_secondary_processors 809 */ 810 } 811 812 void 813 xc_send_ipi(struct cpu_info *ci) 814 { 815 KASSERT(kpreempt_disabled()); 816 KASSERT(curcpu() != ci); 817 818 intr_ipi_send(ci != NULL ? ci->ci_kcpuset : NULL, IPI_XCALL); 819 } 820 821 void 822 cpu_ipi(struct cpu_info *ci) 823 { 824 KASSERT(kpreempt_disabled()); 825 KASSERT(curcpu() != ci); 826 827 intr_ipi_send(ci != NULL ? ci->ci_kcpuset : NULL, IPI_GENERIC); 828 } 829 830 #endif /* MULTIPROCESSOR */ 831 832 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 833 bool 834 mm_md_direct_mapped_phys(paddr_t pa, vaddr_t *vap) 835 { 836 bool rv; 837 vaddr_t va = pmap_direct_mapped_phys(pa, &rv, 0); 838 if (rv) { 839 *vap = va; 840 } 841 return rv; 842 } 843 #endif 844 845 bool 846 mm_md_page_color(paddr_t pa, int *colorp) 847 { 848 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 849 *colorp = atop(pa & arm_cache_prefer_mask); 850 851 return arm_cache_prefer_mask ? false : true; 852 #else 853 *colorp = 0; 854 855 return true; 856 #endif 857 } 858 859 #if defined(FDT) 860 extern char KERNEL_BASE_phys[]; 861 #define KERNEL_BASE_PHYS ((paddr_t)KERNEL_BASE_phys) 862 863 void 864 cpu_kernel_vm_init(paddr_t memory_start, psize_t memory_size) 865 { 866 const struct arm_platform *plat = arm_fdt_platform(); 867 868 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 869 const bool mapallmem_p = true; 870 #ifndef PMAP_NEED_ALLOC_POOLPAGE 871 if (memory_size > KERNEL_VM_BASE - KERNEL_BASE) { 872 VPRINTF("%s: dropping RAM size from %luMB to %uMB\n", 873 __func__, (unsigned long) (memory_size >> 20), 874 (KERNEL_VM_BASE - KERNEL_BASE) >> 20); 875 memory_size = KERNEL_VM_BASE - KERNEL_BASE; 876 } 877 #endif 878 #else 879 const bool mapallmem_p = false; 880 #endif 881 882 VPRINTF("%s: kernel phys start %" PRIxPADDR " end %" PRIxPADDR "\n", 883 __func__, memory_start, memory_start + memory_size); 884 885 arm32_bootmem_init(memory_start, memory_size, KERNEL_BASE_PHYS); 886 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 887 plat->ap_devmap(), mapallmem_p); 888 } 889 #endif 890 891
Indexes created Tue Sep 30 06:09:59 GMT 2025