cpuswitch.S revision 1.102
1 /* $NetBSD: cpuswitch.S,v 1.102 2020/08/14 16:18:36 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 */ 79 80 #include "opt_armfpe.h" 81 #include "opt_cpuoptions.h" 82 #include "opt_kasan.h" 83 #include "opt_lockdebug.h" 84 #include "opt_multiprocessor.h" 85 86 #include "assym.h" 87 #include <arm/asm.h> 88 #include <arm/locore.h> 89 90 RCSID("$NetBSD: cpuswitch.S,v 1.102 2020/08/14 16:18:36 skrll Exp $") 91 92 /* LINTSTUB: include <sys/param.h> */ 93 94 #ifdef FPU_VFP 95 .fpu vfpv2 96 #endif 97 98 #undef IRQdisable 99 #undef IRQenable 100 101 /* 102 * New experimental definitions of IRQdisable and IRQenable 103 * These keep FIQ's enabled since FIQ's are special. 104 */ 105 106 #ifdef _ARM_ARCH_6 107 #define IRQdisable cpsid i 108 #define IRQenable cpsie i 109 #else 110 #define IRQdisable \ 111 mrs r14, cpsr ; \ 112 orr r14, r14, #(I32_bit) ; \ 113 msr cpsr_c, r14 114 115 #define IRQenable \ 116 mrs r14, cpsr ; \ 117 bic r14, r14, #(I32_bit) ; \ 118 msr cpsr_c, r14 119 120 #endif 121 122 .text 123 124 /* 125 * struct lwp * 126 * cpu_switchto(struct lwp *current, struct lwp *next) 127 * 128 * Switch to the specified next LWP 129 * Arguments: 130 * 131 * r0 'struct lwp *' of the current LWP 132 * r1 'struct lwp *' of the LWP to switch to 133 * r2 returning 134 */ 135 ENTRY(cpu_switchto) 136 mov ip, sp 137 push {r4-r7, ip, lr} 138 139 /* move lwps into caller saved registers */ 140 mov r6, r1 141 mov r4, r0 142 143 #ifdef TPIDRPRW_IS_CURCPU 144 GET_CURCPU(r5) 145 #else 146 ldr r5, [r6, #L_CPU] /* get cpu from new lwp */ 147 #endif 148 149 /* rem: r4 = old lwp */ 150 /* rem: r5 = curcpu() */ 151 /* rem: r6 = new lwp */ 152 /* rem: interrupts are enabled */ 153 154 /* Save old context */ 155 156 /* Get the user structure for the old lwp. */ 157 ldr r7, [r4, #(L_PCB)] 158 159 /* Save all the registers in the old lwp's pcb */ 160 #if defined(_ARM_ARCH_DWORD_OK) 161 strd r8, r9, [r7, #(PCB_R8)] 162 strd r10, r11, [r7, #(PCB_R10)] 163 strd r12, r13, [r7, #(PCB_R12)] 164 #else 165 add r0, r7, #(PCB_R8) 166 stmia r0, {r8-r13} 167 #endif 168 169 #ifdef _ARM_ARCH_6 170 /* 171 * Save user read/write thread/process id register 172 */ 173 mrc p15, 0, r0, c13, c0, 2 174 str r0, [r7, #(PCB_USER_PID_RW)] 175 #endif 176 /* 177 * NOTE: We can now use r8-r13 until it is time to restore 178 * them for the new process. 179 */ 180 181 /* Restore saved context */ 182 183 /* rem: r4 = old lwp */ 184 /* rem: r5 = curcpu() */ 185 /* rem: r6 = new lwp */ 186 187 IRQdisable 188 #if defined(TPIDRPRW_IS_CURLWP) 189 mcr p15, 0, r6, c13, c0, 4 /* set current lwp */ 190 #endif 191 192 /* We have a new curlwp now so make a note of it */ 193 str r6, [r5, #(CI_CURLWP)] 194 dmb /* see comments in kern_mutex.c */ 195 196 /* Get the new pcb */ 197 ldr r7, [r6, #(L_PCB)] 198 199 /* make sure we are using the new lwp's stack */ 200 ldr sp, [r7, #(PCB_KSP)] 201 202 /* At this point we can allow IRQ's again. */ 203 IRQenable 204 205 /* rem: r4 = old lwp */ 206 /* rem: r5 = curcpu() */ 207 /* rem: r6 = new lwp */ 208 /* rem: r7 = new pcb */ 209 /* rem: interrupts are enabled */ 210 211 /* 212 * If we are switching to a system lwp, don't bother restoring 213 * thread or vfp registers and skip the ras check. 214 */ 215 ldr r0, [r6, #(L_FLAG)] 216 tst r0, #(LW_SYSTEM) 217 bne .Lswitch_do_restore 218 219 #ifdef _ARM_ARCH_6 220 /* 221 * Restore user thread/process id registers 222 */ 223 ldr r0, [r7, #(PCB_USER_PID_RW)] 224 mcr p15, 0, r0, c13, c0, 2 225 ldr r0, [r6, #(L_PRIVATE)] 226 mcr p15, 0, r0, c13, c0, 3 227 #endif 228 229 #ifdef FPU_VFP 230 /* 231 * If we have a VFP, we need to load FPEXC. 232 */ 233 ldr r0, [r5, #(CI_VFP_ID)] 234 cmp r0, #0 235 ldrne r0, [r7, #(PCB_VFP_FPEXC)] 236 vmsrne fpexc, r0 237 #endif 238 239 /* 240 * Check for restartable atomic sequences (RAS). 241 */ 242 ldr r0, [r6, #(L_PROC)] /* fetch the proc for ras_lookup */ 243 ldr r2, [r0, #(P_RASLIST)] 244 cmp r2, #0 /* p->p_nras == 0? */ 245 beq .Lswitch_do_restore 246 247 /* we can use r8 since we haven't restored saved registers yet. */ 248 ldr r8, [r6, #(L_MD_TF)] /* r1 = trapframe (used below) */ 249 ldr r1, [r8, #(TF_PC)] /* second ras_lookup() arg */ 250 bl _C_LABEL(ras_lookup) 251 cmn r0, #1 /* -1 means "not in a RAS" */ 252 strne r0, [r8, #(TF_PC)] 253 254 /* rem: r4 = old lwp */ 255 /* rem: r5 = curcpu() */ 256 /* rem: r6 = new lwp */ 257 /* rem: r7 = new pcb */ 258 259 .Lswitch_do_restore: 260 /* Restore all the saved registers */ 261 #ifdef __XSCALE__ 262 ldr r8, [r7, #(PCB_R8)] 263 ldr r9, [r7, #(PCB_R9)] 264 ldr r10, [r7, #(PCB_R10)] 265 ldr r11, [r7, #(PCB_R11)] 266 ldr r12, [r7, #(PCB_R12)] 267 #elif defined(_ARM_ARCH_DWORD_OK) 268 ldrd r8, r9, [r7, #(PCB_R8)] 269 ldrd r10, r11, [r7, #(PCB_R10)] 270 ldr r12, [r7, #(PCB_R12)] 271 #else 272 add r0, r7, #PCB_R8 273 ldmia r0, {r8-r12} 274 #endif 275 276 /* Record the old lwp for pmap_activate()'s benefit */ 277 #ifndef ARM_MMU_EXTENDED 278 str r4, [r5, #CI_LASTLWP] 279 #endif 280 281 /* cpu_switchto returns the old lwp */ 282 mov r0, r4 283 /* lwp_trampoline expects new lwp as its second argument */ 284 mov r1, r6 285 286 #ifdef _ARM_ARCH_7 287 clrex /* cause any subsequent STREX* to fail */ 288 #endif 289 290 /* 291 * Pull the registers that got pushed when cpu_switchto() was called, 292 * and return. 293 */ 294 pop {r4-r7, ip, pc} 295 296 END(cpu_switchto) 297 298 ENTRY_NP(lwp_trampoline) 299 /* 300 * cpu_switchto gives us: 301 * arg0(r0) = old lwp 302 * arg1(r1) = new lwp 303 * setup by cpu_lwp_fork: 304 * r4 = func to call 305 * r5 = arg to func 306 * r6 = <unused> 307 * r7 = spsr mode 308 */ 309 bl _C_LABEL(lwp_startup) 310 311 mov fp, #0 /* top stack frame */ 312 mov r0, r5 313 mov r1, sp 314 #ifdef _ARM_ARCH_5 315 blx r4 316 #else 317 mov lr, pc 318 mov pc, r4 319 #endif 320 321 GET_CPSR(r0) 322 CPSID_I(r0, r0) /* Kill irq's */ 323 324 GET_CURCPU(r4) /* for DO_AST */ 325 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 326 PULLFRAME 327 328 movs pc, lr /* Exit */ 329 END(lwp_trampoline) 330 331 AST_ALIGNMENT_FAULT_LOCALS 332 333 #ifdef __HAVE_FAST_SOFTINTS 334 /* 335 * Called at IPL_HIGH 336 * r0 = new lwp 337 * r1 = ipl for softint_dispatch 338 */ 339 ENTRY_NP(softint_switch) 340 push {r4, r6, r7, lr} 341 342 ldr r7, [r0, #L_CPU] /* get curcpu */ 343 #if defined(TPIDRPRW_IS_CURLWP) 344 mrc p15, 0, r4, c13, c0, 4 /* get old lwp */ 345 #else 346 ldr r4, [r7, #(CI_CURLWP)] /* get old lwp */ 347 #endif 348 mrs r6, cpsr /* we need to save this */ 349 350 /* 351 * If the soft lwp blocks, it needs to return to softint_tramp 352 */ 353 mov r2, sp /* think ip */ 354 adr r3, softint_tramp /* think lr */ 355 push {r2-r3} 356 push {r4-r7} 357 358 mov r5, r0 /* save new lwp */ 359 360 ldr r2, [r4, #(L_PCB)] /* get old lwp's pcb */ 361 362 /* Save all the registers into the old lwp's pcb */ 363 #if defined(__XSCALE__) || defined(_ARM_ARCH_6) 364 strd r8, r9, [r2, #(PCB_R8)] 365 strd r10, r11, [r2, #(PCB_R10)] 366 strd r12, r13, [r2, #(PCB_R12)] 367 #else 368 add r3, r2, #(PCB_R8) 369 stmia r3, {r8-r13} 370 #endif 371 372 #ifdef _ARM_ARCH_6 373 /* 374 * Save user read/write thread/process id register in case it was 375 * set in userland. 376 */ 377 mrc p15, 0, r0, c13, c0, 2 378 str r0, [r2, #(PCB_USER_PID_RW)] 379 #endif 380 381 /* this is an invariant so load before disabling intrs */ 382 ldr r2, [r5, #(L_PCB)] /* get new lwp's pcb */ 383 384 IRQdisable 385 /* 386 * We're switching to a bound LWP so its l_cpu is already correct. 387 */ 388 #if defined(TPIDRPRW_IS_CURLWP) 389 mcr p15, 0, r5, c13, c0, 4 /* save new lwp */ 390 #endif 391 str r5, [r7, #(CI_CURLWP)] /* save new lwp */ 392 dmb /* see comments in kern_mutex.c */ 393 394 #ifdef KASAN 395 mov r0, r5 396 bl _C_LABEL(kasan_softint) 397 #endif 398 399 /* 400 * Normally, we'd get {r8-r13} but since this is a softint lwp 401 * its existing state doesn't matter. We start the stack just 402 * below the trapframe. 403 */ 404 ldr sp, [r5, #(L_MD_TF)] /* get new lwp's stack ptr */ 405 406 /* At this point we can allow IRQ's again. */ 407 IRQenable 408 /* r1 still has ipl */ 409 mov r0, r4 /* r0 has pinned (old) lwp */ 410 bl _C_LABEL(softint_dispatch) 411 /* 412 * If we've returned, we need to change everything back and return. 413 */ 414 ldr r2, [r4, #(L_PCB)] /* get pinned lwp's pcb */ 415 416 /* 417 * We don't need to restore all the registers since another lwp was 418 * never executed. But we do need the SP from the formerly pinned lwp. 419 */ 420 421 IRQdisable 422 #if defined(TPIDRPRW_IS_CURLWP) 423 mcr p15, 0, r4, c13, c0, 4 /* restore pinned lwp */ 424 #endif 425 str r4, [r7, #(CI_CURLWP)] /* restore pinned lwp */ 426 ldr sp, [r2, #(PCB_KSP)] /* now running on the old stack. */ 427 428 /* At this point we can allow IRQ's again. */ 429 msr cpsr_c, r6 430 431 /* 432 * Grab the registers that got pushed at the start and return. 433 */ 434 pop {r4-r7, ip, lr} /* eat switch frame */ 435 pop {r4, r6, r7, pc} /* pop stack and return */ 436 437 END(softint_switch) 438 439 /* 440 * r0 = previous LWP (the soft lwp) 441 * r4 = original LWP (the current lwp) 442 * r6 = original CPSR 443 * r7 = curcpu() 444 */ 445 ENTRY_NP(softint_tramp) 446 ldr r3, [r7, #(CI_MTX_COUNT)] /* readjust after mi_switch */ 447 add r3, r3, #1 448 str r3, [r7, #(CI_MTX_COUNT)] 449 450 msr cpsr_c, r6 /* restore interrupts */ 451 pop {r4, r6, r7, pc} /* pop stack and return */ 452 END(softint_tramp) 453 #endif /* __HAVE_FAST_SOFTINTS */ 454
Indexes created Thu Oct 23 22:10:10 GMT 2025