cpuswitch.S revision 1.3.2.13
1 /* $NetBSD: cpuswitch.S,v 1.3.2.13 2002/08/06 19:22:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpuswitch.S 40 * 41 * cpu switching functions 42 * 43 * Created : 15/10/94 44 */ 45 46 #include "opt_armfpe.h" 47 48 #include "assym.h" 49 #include <machine/param.h> 50 #include <machine/cpu.h> 51 #include <machine/frame.h> 52 #include <machine/asm.h> 53 54 #undef IRQdisable 55 #undef IRQenable 56 57 /* 58 * New experimental definitions of IRQdisable and IRQenable 59 * These keep FIQ's enabled since FIQ's are special. 60 */ 61 62 #define IRQdisable \ 63 mrs r14, cpsr_all ; \ 64 orr r14, r14, #(I32_bit) ; \ 65 msr cpsr_all, r14 ; \ 66 67 #define IRQenable \ 68 mrs r14, cpsr_all ; \ 69 bic r14, r14, #(I32_bit) ; \ 70 msr cpsr_all, r14 ; \ 71 72 /* 73 * setrunqueue() and remrunqueue() 74 * 75 * Functions to add and remove a process for the run queue. 76 */ 77 78 .text 79 80 Lwhichqs: 81 .word _C_LABEL(sched_whichqs) 82 83 Lqs: 84 .word _C_LABEL(sched_qs) 85 86 /* 87 * On entry 88 * r0 = lwp 89 */ 90 91 ENTRY(setrunqueue) 92 /* 93 * Local register usage 94 * r0 = process 95 * r1 = queue 96 * r2 = &qs[queue] and temp 97 * r3 = temp 98 * r12 = whichqs 99 */ 100 #ifdef DIAGNOSTIC 101 ldr r1, [r0, #(L_BACK)] 102 teq r1, #0x00000000 103 bne Lsetrunqueue_erg 104 105 ldr r1, [r0, #(L_WCHAN)] 106 teq r1, #0x00000000 107 bne Lsetrunqueue_erg 108 #endif 109 110 /* Get the priority of the queue */ 111 ldrb r1, [r0, #(L_PRIORITY)] 112 mov r1, r1, lsr #2 113 114 /* Indicate that there is a process on this queue */ 115 ldr r12, Lwhichqs 116 ldr r2, [r12] 117 mov r3, #0x00000001 118 mov r3, r3, lsl r1 119 orr r2, r2, r3 120 str r2, [r12] 121 122 /* Get the address of the queue */ 123 ldr r2, Lqs 124 add r1, r2, r1, lsl # 3 125 126 /* Hook the process in */ 127 str r1, [r0, #(L_FORW)] 128 ldr r2, [r1, #(L_BACK)] 129 130 str r0, [r1, #(L_BACK)] 131 #ifdef DIAGNOSTIC 132 teq r2, #0x00000000 133 beq Lsetrunqueue_erg 134 #endif 135 str r0, [r2, #(L_FORW)] 136 str r2, [r0, #(L_BACK)] 137 138 mov pc, lr 139 140 #ifdef DIAGNOSTIC 141 Lsetrunqueue_erg: 142 mov r2, r1 143 mov r1, r0 144 add r0, pc, #Ltext1 - . - 8 145 bl _C_LABEL(printf) 146 147 ldr r2, Lqs 148 ldr r1, [r2] 149 add r0, pc, #Ltext2 - . - 8 150 b _C_LABEL(panic) 151 152 Ltext1: 153 .asciz "setrunqueue : %08x %08x\n" 154 Ltext2: 155 .asciz "setrunqueue : [qs]=%08x qs=%08x\n" 156 .align 0 157 #endif 158 159 /* 160 * On entry 161 * r0 = lwp 162 */ 163 164 ENTRY(remrunqueue) 165 /* 166 * Local register usage 167 * r0 = oldproc 168 * r1 = queue 169 * r2 = &qs[queue] and scratch 170 * r3 = scratch 171 * r12 = whichqs 172 */ 173 174 /* Get the priority of the queue */ 175 ldrb r1, [r0, #(L_PRIORITY)] 176 mov r1, r1, lsr #2 177 178 /* Unhook the process */ 179 ldr r2, [r0, #(L_FORW)] 180 ldr r3, [r0, #(L_BACK)] 181 182 str r3, [r2, #(L_BACK)] 183 str r2, [r3, #(L_FORW)] 184 185 /* If the queue is now empty clear the queue not empty flag */ 186 teq r2, r3 187 188 /* This could be reworked to avoid the use of r4 */ 189 ldreq r12, Lwhichqs 190 ldreq r2, [r12] 191 moveq r3, #0x00000001 192 moveq r3, r3, lsl r1 193 biceq r2, r2, r3 194 streq r2, [r12] 195 196 /* Remove the back pointer for the process */ 197 mov r1, #0x00000000 198 str r1, [r0, #(L_BACK)] 199 200 mov pc, lr 201 202 203 /* 204 * cpuswitch() 205 * 206 * preforms a process context switch. 207 * This function has several entry points 208 */ 209 210 Lcurlwp: 211 .word _C_LABEL(curlwp) 212 213 Lcurpcb: 214 .word _C_LABEL(curpcb) 215 216 Lwant_resched: 217 .word _C_LABEL(want_resched) 218 219 Lcpufuncs: 220 .word _C_LABEL(cpufuncs) 221 222 .data 223 .global _C_LABEL(curpcb) 224 _C_LABEL(curpcb): 225 .word 0x00000000 226 .text 227 228 Lblock_userspace_access: 229 .word _C_LABEL(block_userspace_access) 230 231 /* 232 * Idle loop, exercised while waiting for a process to wake up. 233 */ 234 /* LINTSTUB: Ignore */ 235 ASENTRY_NP(idle) 236 /* Enable interrupts */ 237 IRQenable 238 239 /* XXX - r1 needs to be preserved for cpu_switch */ 240 mov r7, r1 241 ldr r3, Lcpufuncs 242 mov r0, #0 243 add lr, pc, #Lidle_slept - . - 8 244 ldr pc, [r3, #CF_SLEEP] 245 246 Lidle_slept: 247 mov r1, r7 248 249 /* Disable interrupts while we check for an active queue */ 250 IRQdisable 251 ldr r7, Lwhichqs 252 ldr r3, [r7] 253 teq r3, #0x00000000 254 bne sw1 255 256 /* All processes are still asleep so idle a while longer */ 257 b _ASM_LABEL(idle) 258 259 260 /* 261 * Find a new lwp to run, save the current context and 262 * load the new context 263 * 264 * Arguments: 265 * r0 'struct lwp *' of the current LWP 266 */ 267 268 ENTRY(cpu_switch) 269 /* 270 * Local register usage. Some of these registers are out of date. 271 * r1 = oldlwp 272 * r2 = spl level 273 * r3 = whichqs 274 * r4 = queue 275 * r5 = &qs[queue] 276 * r6 = newlwp 277 * r7 = scratch 278 */ 279 stmfd sp!, {r4-r7, lr} 280 281 /* 282 * Get the current lwp and indicate that there is no longer 283 * a valid process (curlwp = 0) 284 */ 285 ldr r7, Lcurlwp 286 ldr r1, [r7] 287 mov r0, #0x00000000 288 str r0, [r7] 289 290 /* Zero the pcb */ 291 ldr r7, Lcurpcb 292 str r0, [r7] 293 294 /* Lower the spl level to spl0 and get the current spl level. */ 295 mov r7, r1 296 297 #ifdef __NEWINTR 298 mov r0, #(IPL_NONE) 299 bl _C_LABEL(_spllower) 300 #else /* ! __NEWINTR */ 301 #ifdef spl0 302 mov r0, #(_SPL_0) 303 bl _C_LABEL(splx) 304 #else 305 bl _C_LABEL(spl0) 306 #endif /* spl0 */ 307 #endif /* __NEWINTR */ 308 309 /* Push the old spl level onto the stack */ 310 str r0, [sp, #-0x0004]! 311 312 mov r1, r7 313 314 /* First phase : find a new lwp */ 315 316 /* rem: r1 = old lwp */ 317 318 Lswitch_search: 319 IRQdisable 320 321 /* Do we have any active queues */ 322 ldr r7, Lwhichqs 323 ldr r3, [r7] 324 325 /* If not we must idle until we do. */ 326 teq r3, #0x00000000 327 beq _ASM_LABEL(idle) 328 329 sw1: 330 /* rem: r1 = old lwp */ 331 /* rem: r3 = whichqs */ 332 /* rem: interrupts are disabled */ 333 334 /* 335 * We have found an active queue. Currently we do not know which queue 336 * is active just that one of them is. 337 */ 338 /* this is the ffs algorithm devised by d.seal and posted to 339 * comp.sys.arm on 16 Feb 1994. 340 */ 341 rsb r5, r3, #0 342 ands r0, r3, r5 343 344 adr r5, Lcpu_switch_ffs_table 345 346 /* X = R0 */ 347 orr r4, r0, r0, lsl #4 /* r4 = X * 0x11 */ 348 orr r4, r4, r4, lsl #6 /* r4 = X * 0x451 */ 349 rsb r4, r4, r4, lsl #16 /* r4 = X * 0x0450fbaf */ 350 351 /* used further down, saves SA stall */ 352 ldr r6, Lqs 353 354 /* now lookup in table indexed on top 6 bits of a4 */ 355 ldrb r4, [ r5, r4, lsr #26 ] 356 357 /* rem: r0 = bit mask of chosen queue (1 << r4) */ 358 /* rem: r1 = old lwp */ 359 /* rem: r3 = whichqs */ 360 /* rem: r4 = queue number */ 361 /* rem: interrupts are disabled */ 362 363 /* Get the address of the queue (&qs[queue]) */ 364 add r5, r6, r4, lsl #3 365 366 /* 367 * Get the lwp from the queue and place the next process in 368 * the queue at the head. This basically unlinks the lwp at 369 * the head of the queue. 370 */ 371 ldr r6, [r5, #(L_FORW)] 372 373 /* rem: r6 = new lwp */ 374 ldr r7, [r6, #(L_FORW)] 375 str r7, [r5, #(L_FORW)] 376 377 /* 378 * Test to see if the queue is now empty. If the head of the queue 379 * points to the queue itself then there are no more lwps in 380 * the queue. We can therefore clear the queue not empty flag held 381 * in r3. 382 */ 383 384 teq r5, r7 385 biceq r3, r3, r0 386 387 /* rem: r0 = bit mask of chosen queue (1 << r4) - NOT NEEDED AN MORE */ 388 389 /* Fix the back pointer for the lwp now at the head of the queue. */ 390 ldr r0, [r6, #(L_BACK)] 391 str r0, [r7, #(L_BACK)] 392 393 /* Update the RAM copy of the queue not empty flags word. */ 394 ldr r7, Lwhichqs 395 str r3, [r7] 396 397 /* rem: r1 = old lwp */ 398 /* rem: r3 = whichqs - NOT NEEDED ANY MORE */ 399 /* rem: r4 = queue number - NOT NEEDED ANY MORE */ 400 /* rem: r6 = new lwp */ 401 /* rem: interrupts are disabled */ 402 403 /* Clear the want_resched flag */ 404 ldr r7, Lwant_resched 405 mov r0, #0x00000000 406 str r0, [r7] 407 408 /* 409 * Clear the back pointer of the lwp we have removed from 410 * the head of the queue. The new lwp is isolated now. 411 */ 412 str r0, [r6, #(L_BACK)] 413 414 switch_resume: 415 /* l->l_cpu initialized in fork1() for single-processor */ 416 417 /* Process is now on a processor. */ 418 mov r0, #LSONPROC /* l->l_stat = LSONPROC */ 419 str r0, [r6, #(L_STAT)] 420 421 /* We have a new curlwp now so make a note it */ 422 ldr r7, Lcurlwp 423 str r6, [r7] 424 425 /* Hook in a new pcb */ 426 ldr r7, Lcurpcb 427 ldr r0, [r6, #(L_ADDR)] 428 str r0, [r7] 429 430 /* At this point we can allow IRQ's again. */ 431 IRQenable 432 433 /* rem: r1 = old lwp */ 434 /* rem: r4 = return value */ 435 /* rem: r6 = new process */ 436 /* rem: interrupts are enabled */ 437 438 /* 439 * If the new process is the same as the process that called 440 * cpu_switch() then we do not need to save and restore any 441 * contexts. This means we can make a quick exit. 442 * The test is simple if curlwp on entry (now in r1) is the 443 * same as the proc removed from the queue we can jump to the exit. 444 */ 445 teq r1, r6 446 moveq r4, #0x00000000 /* default to "didn't switch" */ 447 beq switch_return 448 449 /* 450 * At this point, we are guaranteed to be switching to 451 * a new lwp. 452 */ 453 mov r4, #0x00000001 454 455 /* Remember the old lwp in r0 */ 456 mov r0, r1 457 458 /* 459 * If the old lwp on entry to cpu_switch was zero then the 460 * process that called it was exiting. This means that we do 461 * not need to save the current context. Instead we can jump 462 * straight to restoring the context for the new process. 463 */ 464 teq r0, #0x00000000 465 beq switch_exited 466 467 /* rem: r0 = old lwp */ 468 /* rem: r4 = return value */ 469 /* rem: r6 = new process */ 470 /* rem: interrupts are enabled */ 471 472 /* Stage two : Save old context */ 473 474 /* Get the user structure for the old lwp. */ 475 ldr r1, [r0, #(L_ADDR)] 476 477 /* Save all the registers in the old lwp's pcb */ 478 add r7, r1, #(PCB_R8) 479 stmia r7, {r8-r13} 480 481 /* 482 * This can be optimised... We know we want to go from SVC32 483 * mode to UND32 mode 484 */ 485 mrs r3, cpsr_all 486 bic r2, r3, #(PSR_MODE) 487 orr r2, r2, #(PSR_UND32_MODE | I32_bit) 488 msr cpsr_all, r2 489 490 str sp, [r1, #(PCB_UND_SP)] 491 492 msr cpsr_all, r3 /* Restore the old mode */ 493 494 /* rem: r0 = old lwp */ 495 /* rem: r1 = old pcb */ 496 /* rem: r4 = return value */ 497 /* rem: r6 = new process */ 498 /* rem: interrupts are enabled */ 499 500 /* What else needs to be saved Only FPA stuff when that is supported */ 501 502 /* r1 now free! */ 503 504 /* Third phase : restore saved context */ 505 506 /* rem: r0 = old lwp */ 507 /* rem: r4 = return value */ 508 /* rem: r6 = new lwp */ 509 /* rem: interrupts are enabled */ 510 511 /* 512 * Don't allow user space access between the purge and the switch. 513 */ 514 ldr r3, Lblock_userspace_access 515 mov r1, #0x00000001 516 mov r2, #0x00000000 517 str r1, [r3] 518 519 stmfd sp!, {r0-r3} 520 ldr r1, Lcpufuncs 521 add lr, pc, #Lcs_cache_purged - . - 8 522 ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] 523 524 Lcs_cache_purged: 525 ldmfd sp!, {r0-r3} 526 527 Lcs_cache_purge_skipped: 528 /* At this point we need to kill IRQ's again. */ 529 IRQdisable 530 531 /* 532 * Interrupts are disabled so we can allow user space accesses again 533 * as none will occur until interrupts are re-enabled after the 534 * switch. 535 */ 536 str r2, [r3] 537 538 /* Get the user structure for the new process in r1 */ 539 ldr r1, [r6, #(L_ADDR)] 540 541 /* Get the pagedir physical address for the process. */ 542 ldr r0, [r1, #(PCB_PAGEDIR)] 543 544 /* Switch the memory to the new process */ 545 ldr r3, Lcpufuncs 546 add lr, pc, #Lcs_context_switched - . - 8 547 ldr pc, [r3, #CF_CONTEXT_SWITCH] 548 549 Lcs_context_switched: 550 /* 551 * This can be optimised... We know we want to go from SVC32 552 * mode to UND32 mode 553 */ 554 mrs r3, cpsr_all 555 bic r2, r3, #(PSR_MODE) 556 orr r2, r2, #(PSR_UND32_MODE) 557 msr cpsr_all, r2 558 559 ldr sp, [r1, #(PCB_UND_SP)] 560 561 msr cpsr_all, r3 /* Restore the old mode */ 562 563 /* Restore all the save registers */ 564 add r7, r1, #PCB_R8 565 ldmia r7, {r8-r13} 566 567 #ifdef ARMFPE 568 add r0, r1, #(USER_SIZE) & 0x00ff 569 add r0, r0, #(USER_SIZE) & 0xff00 570 bl _C_LABEL(arm_fpe_core_changecontext) 571 #endif 572 573 /* We can enable interrupts again */ 574 IRQenable 575 576 switch_return: 577 578 /* Get the spl level from the stack and update the current spl level */ 579 ldr r0, [sp], #0x0004 580 bl _C_LABEL(splx) 581 582 /* cpu_switch returns 1 == switched, 0 == didn't switch */ 583 mov r0, r4 584 585 /* 586 * Pull the registers that got pushed when either savectx() or 587 * cpu_switch() was called and return. 588 */ 589 ldmfd sp!, {r4-r7, pc} 590 591 switch_exited: 592 /* 593 * We skip the cache purge because switch_exit()/switch_lwp_exit() 594 * already did it. Load up registers the way Lcs_cache_purge_skipped 595 * expects. Userpsace access already blocked by switch_exit()/ 596 * switch_lwp_exit(). 597 */ 598 ldr r3, Lblock_userspace_access 599 mov r2, #0x00000000 600 b Lcs_cache_purge_skipped 601 602 /* 603 * cpu_preempt(struct lwp *current, struct lwp *next) 604 * Switch to the specified next LWP 605 * Arguments: 606 * 607 * r0 'struct lwp *' of the current LWP 608 * r1 'struct lwp *' of the LWP to switch to 609 */ 610 ENTRY(cpu_preempt) 611 stmfd sp!, {r4-r7, lr} 612 613 /* Lower the spl level to spl0 and get the current spl level. */ 614 mov r6, r0 /* save old lwp */ 615 mov r7, r1 /* save new lwp */ 616 617 #ifdef __NEWINTR 618 mov r0, #(IPL_NONE) 619 bl _C_LABEL(_spllower) 620 #else /* ! __NEWINTR */ 621 #ifdef spl0 622 mov r0, #(_SPL_0) 623 bl _C_LABEL(splx) 624 #else 625 bl _C_LABEL(spl0) 626 #endif /* spl0 */ 627 #endif /* __NEWINTR */ 628 629 /* Push the old spl level onto the stack */ 630 str r0, [sp, #-0x0004]! 631 632 mov r0, r6 /* restore old lwp */ 633 mov r1, r7 /* restore new lwp */ 634 635 /* rem: r1 = new lwp */ 636 637 IRQdisable 638 639 /* Do we have any active queues? */ 640 ldr r7, Lwhichqs 641 ldr r3, [r7] 642 643 /* If none, panic! */ 644 teq r3, #0x00000000 645 beq preempt_noqueues 646 647 /* rem: r0 = old lwp */ 648 /* rem: r1 = new lwp */ 649 /* rem: r3 = whichqs */ 650 /* rem: r7 = &whichqs */ 651 /* rem: interrupts are disabled */ 652 653 /* Compute the queue bit corresponding to the new lwp. */ 654 ldrb r4, [r1, #(L_PRIORITY)] 655 mov r2, #0x00000001 656 mov r4, r4, lsr #2 /* queue number */ 657 mov r2, r2, lsl r4 /* queue bit */ 658 659 /* rem: r0 = old lwp */ 660 /* rem: r1 = new lwp */ 661 /* rem: r2 = queue bit */ 662 /* rem: r3 = whichqs */ 663 /* rem: r4 = queue number */ 664 /* rem: r7 = &whichqs */ 665 666 /* 667 * Unlink the lwp from the queue. 668 */ 669 ldr r5, [r1, #(L_BACK)] /* r5 = l->l_back */ 670 mov r6, #0x00000000 671 str r6, [r1, #(L_BACK)] /* firewall: l->l_back = NULL */ 672 ldr r6, [r1, #(L_FORW)] /* r6 = l->l_forw */ 673 str r5, [r6, #(L_BACK)] /* r6->l_back = r5 */ 674 str r6, [r5, #(L_FORW)] /* r5->l_forw = r6 */ 675 676 teq r5, r6 /* see if queue is empty */ 677 biceq r3, r3, r2 /* clear bit if so */ 678 streq r3, [r7] /* store it back if so */ 679 680 /* rem: r2 (queue bit) now free */ 681 /* rem: r3 (whichqs) now free */ 682 /* rem: r7 (&whichqs) now free */ 683 684 /* 685 * Okay, set up registers the way cpu_switch() wants them, 686 * and jump into the middle of it (where we bring up the 687 * new process). 688 */ 689 mov r6, r1 /* r6 = new lwp */ 690 mov r1, r0 /* r1 = old lwp */ 691 b switch_resume 692 693 preempt_noqueues: 694 add r0, pc, #preemptpanic - . - 8 695 bl _C_LABEL(panic) 696 697 preemptpanic: 698 .asciz "cpu_preempt: whichqs empty" 699 .align 0 700 701 Llwp0: 702 .word _C_LABEL(lwp0) 703 704 Lkernel_map: 705 .word _C_LABEL(kernel_map) 706 707 /* 708 * void switch_exit(struct lwp *l, struct lwp *l0); 709 * Switch to lwp0's saved context and deallocate the address space and kernel 710 * stack for l. Then jump into cpu_switch(), as if we were in lwp0 all along. 711 */ 712 713 /* LINTSTUB: Func: void switch_exit(struct lwp *l, struct lwp *l0) */ 714 ENTRY(switch_exit) 715 /* 716 * r0 = lwp 717 * r1 = lwp0 718 */ 719 720 mov r3, r0 721 722 /* In case we fault */ 723 ldr r0, Lcurlwp 724 mov r2, #0x00000000 725 str r2, [r0] 726 727 /* ldr r0, Lcurpcb 728 str r2, [r0]*/ 729 730 /* 731 * Don't allow user space access between the purge and the switch. 732 */ 733 ldr r0, Lblock_userspace_access 734 mov r2, #0x00000001 735 str r2, [r0] 736 737 /* Switch to lwp0 context */ 738 739 stmfd sp!, {r0-r3} 740 741 ldr r0, Lcpufuncs 742 add lr, pc, #Lse_cache_purged - . - 8 743 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] 744 745 Lse_cache_purged: 746 ldmfd sp!, {r0-r3} 747 748 IRQdisable 749 750 ldr r2, [r1, #(L_ADDR)] 751 ldr r0, [r2, #(PCB_PAGEDIR)] 752 753 /* Switch the memory to the new process */ 754 ldr r4, Lcpufuncs 755 add lr, pc, #Lse_context_switched - . - 8 756 ldr pc, [r4, #CF_CONTEXT_SWITCH] 757 758 Lse_context_switched: 759 /* Restore all the save registers */ 760 add r7, r2, #PCB_R8 761 ldmia r7, {r8-r13} 762 763 /* This is not really needed ! */ 764 /* Yes it is for the su and fu routines */ 765 ldr r0, Lcurpcb 766 str r2, [r0] 767 768 IRQenable 769 770 /* str r3, [sp, #-0x0004]!*/ 771 772 /* 773 * Schedule the vmspace and stack to be freed. 774 */ 775 mov r0, r3 /* exit2(l) */ 776 bl _C_LABEL(exit2) 777 778 /* Paranoia */ 779 mov r0, #0x00000000 780 ldr r1, Lcurlwp 781 str r0, [r1] 782 783 mov r1, #0x00000000 /* r1 = old lwp = NULL */ 784 b Lswitch_search 785 786 /* 787 * void switch_lwp_exit(struct lwp *l, struct lwp *l0); 788 * Switch to lwp0's saved context and deallocate the address space and kernel 789 * stack for l. Then jump into cpu_switch(), as if we were in lwp0 all along. 790 */ 791 792 /* LINTSTUB: Func: void switch_exit(struct lwp *l, struct lwp *l0) */ 793 ENTRY(switch_lwp_exit) 794 /* 795 * r0 = lwp 796 * r1 = lwp0 797 */ 798 799 mov r3, r0 800 801 /* In case we fault */ 802 mov r2, #0x00000000 803 ldr r0, Lcurlwp 804 str r2, [r0] 805 806 /* ldr r0, Lcurpcb 807 str r2, [r0]*/ 808 809 /* 810 * Don't allow user space access between the purge and the switch. 811 */ 812 ldr r0, Lblock_userspace_access 813 mov r2, #0x00000001 814 str r2, [r0] 815 816 /* Switch to lwp0 context */ 817 818 stmfd sp!, {r0-r3} 819 820 ldr r0, Lcpufuncs 821 add lr, pc, #Lsle_cache_purged - . - 8 822 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] 823 824 Lsle_cache_purged: 825 ldmfd sp!, {r0-r3} 826 827 IRQdisable 828 829 ldr r2, [r1, #(L_ADDR)] 830 ldr r0, [r2, #(PCB_PAGEDIR)] 831 832 /* Switch the memory to the new process */ 833 ldr r4, Lcpufuncs 834 add lr, pc, #Lsle_context_switched - . - 8 835 ldr pc, [r4, #CF_CONTEXT_SWITCH] 836 837 Lsle_context_switched: 838 /* Restore all the save registers */ 839 add r7, r2, #PCB_R8 840 ldmia r7, {r8-r13} 841 842 /* This is not really needed ! */ 843 /* Yes it is for the su and fu routines */ 844 ldr r0, Lcurpcb 845 str r2, [r0] 846 847 IRQenable 848 849 /* str r3, [sp, #-0x0004]!*/ 850 851 /* 852 * Schedule the vmspace and stack to be freed. 853 */ 854 mov r0, r3 /* lwp_exit2(l) */ 855 bl _C_LABEL(lwp_exit2) 856 857 /* Paranoia */ 858 ldr r1, Lcurlwp 859 mov r0, #0x00000000 860 str r0, [r1] 861 862 mov r1, #0x00000000 /* r1 = old lwp = NULL */ 863 b Lswitch_search 864 865 /* LINTSTUB: Func: void savectx(struct pcb *pcb) */ 866 ENTRY(savectx) 867 /* 868 * r0 = pcb 869 */ 870 871 /* Push registers.*/ 872 stmfd sp!, {r4-r7, lr} 873 874 /* Store all the registers in the process's pcb */ 875 add r2, r0, #(PCB_R8) 876 stmia r2, {r8-r13} 877 878 /* Pull the regs of the stack */ 879 ldmfd sp!, {r4-r7, pc} 880 881 ENTRY(proc_trampoline) 882 add lr, pc, #(trampoline_return - . - 8) 883 mov r0, r5 884 mov r1, sp 885 mov pc, r4 886 887 trampoline_return: 888 /* Kill irq's */ 889 mrs r0, cpsr_all 890 orr r0, r0, #(I32_bit) 891 msr cpsr_all, r0 892 893 PULLFRAME 894 895 movs pc, lr /* Exit */ 896 897 .type Lcpu_switch_ffs_table, _ASM_TYPE_OBJECT; 898 Lcpu_switch_ffs_table: 899 /* same as ffs table but all nums are -1 from that */ 900 /* 0 1 2 3 4 5 6 7 */ 901 .byte 0, 0, 1, 12, 2, 6, 0, 13 /* 0- 7 */ 902 .byte 3, 0, 7, 0, 0, 0, 0, 14 /* 8-15 */ 903 .byte 10, 4, 0, 0, 8, 0, 0, 25 /* 16-23 */ 904 .byte 0, 0, 0, 0, 0, 21, 27, 15 /* 24-31 */ 905 .byte 31, 11, 5, 0, 0, 0, 0, 0 /* 32-39 */ 906 .byte 9, 0, 0, 24, 0, 0, 20, 26 /* 40-47 */ 907 .byte 30, 0, 0, 0, 0, 23, 0, 19 /* 48-55 */ 908 .byte 29, 0, 22, 18, 28, 17, 16, 0 /* 56-63 */ 909 910 /* End of cpuswitch.S */ 911
Indexes created Sun Oct 26 13:09:57 GMT 2025