cpuswitch.S revision 1.3.2.17
1 /* $NetBSD: cpuswitch.S,v 1.3.2.17 2002/08/12 20:34:50 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpuswitch.S 40 * 41 * cpu switching functions 42 * 43 * Created : 15/10/94 44 */ 45 46 #include "opt_armfpe.h" 47 48 #include "assym.h" 49 #include <machine/param.h> 50 #include <machine/cpu.h> 51 #include <machine/frame.h> 52 #include <machine/asm.h> 53 54 #undef IRQdisable 55 #undef IRQenable 56 57 /* 58 * New experimental definitions of IRQdisable and IRQenable 59 * These keep FIQ's enabled since FIQ's are special. 60 */ 61 62 #define IRQdisable \ 63 mrs r14, cpsr_all ; \ 64 orr r14, r14, #(I32_bit) ; \ 65 msr cpsr_all, r14 ; \ 66 67 #define IRQenable \ 68 mrs r14, cpsr_all ; \ 69 bic r14, r14, #(I32_bit) ; \ 70 msr cpsr_all, r14 ; \ 71 72 /* 73 * setrunqueue() and remrunqueue() 74 * 75 * Functions to add and remove a process for the run queue. 76 */ 77 78 .text 79 80 Lwhichqs: 81 .word _C_LABEL(sched_whichqs) 82 83 Lqs: 84 .word _C_LABEL(sched_qs) 85 86 /* 87 * On entry 88 * r0 = lwp 89 */ 90 91 ENTRY(setrunqueue) 92 /* 93 * Local register usage 94 * r0 = process 95 * r1 = queue 96 * r2 = &qs[queue] and temp 97 * r3 = temp 98 * r12 = whichqs 99 */ 100 #ifdef DIAGNOSTIC 101 ldr r1, [r0, #(L_BACK)] 102 teq r1, #0x00000000 103 bne Lsetrunqueue_erg 104 105 ldr r1, [r0, #(L_WCHAN)] 106 teq r1, #0x00000000 107 bne Lsetrunqueue_erg 108 #endif 109 110 /* Get the priority of the queue */ 111 ldrb r1, [r0, #(L_PRIORITY)] 112 mov r1, r1, lsr #2 113 114 /* Indicate that there is a process on this queue */ 115 ldr r12, Lwhichqs 116 ldr r2, [r12] 117 mov r3, #0x00000001 118 mov r3, r3, lsl r1 119 orr r2, r2, r3 120 str r2, [r12] 121 122 /* Get the address of the queue */ 123 ldr r2, Lqs 124 add r1, r2, r1, lsl # 3 125 126 /* Hook the process in */ 127 str r1, [r0, #(L_FORW)] 128 ldr r2, [r1, #(L_BACK)] 129 130 str r0, [r1, #(L_BACK)] 131 #ifdef DIAGNOSTIC 132 teq r2, #0x00000000 133 beq Lsetrunqueue_erg 134 #endif 135 str r0, [r2, #(L_FORW)] 136 str r2, [r0, #(L_BACK)] 137 138 mov pc, lr 139 140 #ifdef DIAGNOSTIC 141 Lsetrunqueue_erg: 142 mov r2, r1 143 mov r1, r0 144 add r0, pc, #Ltext1 - . - 8 145 bl _C_LABEL(printf) 146 147 ldr r2, Lqs 148 ldr r1, [r2] 149 add r0, pc, #Ltext2 - . - 8 150 b _C_LABEL(panic) 151 152 Ltext1: 153 .asciz "setrunqueue : %08x %08x\n" 154 Ltext2: 155 .asciz "setrunqueue : [qs]=%08x qs=%08x\n" 156 .align 0 157 #endif 158 159 /* 160 * On entry 161 * r0 = lwp 162 */ 163 164 ENTRY(remrunqueue) 165 /* 166 * Local register usage 167 * r0 = oldproc 168 * r1 = queue 169 * r2 = &qs[queue] and scratch 170 * r3 = scratch 171 * r12 = whichqs 172 */ 173 174 /* Get the priority of the queue */ 175 ldrb r1, [r0, #(L_PRIORITY)] 176 mov r1, r1, lsr #2 177 178 /* Unhook the process */ 179 ldr r2, [r0, #(L_FORW)] 180 ldr r3, [r0, #(L_BACK)] 181 182 str r3, [r2, #(L_BACK)] 183 str r2, [r3, #(L_FORW)] 184 185 /* If the queue is now empty clear the queue not empty flag */ 186 teq r2, r3 187 188 /* This could be reworked to avoid the use of r4 */ 189 ldreq r12, Lwhichqs 190 ldreq r2, [r12] 191 moveq r3, #0x00000001 192 moveq r3, r3, lsl r1 193 biceq r2, r2, r3 194 streq r2, [r12] 195 196 /* Remove the back pointer for the process */ 197 mov r1, #0x00000000 198 str r1, [r0, #(L_BACK)] 199 200 mov pc, lr 201 202 203 /* 204 * cpuswitch() 205 * 206 * preforms a process context switch. 207 * This function has several entry points 208 */ 209 210 Lcurlwp: 211 .word _C_LABEL(curlwp) 212 213 Lcurpcb: 214 .word _C_LABEL(curpcb) 215 216 Lwant_resched: 217 .word _C_LABEL(want_resched) 218 219 Lcpufuncs: 220 .word _C_LABEL(cpufuncs) 221 222 .data 223 .global _C_LABEL(curpcb) 224 _C_LABEL(curpcb): 225 .word 0x00000000 226 .text 227 228 Lblock_userspace_access: 229 .word _C_LABEL(block_userspace_access) 230 231 /* 232 * Idle loop, exercised while waiting for a process to wake up. 233 */ 234 /* LINTSTUB: Ignore */ 235 ASENTRY_NP(idle) 236 /* Enable interrupts */ 237 IRQenable 238 239 ldr r3, Lcpufuncs 240 mov r0, #0 241 add lr, pc, #Lidle_slept - . - 8 242 ldr pc, [r3, #CF_SLEEP] 243 244 Lidle_slept: 245 246 /* Disable interrupts while we check for an active queue */ 247 IRQdisable 248 ldr r7, Lwhichqs 249 ldr r3, [r7] 250 teq r3, #0x00000000 251 252 beq _ASM_LABEL(idle) 253 b Lidle_ret 254 255 /* 256 * Find a new lwp to run, save the current context and 257 * load the new context 258 * 259 * Arguments: 260 * r0 'struct lwp *' of the current LWP 261 */ 262 263 ENTRY(cpu_switch) 264 /* 265 * Local register usage. Some of these registers are out of date. 266 * r1 = oldlwp 267 * r2 = spl level 268 * r3 = whichqs 269 * r4 = queue 270 * r5 = &qs[queue] 271 * r6 = newlwp 272 * r7 = scratch 273 */ 274 stmfd sp!, {r4-r7, lr} 275 276 /* 277 * Get the current lwp and indicate that there is no longer 278 * a valid process (curlwp = 0) 279 */ 280 ldr r7, Lcurlwp 281 ldr r1, [r7] 282 mov r0, #0x00000000 283 str r0, [r7] 284 285 /* Zero the pcb */ 286 ldr r7, Lcurpcb 287 str r0, [r7] 288 289 /* stash the old proc while we call functions */ 290 mov r5, r1 291 292 /* Lower the spl level to spl0 and get the current spl level. */ 293 #ifdef __NEWINTR 294 mov r0, #(IPL_NONE) 295 bl _C_LABEL(_spllower) 296 #else /* ! __NEWINTR */ 297 #ifdef spl0 298 mov r0, #(_SPL_0) 299 bl _C_LABEL(splx) 300 #else 301 bl _C_LABEL(spl0) 302 #endif /* spl0 */ 303 #endif /* __NEWINTR */ 304 305 /* Push the old spl level onto the stack */ 306 str r0, [sp, #-0x0004]! 307 308 /* First phase : find a new lwp */ 309 310 /* rem: r5 = old lwp */ 311 312 Lswitch_search: 313 IRQdisable 314 315 /* Do we have any active queues */ 316 ldr r7, Lwhichqs 317 ldr r3, [r7] 318 319 /* If not we must idle until we do. */ 320 teq r3, #0x00000000 321 beq _ASM_LABEL(idle) 322 Lidle_ret: 323 324 /* put old proc back in r1 */ 325 mov r1, r5 326 327 /* rem: r1 = old lwp */ 328 /* rem: r3 = whichqs */ 329 /* rem: interrupts are disabled */ 330 331 /* 332 * We have found an active queue. Currently we do not know which queue 333 * is active just that one of them is. 334 */ 335 /* this is the ffs algorithm devised by d.seal and posted to 336 * comp.sys.arm on 16 Feb 1994. 337 */ 338 rsb r5, r3, #0 339 ands r0, r3, r5 340 341 adr r5, Lcpu_switch_ffs_table 342 343 /* X = R0 */ 344 orr r4, r0, r0, lsl #4 /* r4 = X * 0x11 */ 345 orr r4, r4, r4, lsl #6 /* r4 = X * 0x451 */ 346 rsb r4, r4, r4, lsl #16 /* r4 = X * 0x0450fbaf */ 347 348 /* used further down, saves SA stall */ 349 ldr r6, Lqs 350 351 /* now lookup in table indexed on top 6 bits of a4 */ 352 ldrb r4, [ r5, r4, lsr #26 ] 353 354 /* rem: r0 = bit mask of chosen queue (1 << r4) */ 355 /* rem: r1 = old lwp */ 356 /* rem: r3 = whichqs */ 357 /* rem: r4 = queue number */ 358 /* rem: interrupts are disabled */ 359 360 /* Get the address of the queue (&qs[queue]) */ 361 add r5, r6, r4, lsl #3 362 363 /* 364 * Get the lwp from the queue and place the next process in 365 * the queue at the head. This basically unlinks the lwp at 366 * the head of the queue. 367 */ 368 ldr r6, [r5, #(L_FORW)] 369 370 /* rem: r6 = new lwp */ 371 ldr r7, [r6, #(L_FORW)] 372 str r7, [r5, #(L_FORW)] 373 374 /* 375 * Test to see if the queue is now empty. If the head of the queue 376 * points to the queue itself then there are no more lwps in 377 * the queue. We can therefore clear the queue not empty flag held 378 * in r3. 379 */ 380 381 teq r5, r7 382 biceq r3, r3, r0 383 384 /* rem: r0 = bit mask of chosen queue (1 << r4) - NOT NEEDED AN MORE */ 385 386 /* Fix the back pointer for the lwp now at the head of the queue. */ 387 ldr r0, [r6, #(L_BACK)] 388 str r0, [r7, #(L_BACK)] 389 390 /* Update the RAM copy of the queue not empty flags word. */ 391 ldr r7, Lwhichqs 392 str r3, [r7] 393 394 /* rem: r1 = old lwp */ 395 /* rem: r3 = whichqs - NOT NEEDED ANY MORE */ 396 /* rem: r4 = queue number - NOT NEEDED ANY MORE */ 397 /* rem: r6 = new lwp */ 398 /* rem: interrupts are disabled */ 399 400 /* Clear the want_resched flag */ 401 ldr r7, Lwant_resched 402 mov r0, #0x00000000 403 str r0, [r7] 404 405 /* 406 * Clear the back pointer of the lwp we have removed from 407 * the head of the queue. The new lwp is isolated now. 408 */ 409 str r0, [r6, #(L_BACK)] 410 411 switch_resume: 412 /* l->l_cpu initialized in fork1() for single-processor */ 413 414 /* Process is now on a processor. */ 415 mov r0, #LSONPROC /* l->l_stat = LSONPROC */ 416 str r0, [r6, #(L_STAT)] 417 418 /* We have a new curlwp now so make a note it */ 419 ldr r7, Lcurlwp 420 str r6, [r7] 421 422 /* Hook in a new pcb */ 423 ldr r7, Lcurpcb 424 ldr r0, [r6, #(L_ADDR)] 425 str r0, [r7] 426 427 /* At this point we can allow IRQ's again. */ 428 IRQenable 429 430 /* rem: r1 = old lwp */ 431 /* rem: r4 = return value */ 432 /* rem: r6 = new process */ 433 /* rem: interrupts are enabled */ 434 435 /* 436 * If the new process is the same as the process that called 437 * cpu_switch() then we do not need to save and restore any 438 * contexts. This means we can make a quick exit. 439 * The test is simple if curlwp on entry (now in r1) is the 440 * same as the proc removed from the queue we can jump to the exit. 441 */ 442 teq r1, r6 443 moveq r4, #0x00000000 /* default to "didn't switch" */ 444 beq switch_return 445 446 /* 447 * At this point, we are guaranteed to be switching to 448 * a new lwp. 449 */ 450 mov r4, #0x00000001 451 452 /* Remember the old lwp in r0 */ 453 mov r0, r1 454 455 /* 456 * If the old lwp on entry to cpu_switch was zero then the 457 * process that called it was exiting. This means that we do 458 * not need to save the current context. Instead we can jump 459 * straight to restoring the context for the new process. 460 */ 461 teq r0, #0x00000000 462 beq switch_exited 463 464 /* rem: r0 = old lwp */ 465 /* rem: r4 = return value */ 466 /* rem: r6 = new process */ 467 /* rem: interrupts are enabled */ 468 469 /* Stage two : Save old context */ 470 471 /* Get the user structure for the old lwp. */ 472 ldr r1, [r0, #(L_ADDR)] 473 474 /* Save all the registers in the old lwp's pcb */ 475 add r7, r1, #(PCB_R8) 476 stmia r7, {r8-r13} 477 478 /* 479 * This can be optimised... We know we want to go from SVC32 480 * mode to UND32 mode 481 */ 482 mrs r3, cpsr_all 483 bic r2, r3, #(PSR_MODE) 484 orr r2, r2, #(PSR_UND32_MODE | I32_bit) 485 msr cpsr_all, r2 486 487 str sp, [r1, #(PCB_UND_SP)] 488 489 msr cpsr_all, r3 /* Restore the old mode */ 490 491 /* rem: r0 = old lwp */ 492 /* rem: r1 = old pcb */ 493 /* rem: r4 = return value */ 494 /* rem: r6 = new process */ 495 /* rem: interrupts are enabled */ 496 497 /* What else needs to be saved Only FPA stuff when that is supported */ 498 499 /* r1 now free! */ 500 501 /* Third phase : restore saved context */ 502 503 /* rem: r0 = old lwp */ 504 /* rem: r4 = return value */ 505 /* rem: r6 = new lwp */ 506 /* rem: interrupts are enabled */ 507 508 /* 509 * Don't allow user space access between the purge and the switch. 510 */ 511 ldr r3, Lblock_userspace_access 512 mov r1, #0x00000001 513 mov r2, #0x00000000 514 str r1, [r3] 515 516 stmfd sp!, {r0-r3} 517 ldr r1, Lcpufuncs 518 add lr, pc, #Lcs_cache_purged - . - 8 519 ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] 520 521 Lcs_cache_purged: 522 ldmfd sp!, {r0-r3} 523 524 Lcs_cache_purge_skipped: 525 /* At this point we need to kill IRQ's again. */ 526 IRQdisable 527 528 /* 529 * Interrupts are disabled so we can allow user space accesses again 530 * as none will occur until interrupts are re-enabled after the 531 * switch. 532 */ 533 str r2, [r3] 534 535 /* Get the user structure for the new process in r1 */ 536 ldr r1, [r6, #(L_ADDR)] 537 538 /* Get the pagedir physical address for the process. */ 539 ldr r0, [r1, #(PCB_PAGEDIR)] 540 541 /* Switch the memory to the new process */ 542 ldr r3, Lcpufuncs 543 add lr, pc, #Lcs_context_switched - . - 8 544 ldr pc, [r3, #CF_CONTEXT_SWITCH] 545 546 Lcs_context_switched: 547 /* 548 * This can be optimised... We know we want to go from SVC32 549 * mode to UND32 mode 550 */ 551 mrs r3, cpsr_all 552 bic r2, r3, #(PSR_MODE) 553 orr r2, r2, #(PSR_UND32_MODE) 554 msr cpsr_all, r2 555 556 ldr sp, [r1, #(PCB_UND_SP)] 557 558 msr cpsr_all, r3 /* Restore the old mode */ 559 560 /* Restore all the save registers */ 561 add r7, r1, #PCB_R8 562 ldmia r7, {r8-r13} 563 564 #ifdef ARMFPE 565 add r0, r1, #(USER_SIZE) & 0x00ff 566 add r0, r0, #(USER_SIZE) & 0xff00 567 bl _C_LABEL(arm_fpe_core_changecontext) 568 #endif 569 570 /* We can enable interrupts again */ 571 IRQenable 572 573 switch_return: 574 575 /* Get the spl level from the stack and update the current spl level */ 576 ldr r0, [sp], #0x0004 577 bl _C_LABEL(splx) 578 579 /* cpu_switch returns 1 == switched, 0 == didn't switch */ 580 mov r0, r4 581 582 /* 583 * Pull the registers that got pushed when either savectx() or 584 * cpu_switch() was called and return. 585 */ 586 ldmfd sp!, {r4-r7, pc} 587 588 switch_exited: 589 /* 590 * We skip the cache purge because switch_exit()/switch_lwp_exit() 591 * already did it. Load up registers the way Lcs_cache_purge_skipped 592 * expects. Userpsace access already blocked by switch_exit()/ 593 * switch_lwp_exit(). 594 */ 595 ldr r3, Lblock_userspace_access 596 mov r2, #0x00000000 597 b Lcs_cache_purge_skipped 598 599 /* 600 * cpu_preempt(struct lwp *current, struct lwp *next) 601 * Switch to the specified next LWP 602 * Arguments: 603 * 604 * r0 'struct lwp *' of the current LWP 605 * r1 'struct lwp *' of the LWP to switch to 606 */ 607 ENTRY(cpu_preempt) 608 stmfd sp!, {r4-r7, lr} 609 610 /* Lower the spl level to spl0 and get the current spl level. */ 611 mov r6, r0 /* save old lwp */ 612 mov r5, r1 /* save new lwp */ 613 614 #ifdef __NEWINTR 615 mov r0, #(IPL_NONE) 616 bl _C_LABEL(_spllower) 617 #else /* ! __NEWINTR */ 618 #ifdef spl0 619 mov r0, #(_SPL_0) 620 bl _C_LABEL(splx) 621 #else 622 bl _C_LABEL(spl0) 623 #endif /* spl0 */ 624 #endif /* __NEWINTR */ 625 626 /* Push the old spl level onto the stack */ 627 str r0, [sp, #-0x0004]! 628 629 IRQdisable 630 631 /* Do we have any active queues? */ 632 ldr r7, Lwhichqs 633 ldr r3, [r7] 634 635 /* If none, panic! */ 636 teq r3, #0x00000000 637 beq preempt_noqueues 638 639 mov r0, r6 /* restore old lwp */ 640 mov r1, r5 /* restore new lwp */ 641 642 /* rem: r0 = old lwp */ 643 /* rem: r1 = new lwp */ 644 /* rem: r3 = whichqs */ 645 /* rem: r7 = &whichqs */ 646 /* rem: interrupts are disabled */ 647 648 /* Compute the queue bit corresponding to the new lwp. */ 649 ldrb r4, [r1, #(L_PRIORITY)] 650 mov r2, #0x00000001 651 mov r4, r4, lsr #2 /* queue number */ 652 mov r2, r2, lsl r4 /* queue bit */ 653 654 /* rem: r0 = old lwp */ 655 /* rem: r1 = new lwp */ 656 /* rem: r2 = queue bit */ 657 /* rem: r3 = whichqs */ 658 /* rem: r4 = queue number */ 659 /* rem: r7 = &whichqs */ 660 661 /* 662 * Unlink the lwp from the queue. 663 */ 664 ldr r5, [r1, #(L_BACK)] /* r5 = l->l_back */ 665 mov r6, #0x00000000 666 str r6, [r1, #(L_BACK)] /* firewall: l->l_back = NULL */ 667 ldr r6, [r1, #(L_FORW)] /* r6 = l->l_forw */ 668 str r5, [r6, #(L_BACK)] /* r6->l_back = r5 */ 669 str r6, [r5, #(L_FORW)] /* r5->l_forw = r6 */ 670 671 teq r5, r6 /* see if queue is empty */ 672 biceq r3, r3, r2 /* clear bit if so */ 673 streq r3, [r7] /* store it back if so */ 674 675 /* rem: r2 (queue bit) now free */ 676 /* rem: r3 (whichqs) now free */ 677 /* rem: r7 (&whichqs) now free */ 678 679 /* 680 * Okay, set up registers the way cpu_switch() wants them, 681 * and jump into the middle of it (where we bring up the 682 * new process). 683 */ 684 mov r6, r1 /* r6 = new lwp */ 685 mov r1, r0 /* r1 = old lwp */ 686 b switch_resume 687 688 preempt_noqueues: 689 add r0, pc, #preemptpanic - . - 8 690 bl _C_LABEL(panic) 691 692 preemptpanic: 693 .asciz "cpu_preempt: whichqs empty" 694 .align 0 695 696 Llwp0: 697 .word _C_LABEL(lwp0) 698 699 Lkernel_map: 700 .word _C_LABEL(kernel_map) 701 702 /* 703 * void switch_exit(struct lwp *l, struct lwp *l0); 704 * Switch to lwp0's saved context and deallocate the address space and kernel 705 * stack for l. Then jump into cpu_switch(), as if we were in lwp0 all along. 706 */ 707 708 /* LINTSTUB: Func: void switch_exit(struct lwp *l, struct lwp *l0) */ 709 ENTRY(switch_exit) 710 /* 711 * r0 = lwp 712 * r1 = lwp0 713 */ 714 715 mov r3, r0 716 717 /* In case we fault */ 718 ldr r0, Lcurlwp 719 mov r2, #0x00000000 720 str r2, [r0] 721 722 /* ldr r0, Lcurpcb 723 str r2, [r0]*/ 724 725 /* 726 * Don't allow user space access between the purge and the switch. 727 */ 728 ldr r0, Lblock_userspace_access 729 mov r2, #0x00000001 730 str r2, [r0] 731 732 /* Switch to lwp0 context */ 733 734 stmfd sp!, {r0-r3} 735 736 ldr r0, Lcpufuncs 737 add lr, pc, #Lse_cache_purged - . - 8 738 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] 739 740 Lse_cache_purged: 741 ldmfd sp!, {r0-r3} 742 743 IRQdisable 744 745 ldr r2, [r1, #(L_ADDR)] 746 ldr r0, [r2, #(PCB_PAGEDIR)] 747 748 /* Switch the memory to the new process */ 749 ldr r4, Lcpufuncs 750 add lr, pc, #Lse_context_switched - . - 8 751 ldr pc, [r4, #CF_CONTEXT_SWITCH] 752 753 Lse_context_switched: 754 /* Restore all the save registers */ 755 add r7, r2, #PCB_R8 756 ldmia r7, {r8-r13} 757 758 /* This is not really needed ! */ 759 /* Yes it is for the su and fu routines */ 760 ldr r0, Lcurpcb 761 str r2, [r0] 762 763 IRQenable 764 765 /* str r3, [sp, #-0x0004]!*/ 766 767 /* 768 * Schedule the vmspace and stack to be freed. 769 */ 770 mov r0, r3 /* exit2(l) */ 771 bl _C_LABEL(exit2) 772 773 /* Paranoia */ 774 mov r0, #0x00000000 775 ldr r1, Lcurlwp 776 str r0, [r1] 777 778 mov r5, #0x00000000 /* r5 = old lwp = NULL */ 779 b Lswitch_search 780 781 /* 782 * void switch_lwp_exit(struct lwp *l, struct lwp *l0); 783 * Switch to lwp0's saved context and deallocate the address space and kernel 784 * stack for l. Then jump into cpu_switch(), as if we were in lwp0 all along. 785 */ 786 787 /* LINTSTUB: Func: void switch_exit(struct lwp *l, struct lwp *l0) */ 788 ENTRY(switch_lwp_exit) 789 /* 790 * r0 = lwp 791 * r1 = lwp0 792 */ 793 794 mov r3, r0 795 796 /* In case we fault */ 797 mov r2, #0x00000000 798 ldr r0, Lcurlwp 799 str r2, [r0] 800 801 /* ldr r0, Lcurpcb 802 str r2, [r0]*/ 803 804 /* 805 * Don't allow user space access between the purge and the switch. 806 */ 807 ldr r0, Lblock_userspace_access 808 mov r2, #0x00000001 809 str r2, [r0] 810 811 /* Switch to lwp0 context */ 812 813 stmfd sp!, {r0-r3} 814 815 ldr r0, Lcpufuncs 816 add lr, pc, #Lsle_cache_purged - . - 8 817 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] 818 819 Lsle_cache_purged: 820 ldmfd sp!, {r0-r3} 821 822 IRQdisable 823 824 ldr r2, [r1, #(L_ADDR)] 825 ldr r0, [r2, #(PCB_PAGEDIR)] 826 827 /* Switch the memory to the new process */ 828 ldr r4, Lcpufuncs 829 add lr, pc, #Lsle_context_switched - . - 8 830 ldr pc, [r4, #CF_CONTEXT_SWITCH] 831 832 Lsle_context_switched: 833 /* Restore all the save registers */ 834 add r7, r2, #PCB_R8 835 ldmia r7, {r8-r13} 836 837 /* This is not really needed ! */ 838 /* Yes it is for the su and fu routines */ 839 ldr r0, Lcurpcb 840 str r2, [r0] 841 842 IRQenable 843 844 /* str r3, [sp, #-0x0004]!*/ 845 846 /* 847 * Schedule the vmspace and stack to be freed. 848 */ 849 mov r0, r3 /* lwp_exit2(l) */ 850 bl _C_LABEL(lwp_exit2) 851 852 /* Paranoia */ 853 ldr r1, Lcurlwp 854 mov r0, #0x00000000 855 str r0, [r1] 856 857 mov r5, #0x00000000 /* r5 = old lwp = NULL */ 858 b Lswitch_search 859 860 /* LINTSTUB: Func: void savectx(struct pcb *pcb) */ 861 ENTRY(savectx) 862 /* 863 * r0 = pcb 864 */ 865 866 /* Push registers.*/ 867 stmfd sp!, {r4-r7, lr} 868 869 /* Store all the registers in the process's pcb */ 870 add r2, r0, #(PCB_R8) 871 stmia r2, {r8-r13} 872 873 /* Pull the regs of the stack */ 874 ldmfd sp!, {r4-r7, pc} 875 876 ENTRY(proc_trampoline) 877 add lr, pc, #(trampoline_return - . - 8) 878 mov r0, r5 879 mov r1, sp 880 mov pc, r4 881 882 trampoline_return: 883 /* Kill irq's */ 884 mrs r0, cpsr_all 885 orr r0, r0, #(I32_bit) 886 msr cpsr_all, r0 887 888 PULLFRAME 889 890 movs pc, lr /* Exit */ 891 892 .type Lcpu_switch_ffs_table, _ASM_TYPE_OBJECT; 893 Lcpu_switch_ffs_table: 894 /* same as ffs table but all nums are -1 from that */ 895 /* 0 1 2 3 4 5 6 7 */ 896 .byte 0, 0, 1, 12, 2, 6, 0, 13 /* 0- 7 */ 897 .byte 3, 0, 7, 0, 0, 0, 0, 14 /* 8-15 */ 898 .byte 10, 4, 0, 0, 8, 0, 0, 25 /* 16-23 */ 899 .byte 0, 0, 0, 0, 0, 21, 27, 15 /* 24-31 */ 900 .byte 31, 11, 5, 0, 0, 0, 0, 0 /* 32-39 */ 901 .byte 9, 0, 0, 24, 0, 0, 20, 26 /* 40-47 */ 902 .byte 30, 0, 0, 0, 0, 23, 0, 19 /* 48-55 */ 903 .byte 29, 0, 22, 18, 28, 17, 16, 0 /* 56-63 */ 904 905 /* End of cpuswitch.S */ 906
Indexes created Sun Oct 26 13:09:57 GMT 2025