cpuswitch.S revision 1.3.2.4
1 /* $NetBSD: cpuswitch.S,v 1.3.2.4 2002/01/08 00:23:08 nathanw Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpuswitch.S 40 * 41 * cpu switching functions 42 * 43 * Created : 15/10/94 44 */ 45 46 #include "opt_armfpe.h" 47 48 #include "assym.h" 49 #include <machine/param.h> 50 #include <machine/cpu.h> 51 #include <machine/frame.h> 52 #include <machine/asm.h> 53 54 #undef IRQdisable 55 #undef IRQenable 56 57 /* 58 * New experimental definitions of IRQdisable and IRQenable 59 * These keep FIQ's enabled since FIQ's are special. 60 */ 61 62 #define IRQdisable \ 63 mrs r14, cpsr_all ; \ 64 orr r14, r14, #(I32_bit) ; \ 65 msr cpsr_all, r14 ; \ 66 67 #define IRQenable \ 68 mrs r14, cpsr_all ; \ 69 bic r14, r14, #(I32_bit) ; \ 70 msr cpsr_all, r14 ; \ 71 72 /* 73 * setrunqueue() and remrunqueue() 74 * 75 * Functions to add and remove a process for the run queue. 76 */ 77 78 .text 79 80 Lwhichqs: 81 .word _C_LABEL(sched_whichqs) 82 83 Lqs: 84 .word _C_LABEL(sched_qs) 85 86 /* 87 * On entry 88 * r0 = lwp 89 */ 90 91 ENTRY(setrunqueue) 92 /* 93 * Local register usage 94 * r0 = process 95 * r1 = queue 96 * r2 = &qs[queue] and temp 97 * r3 = temp 98 * r12 = whichqs 99 */ 100 #ifdef DIAGNOSTIC 101 ldr r1, [r0, #(L_BACK)] 102 teq r1, #0x00000000 103 bne Lsetrunqueue_erg 104 105 ldr r1, [r0, #(L_WCHAN)] 106 teq r1, #0x00000000 107 bne Lsetrunqueue_erg 108 #endif 109 110 /* Get the priority of the queue */ 111 ldrb r1, [r0, #(L_PRIORITY)] 112 mov r1, r1, lsr #2 113 114 /* Indicate that there is a process on this queue */ 115 ldr r12, Lwhichqs 116 ldr r2, [r12] 117 mov r3, #0x00000001 118 mov r3, r3, lsl r1 119 orr r2, r2, r3 120 str r2, [r12] 121 122 /* Get the address of the queue */ 123 ldr r2, Lqs 124 add r1, r2, r1, lsl # 3 125 126 /* Hook the process in */ 127 str r1, [r0, #(L_FORW)] 128 ldr r2, [r1, #(L_BACK)] 129 130 str r0, [r1, #(L_BACK)] 131 #ifdef DIAGNOSTIC 132 teq r2, #0x00000000 133 beq Lsetrunqueue_erg 134 #endif 135 str r0, [r2, #(L_FORW)] 136 str r2, [r0, #(L_BACK)] 137 138 mov pc, lr 139 140 #ifdef DIAGNOSTIC 141 Lsetrunqueue_erg: 142 mov r2, r1 143 mov r1, r0 144 add r0, pc, #Ltext1 - . - 8 145 bl _C_LABEL(printf) 146 147 ldr r2, Lqs 148 ldr r1, [r2] 149 add r0, pc, #Ltext2 - . - 8 150 b _C_LABEL(panic) 151 152 Ltext1: 153 .asciz "setrunqueue : %08x %08x\n" 154 Ltext2: 155 .asciz "setrunqueue : [qs]=%08x qs=%08x\n" 156 .align 0 157 #endif 158 159 /* 160 * On entry 161 * r0 = lwp 162 */ 163 164 ENTRY(remrunqueue) 165 /* 166 * Local register usage 167 * r0 = oldproc 168 * r1 = queue 169 * r2 = &qs[queue] and scratch 170 * r3 = scratch 171 * r12 = whichqs 172 */ 173 174 /* Get the priority of the queue */ 175 ldrb r1, [r0, #(L_PRIORITY)] 176 mov r1, r1, lsr #2 177 178 /* Unhook the process */ 179 ldr r2, [r0, #(L_FORW)] 180 ldr r3, [r0, #(L_BACK)] 181 182 str r3, [r2, #(L_BACK)] 183 str r2, [r3, #(L_FORW)] 184 185 /* If the queue is now empty clear the queue not empty flag */ 186 teq r2, r3 187 188 /* This could be reworked to avoid the use of r4 */ 189 ldreq r12, Lwhichqs 190 ldreq r2, [r12] 191 moveq r3, #0x00000001 192 moveq r3, r3, lsl r1 193 biceq r2, r2, r3 194 streq r2, [r12] 195 196 /* Remove the back pointer for the process */ 197 mov r1, #0x00000000 198 str r1, [r0, #(L_BACK)] 199 200 mov pc, lr 201 202 203 /* 204 * cpuswitch() 205 * 206 * preforms a process context switch. 207 * This function has several entry points 208 */ 209 210 Lcurproc: 211 .word _C_LABEL(curproc) 212 213 Lcurpcb: 214 .word _C_LABEL(curpcb) 215 216 Lwant_resched: 217 .word _C_LABEL(want_resched) 218 219 Lcpufuncs: 220 .word _C_LABEL(cpufuncs) 221 222 .data 223 .global _C_LABEL(curpcb) 224 _C_LABEL(curpcb): 225 .word 0x00000000 226 .text 227 228 Lblock_userspace_access: 229 .word _C_LABEL(block_userspace_access) 230 231 /* 232 * Idle loop, exercised while waiting for a process to wake up. 233 */ 234 ASENTRY_NP(idle) 235 /* Enable interrupts */ 236 IRQenable 237 238 /* XXX - r1 needs to be preserved for cpu_switch */ 239 mov r7, r1 240 ldr r3, Lcpufuncs 241 mov r0, #0 242 add lr, pc, #Lidle_slept - . - 8 243 ldr pc, [r3, #CF_SLEEP] 244 245 Lidle_slept: 246 mov r1, r7 247 248 /* Disable interrupts while we check for an active queue */ 249 IRQdisable 250 ldr r7, Lwhichqs 251 ldr r3, [r7] 252 teq r3, #0x00000000 253 bne sw1 254 255 /* All processes are still asleep so idle a while longer */ 256 b _ASM_LABEL(idle) 257 258 259 /* 260 * Find a new lwp to run, save the current context and 261 * load the new context 262 * 263 * Arguments: 264 * r0 'struct lwp *' of the current LWP 265 */ 266 267 ENTRY(cpu_switch) 268 /* 269 * Local register usage. Some of these registers are out of date. 270 * r1 = oldlwp 271 * r2 = spl level 272 * r3 = whichqs 273 * r4 = queue 274 * r5 = &qs[queue] 275 * r6 = newlwp 276 * r7 = scratch 277 */ 278 stmfd sp!, {r4-r7, lr} 279 280 /* 281 * Get the current lwp and indicate that there is no longer 282 * a valid process (curproc = 0) 283 */ 284 ldr r7, Lcurproc 285 ldr r1, [r7] 286 mov r0, #0x00000000 287 str r0, [r7] 288 289 /* Zero the pcb */ 290 ldr r7, Lcurpcb 291 str r0, [r7] 292 293 /* Lower the spl level to spl0 and get the current spl level. */ 294 mov r7, r1 295 296 #ifdef __NEWINTR 297 mov r0, #(IPL_NONE) 298 bl _C_LABEL(_spllower) 299 #else /* ! __NEWINTR */ 300 #ifdef spl0 301 mov r0, #(_SPL_0) 302 bl _C_LABEL(splx) 303 #else 304 bl _C_LABEL(spl0) 305 #endif /* spl0 */ 306 #endif /* __NEWINTR */ 307 308 /* Push the old spl level onto the stack */ 309 str r0, [sp, #-0x0004]! 310 311 mov r1, r7 312 313 /* First phase : find a new lwp */ 314 315 /* rem: r1 = old proc */ 316 317 switch_search: 318 IRQdisable 319 320 /* Do we have any active queues */ 321 ldr r7, Lwhichqs 322 ldr r3, [r7] 323 324 /* If not we must idle until we do. */ 325 teq r3, #0x00000000 326 beq _ASM_LABEL(idle) 327 328 sw1: 329 /* rem: r1 = old lwp */ 330 /* rem: r3 = whichqs */ 331 /* rem: interrupts are disabled */ 332 333 /* 334 * We have found an active queue. Currently we do not know which queue 335 * is active just that one of them is. 336 */ 337 /* this is the ffs algorithm devised by d.seal and posted to 338 * comp.sys.arm on 16 Feb 1994. 339 */ 340 rsb r5, r3, #0 341 ands r0, r3, r5 342 343 adr r5, Lcpu_switch_ffs_table 344 345 /* X = R0 */ 346 orr r4, r0, r0, lsl #4 /* r4 = X * 0x11 */ 347 orr r4, r4, r4, lsl #6 /* r4 = X * 0x451 */ 348 rsb r4, r4, r4, lsl #16 /* r4 = X * 0x0450fbaf */ 349 350 /* used further down, saves SA stall */ 351 ldr r6, Lqs 352 353 /* now lookup in table indexed on top 6 bits of a4 */ 354 ldrb r4, [ r5, r4, lsr #26 ] 355 356 /* rem: r0 = bit mask of chosen queue (1 << r4) */ 357 /* rem: r1 = old lwp */ 358 /* rem: r3 = whichqs */ 359 /* rem: r4 = queue number */ 360 /* rem: interrupts are disabled */ 361 362 /* Get the address of the queue (&qs[queue]) */ 363 add r5, r6, r4, lsl #3 364 365 /* 366 * Get the lwp from the queue and place the next process in 367 * the queue at the head. This basically unlinks the lwp at 368 * the head of the queue. 369 */ 370 ldr r6, [r5, #(L_FORW)] 371 372 /* rem: r6 = new lwp */ 373 ldr r7, [r6, #(L_FORW)] 374 str r7, [r5, #(L_FORW)] 375 376 /* 377 * Test to see if the queue is now empty. If the head of the queue 378 * points to the queue itself then there are no more lwps in 379 * the queue. We can therefore clear the queue not empty flag held 380 * in r3. 381 */ 382 383 teq r5, r7 384 biceq r3, r3, r0 385 386 /* rem: r0 = bit mask of chosen queue (1 << r4) - NOT NEEDED AN MORE */ 387 388 /* Fix the back pointer for the lwp now at the head of the queue. */ 389 ldr r0, [r6, #(L_BACK)] 390 str r0, [r7, #(L_BACK)] 391 392 /* Update the RAM copy of the queue not empty flags word. */ 393 ldr r7, Lwhichqs 394 str r3, [r7] 395 396 /* rem: r1 = old lwp */ 397 /* rem: r3 = whichqs - NOT NEEDED ANY MORE */ 398 /* rem: r4 = queue number - NOT NEEDED ANY MORE */ 399 /* rem: r6 = new lwp */ 400 /* rem: interrupts are disabled */ 401 402 /* Clear the want_resched flag */ 403 ldr r7, Lwant_resched 404 mov r0, #0x00000000 405 str r0, [r7] 406 407 /* 408 * Clear the back pointer of the lwp we have removed from 409 * the head of the queue. The new lwp is isolated now. 410 */ 411 str r0, [r6, #(L_BACK)] 412 413 switch_resume: 414 /* l->l_cpu initialized in fork1() for single-processor */ 415 416 /* Process is now on a processor. */ 417 mov r0, #LSONPROC /* l->l_stat = LSONPROC */ 418 str r0, [r6, #(L_STAT)] 419 420 /* We have a new curproc now so make a note it */ 421 ldr r7, Lcurproc 422 str r6, [r7] 423 424 /* Hook in a new pcb */ 425 ldr r7, Lcurpcb 426 ldr r0, [r6, #(L_ADDR)] 427 str r0, [r7] 428 429 /* At this point we can allow IRQ's again. */ 430 IRQenable 431 432 /* rem: r1 = old lwp */ 433 /* rem: r4 = return value */ 434 /* rem: r6 = new process */ 435 /* rem: interrupts are enabled */ 436 437 /* 438 * If the new process is the same as the process that called 439 * cpu_switch() then we do not need to save and restore any 440 * contexts. This means we can make a quick exit. 441 * The test is simple if curproc on entry (now in r1) is the 442 * same as the proc removed from the queue we can jump to the exit. 443 */ 444 teq r1, r6 445 moveq r4, #0x00000000 /* default to "didn't switch" */ 446 beq switch_return 447 448 /* 449 * At this point, we are guaranteed to be switching to 450 * a new lwp. 451 */ 452 mov r4, #0x00000001 453 454 /* 455 * If the curproc on entry to cpu_switch was zero then the 456 * process that called it was exiting. This means that we do 457 * not need to save the current context. Instead we can jump 458 * straight to restoring the context for the new process. 459 */ 460 teq r1, #0x00000000 461 beq switch_exited 462 463 /* rem: r1 = old proc */ 464 /* rem: r4 = return value */ 465 /* rem: r6 = new process */ 466 /* rem: interrupts are enabled */ 467 468 /* Stage two : Save old context */ 469 470 /* Remember the old process in r0 */ 471 mov r0, r1 472 473 /* Get the user structure for the old process. */ 474 ldr r1, [r1, #(L_ADDR)] 475 476 /* Save all the registers in the old process's pcb */ 477 add r7, r1, #(PCB_R8) 478 stmia r7, {r8-r13} 479 480 /* 481 * This can be optimised... We know we want to go from SVC32 482 * mode to UND32 mode 483 */ 484 mrs r3, cpsr_all 485 bic r2, r3, #(PSR_MODE) 486 orr r2, r2, #(PSR_UND32_MODE | I32_bit) 487 msr cpsr_all, r2 488 489 str sp, [r1, #(PCB_UND_SP)] 490 491 msr cpsr_all, r3 /* Restore the old mode */ 492 493 /* rem: r0 = old proc */ 494 /* rem: r1 = old pcb */ 495 /* rem: r4 = return value */ 496 /* rem: r6 = new process */ 497 /* rem: interrupts are enabled */ 498 499 /* What else needs to be saved Only FPA stuff when that is supported */ 500 501 /* Third phase : restore saved context */ 502 503 switch_exited: 504 /* Don't allow user space access beween the purge and the switch */ 505 ldr r3, Lblock_userspace_access 506 ldr r2, [r3] 507 orr r0, r2, #1 508 str r0, [r3] 509 510 stmfd sp!, {r0-r3} 511 ldr r0, Lcpufuncs 512 add lr, pc, #Lcs_cache_purged - . - 8 513 ldr pc, [r0, #CF_CACHE_PURGE_ID] 514 515 Lcs_cache_purged: 516 ldmfd sp!, {r0-r3} 517 518 /* At this point we need to kill IRQ's again. */ 519 IRQdisable 520 521 /* Interrupts are disabled so we can allow user space accesses again 522 * as none will occur until interrupts are re-enabled after the 523 * switch. 524 */ 525 str r2, [r3] 526 527 /* Get the user structure for the new process in r1 */ 528 ldr r1, [r6, #(L_ADDR)] 529 530 /* Get the pagedir physical address for the process. */ 531 ldr r0, [r1, #(PCB_PAGEDIR)] 532 533 /* Switch the memory to the new process */ 534 ldr r3, Lcpufuncs 535 add lr, pc, #Lcs_context_switched - . - 8 536 ldr pc, [r3, #CF_CONTEXT_SWITCH] 537 538 Lcs_context_switched: 539 /* 540 * This can be optimised... We know we want to go from SVC32 541 * mode to UND32 mode 542 */ 543 mrs r3, cpsr_all 544 bic r2, r3, #(PSR_MODE) 545 orr r2, r2, #(PSR_UND32_MODE) 546 msr cpsr_all, r2 547 548 ldr sp, [r1, #(PCB_UND_SP)] 549 550 msr cpsr_all, r3 /* Restore the old mode */ 551 552 /* Restore all the save registers */ 553 add r7, r1, #PCB_R8 554 ldmia r7, {r8-r13} 555 556 #ifdef ARMFPE 557 add r0, r1, #(USER_SIZE) & 0x00ff 558 add r0, r0, #(USER_SIZE) & 0xff00 559 bl _C_LABEL(arm_fpe_core_changecontext) 560 #endif 561 562 /* We can enable interrupts again */ 563 IRQenable 564 565 switch_return: 566 567 /* Get the spl level from the stack and update the current spl level */ 568 ldr r0, [sp], #0x0004 569 bl _C_LABEL(splx) 570 571 /* cpu_switch returns 1 == switched, 0 == didn't switch */ 572 mov r0, r4 573 574 /* 575 * Pull the registers that got pushed when either savectx() or 576 * cpu_switch() was called and return. 577 */ 578 ldmfd sp!, {r4-r7, pc} 579 580 /* 581 * cpu_preempt(struct lwp *current, struct lwp *next) 582 * Switch to the specified next LWP 583 * Arguments: 584 * 585 * r0 'struct lwp *' of the current LWP 586 * r1 'struct lwp *' of the LWP to switch to 587 */ 588 ENTRY(cpu_preempt) 589 stmfd sp!, {r4-r7, lr} 590 591 /* Lower the spl level to spl0 and get the current spl level. */ 592 mov r6, r0 /* save old lwp */ 593 mov r7, r1 /* save new lwp */ 594 595 #ifdef spl0 596 mov r0, #(_SPL_0) 597 bl _C_LABEL(splx) 598 #else 599 bl _C_LABEL(spl0) 600 #endif 601 602 /* Push the old spl level onto the stack */ 603 str r0, [sp, #-0x0004]! 604 605 mov r0, r6 /* restore old lwp */ 606 mov r1, r7 /* restore new lwp */ 607 608 /* rem: r1 = new lwp */ 609 610 IRQdisable 611 612 /* Do we have any active queues? */ 613 ldr r7, Lwhichqs 614 ldr r3, [r7] 615 616 /* If none, panic! */ 617 teq r3, #0x00000000 618 beq preempt_noqueues 619 620 /* rem: r0 = old lwp */ 621 /* rem: r1 = new lwp */ 622 /* rem: r3 = whichqs */ 623 /* rem: r7 = &whichqs */ 624 /* rem: interrupts are disabled */ 625 626 /* Compute the queue bit corresponding to the new lwp. */ 627 ldrb r4, [r1, #(L_PRIORITY)] 628 mov r2, #0x00000001 629 mov r4, r4, lsr #2 /* queue number */ 630 mov r2, r2, lsl r4 /* queue bit */ 631 632 /* rem: r0 = old lwp */ 633 /* rem: r1 = new lwp */ 634 /* rem: r2 = queue bit */ 635 /* rem: r3 = whichqs */ 636 /* rem: r4 = queue number */ 637 /* rem: r7 = &whichqs */ 638 639 /* 640 * Unlink the lwp from the queue. 641 */ 642 ldr r5, [r1, #(L_BACK)] /* r5 = l->l_back */ 643 mov r6, #0x00000000 644 str r6, [r1, #(L_BACK)] /* firewall: l->l_back = NULL */ 645 ldr r6, [r1, #(L_FORW)] /* r6 = l->l_forw */ 646 str r5, [r6, #(L_BACK)] /* r6->l_back = r5 */ 647 str r6, [r5, #(L_FORW)] /* r5->l_forw = r6 */ 648 649 teq r5, r6 /* see if queue is empty */ 650 biceq r3, r3, r2 /* clear bit if so */ 651 streq r3, [r7] /* store it back if so */ 652 653 /* rem: r2 (queue bit) now free */ 654 /* rem: r3 (whichqs) now free */ 655 /* rem: r7 (&whichqs) now free */ 656 657 /* 658 * Okay, set up registers the way cpu_switch() wants them, 659 * and jump into the middle of it (where we bring up the 660 * new process). 661 */ 662 mov r6, r1 /* r6 = new lwp */ 663 mov r1, r0 /* r1 = old lwp */ 664 b switch_resume 665 666 preempt_noqueues: 667 add r0, pc, #preemptpanic - . - 8 668 bl _C_LABEL(panic) 669 670 preemptpanic: 671 .asciz "cpu_preempt: whichqs empty" 672 .align 0 673 674 Llwp0: 675 .word _C_LABEL(lwp0) 676 677 Lkernel_map: 678 .word _C_LABEL(kernel_map) 679 680 681 ENTRY(switch_exit) 682 /* 683 * r0 = lwp 684 * r1 = lwp0 685 */ 686 687 mov r3, r0 688 ldr r1, Llwp0 689 690 /* In case we fault */ 691 ldr r0, Lcurproc 692 mov r2, #0x00000000 693 str r2, [r0] 694 695 /* ldr r0, Lcurpcb 696 str r2, [r0]*/ 697 698 /* Switch to lwp0 context */ 699 700 stmfd sp!, {r0-r3} 701 702 ldr r0, Lcpufuncs 703 add lr, pc, #Lse_cache_purged - . - 8 704 ldr pc, [r0, #CF_CACHE_PURGE_ID] 705 706 Lse_cache_purged: 707 ldmfd sp!, {r0-r3} 708 709 IRQdisable 710 711 ldr r2, [r1, #(L_ADDR)] 712 ldr r0, [r2, #(PCB_PAGEDIR)] 713 714 /* Switch the memory to the new process */ 715 ldr r4, Lcpufuncs 716 add lr, pc, #Lse_context_switched - . - 8 717 ldr pc, [r4, #CF_CONTEXT_SWITCH] 718 719 Lse_context_switched: 720 /* Restore all the save registers */ 721 add r7, r2, #PCB_R8 722 ldmia r7, {r8-r13} 723 724 /* This is not really needed ! */ 725 /* Yes it is for the su and fu routines */ 726 ldr r0, Lcurpcb 727 str r2, [r0] 728 729 IRQenable 730 731 /* str r3, [sp, #-0x0004]!*/ 732 733 /* 734 * Schedule the vmspace and stack to be freed. 735 */ 736 mov r0, r3 /* exit2(l) */ 737 bl _C_LABEL(exit2) 738 739 /* Paranoia */ 740 mov r0, #0x00000000 741 ldr r1, Lcurproc 742 str r0, [r1] 743 744 ldr r1, Llwp0 745 b switch_search 746 747 ENTRY(switch_lwp_exit) 748 /* 749 * r0 = lwp 750 * r1 = lwp0 751 */ 752 753 mov r3, r0 754 ldr r1, Llwp0 755 756 /* In case we fault */ 757 mov r2, #0x00000000 758 ldr r0, Lcurproc 759 str r2, [r0] 760 761 /* ldr r0, Lcurpcb 762 str r2, [r0]*/ 763 764 /* Switch to lwp0 context */ 765 766 stmfd sp!, {r0-r3} 767 768 ldr r0, Lcpufuncs 769 add lr, pc, #Lsle_cache_purged - . - 8 770 ldr pc, [r0, #CF_CACHE_PURGE_ID] 771 772 Lsle_cache_purged: 773 ldmfd sp!, {r0-r3} 774 775 IRQdisable 776 777 ldr r2, [r1, #(L_ADDR)] 778 ldr r0, [r2, #(PCB_PAGEDIR)] 779 780 /* Switch the memory to the new process */ 781 ldr r4, Lcpufuncs 782 add lr, pc, #Lsle_context_switched - . - 8 783 ldr pc, [r4, #CF_CONTEXT_SWITCH] 784 785 Lsle_context_switched: 786 /* Restore all the save registers */ 787 add r7, r2, #PCB_R8 788 ldmia r7, {r8-r13} 789 790 /* This is not really needed ! */ 791 /* Yes it is for the su and fu routines */ 792 ldr r0, Lcurpcb 793 str r2, [r0] 794 795 IRQenable 796 797 /* str r3, [sp, #-0x0004]!*/ 798 799 /* 800 * Schedule the vmspace and stack to be freed. 801 */ 802 mov r0, r3 /* lwp_exit2(l) */ 803 bl _C_LABEL(lwp_exit2) 804 805 /* Paranoia */ 806 ldr r1, Lcurproc 807 mov r0, #0x00000000 808 str r0, [r1] 809 810 ldr r1, Llwp0 811 b switch_search 812 813 ENTRY(savectx) 814 /* 815 * r0 = pcb 816 */ 817 818 /* Push registers.*/ 819 stmfd sp!, {r4-r7, lr} 820 821 /* Store all the registers in the process's pcb */ 822 add r2, r0, #(PCB_R8) 823 stmia r2, {r8-r13} 824 825 /* Pull the regs of the stack */ 826 ldmfd sp!, {r4-r7, pc} 827 828 ENTRY(proc_trampoline) 829 add lr, pc, #(trampoline_return - . - 8) 830 mov r0, r5 831 mov r1, sp 832 mov pc, r4 833 834 trampoline_return: 835 /* Kill irq's */ 836 mrs r0, cpsr_all 837 orr r0, r0, #(I32_bit) 838 msr cpsr_all, r0 839 840 PULLFRAME 841 842 movs pc, lr /* Exit */ 843 844 .type Lcpu_switch_ffs_table, _ASM_TYPE_OBJECT; 845 Lcpu_switch_ffs_table: 846 /* same as ffs table but all nums are -1 from that */ 847 /* 0 1 2 3 4 5 6 7 */ 848 .byte 0, 0, 1, 12, 2, 6, 0, 13 /* 0- 7 */ 849 .byte 3, 0, 7, 0, 0, 0, 0, 14 /* 8-15 */ 850 .byte 10, 4, 0, 0, 8, 0, 0, 25 /* 16-23 */ 851 .byte 0, 0, 0, 0, 0, 21, 27, 15 /* 24-31 */ 852 .byte 31, 11, 5, 0, 0, 0, 0, 0 /* 32-39 */ 853 .byte 9, 0, 0, 24, 0, 0, 20, 26 /* 40-47 */ 854 .byte 30, 0, 0, 0, 0, 23, 0, 19 /* 48-55 */ 855 .byte 29, 0, 22, 18, 28, 17, 16, 0 /* 56-63 */ 856 857 /* End of cpuswitch.S */ 858
Indexes created Sat Oct 25 16:10:12 GMT 2025