cpuswitch.S revision 1.46.12.3
1 /* $NetBSD: cpuswitch.S,v 1.46.12.3 2007/10/03 19:22:36 garbled Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 */ 79 80 #include "opt_armfpe.h" 81 #include "opt_arm32_pmap.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_lockdebug.h" 84 85 #include "assym.h" 86 #include <arm/arm32/pte.h> 87 #include <machine/param.h> 88 #include <machine/cpu.h> 89 #include <machine/frame.h> 90 #include <machine/asm.h> 91 92 /* LINTSTUB: include <sys/param.h> */ 93 94 #undef IRQdisable 95 #undef IRQenable 96 97 /* 98 * New experimental definitions of IRQdisable and IRQenable 99 * These keep FIQ's enabled since FIQ's are special. 100 */ 101 102 #define IRQdisable \ 103 mrs r14, cpsr ; \ 104 orr r14, r14, #(I32_bit) ; \ 105 msr cpsr_c, r14 ; \ 106 107 #define IRQenable \ 108 mrs r14, cpsr ; \ 109 bic r14, r14, #(I32_bit) ; \ 110 msr cpsr_c, r14 ; \ 111 112 /* 113 * These are used for switching the translation table/DACR. 114 * Since the vector page can be invalid for a short time, we must 115 * disable both regular IRQs *and* FIQs. 116 * 117 * XXX: This is not necessary if the vector table is relocated. 118 */ 119 #define IRQdisableALL \ 120 mrs r14, cpsr ; \ 121 orr r14, r14, #(I32_bit | F32_bit) ; \ 122 msr cpsr_c, r14 123 124 #define IRQenableALL \ 125 mrs r14, cpsr ; \ 126 bic r14, r14, #(I32_bit | F32_bit) ; \ 127 msr cpsr_c, r14 128 129 .text 130 131 #ifdef MULTIPROCESSOR 132 .Lcpu_info_store: 133 .word _C_LABEL(cpu_info_store) 134 .Lcurlwp: 135 /* FIXME: This is bogus in the general case. */ 136 .word _C_LABEL(cpu_info_store) + CI_CURLWP 137 138 .Lcurpcb: 139 .word _C_LABEL(cpu_info_store) + CI_CURPCB 140 #else 141 .Lcurlwp: 142 .word _C_LABEL(curlwp) 143 144 .Lcurpcb: 145 .word _C_LABEL(curpcb) 146 #endif 147 148 .Lcpufuncs: 149 .word _C_LABEL(cpufuncs) 150 151 #ifndef MULTIPROCESSOR 152 .data 153 .global _C_LABEL(curpcb) 154 _C_LABEL(curpcb): 155 .word 0x00000000 156 .text 157 #endif 158 159 .Lblock_userspace_access: 160 .word _C_LABEL(block_userspace_access) 161 162 163 /* 164 * struct lwp * 165 * cpu_switchto(struct lwp *current, struct lwp *next) 166 * 167 * Switch to the specified next LWP 168 * Arguments: 169 * 170 * r0 'struct lwp *' of the current LWP 171 * r1 'struct lwp *' of the LWP to switch to 172 */ 173 ENTRY(cpu_switchto) 174 stmfd sp!, {r4-r7, lr} 175 176 mov r6, r1 /* save new lwp */ 177 mov r4, r0 /* save old lwp, it's the return value */ 178 179 IRQdisable 180 181 #ifdef MULTIPROCESSOR 182 /* XXX use curcpu() */ 183 ldr r0, .Lcpu_info_store 184 str r0, [r6, #(L_CPU)] 185 #else 186 /* l->l_cpu initialized in fork1() for single-processor */ 187 #endif 188 189 /* We have a new curlwp now so make a note it */ 190 ldr r7, .Lcurlwp 191 str r6, [r7] 192 193 /* Hook in a new pcb */ 194 ldr r7, .Lcurpcb 195 ldr r0, [r6, #(L_ADDR)] 196 str r0, [r7] 197 198 /* At this point we can allow IRQ's again. */ 199 IRQenable 200 201 /* rem: r4 = old lwp */ 202 /* rem: r6 = new lwp */ 203 /* rem: interrupts are enabled */ 204 205 /* 206 * If the old lwp on entry to cpu_switchto was zero then the 207 * process that called it was exiting. This means that we do 208 * not need to save the current context. Instead we can jump 209 * straight to restoring the context for the new process. 210 */ 211 teq r4, #0x00000000 212 ldreq r9, [r6, #(L_ADDR)] 213 beq .Ldo_switch 214 215 /* rem: r4 = old lwp */ 216 /* rem: r6 = new lwp */ 217 /* rem: interrupts are enabled */ 218 219 /* Save old context */ 220 221 /* Get the user structure for the old lwp. */ 222 ldr r1, [r4, #(L_ADDR)] 223 224 /* Save all the registers in the old lwp's pcb */ 225 #ifndef __XSCALE__ 226 add r7, r1, #(PCB_R8) 227 stmia r7, {r8-r13} 228 #else 229 strd r8, [r1, #(PCB_R8)] 230 strd r10, [r1, #(PCB_R10)] 231 strd r12, [r1, #(PCB_R12)] 232 #endif 233 234 /* 235 * NOTE: We can now use r8-r13 until it is time to restore 236 * them for the new process. 237 */ 238 239 /* rem: r1 = old lwp PCB */ 240 /* rem: r4 = old lwp */ 241 /* rem: r6 = new lwp */ 242 /* rem: interrupts are enabled */ 243 244 /* Remember the old PCB. */ 245 mov r8, r1 246 247 /* r1 now free! */ 248 249 /* Get the user structure for the new process in r9 */ 250 ldr r9, [r6, #(L_ADDR)] 251 252 /* 253 * This can be optimised... We know we want to go from SVC32 254 * mode to UND32 mode 255 */ 256 mrs r3, cpsr 257 bic r2, r3, #(PSR_MODE) 258 orr r2, r2, #(PSR_UND32_MODE | I32_bit) 259 msr cpsr_c, r2 260 261 str sp, [r8, #(PCB_UND_SP)] 262 263 msr cpsr_c, r3 /* Restore the old mode */ 264 265 /* What else needs to be saved? Only FPA stuff when that is supported */ 266 267 /* Restore saved context */ 268 269 /* rem: r4 = old lwp */ 270 /* rem: r6 = new lwp */ 271 /* rem: r9 = new PCB */ 272 /* rem: interrupts are enabled */ 273 274 .Ldo_switch: 275 mov r0, r4 276 mov r1, r6 277 bl _C_LABEL(pmap_switch) 278 279 280 /* rem: r4 = old lwp */ 281 /* rem: r6 = new lwp */ 282 /* rem: r9 = new PCB */ 283 284 /* 285 * This can be optimised... We know we want to go from SVC32 286 * mode to UND32 mode 287 */ 288 mrs r3, cpsr 289 bic r2, r3, #(PSR_MODE) 290 orr r2, r2, #(PSR_UND32_MODE) 291 msr cpsr_c, r2 292 293 ldr sp, [r9, #(PCB_UND_SP)] 294 295 msr cpsr_c, r3 /* Restore the old mode */ 296 297 /* Restore all the save registers */ 298 #ifndef __XSCALE__ 299 add r7, r9, #PCB_R8 300 ldmia r7, {r8-r13} 301 302 sub r7, r7, #PCB_R8 /* restore PCB pointer */ 303 #else 304 mov r7, r9 305 ldr r8, [r7, #(PCB_R8)] 306 ldr r9, [r7, #(PCB_R9)] 307 ldr r10, [r7, #(PCB_R10)] 308 ldr r11, [r7, #(PCB_R11)] 309 ldr r12, [r7, #(PCB_R12)] 310 ldr r13, [r7, #(PCB_SP)] 311 #endif 312 313 ldr r5, [r6, #(L_PROC)] /* fetch the proc for below */ 314 315 /* rem: r4 = old lwp */ 316 /* rem: r5 = new lwp's proc */ 317 /* rem: r6 = new lwp */ 318 /* rem: r7 = new pcb */ 319 320 #ifdef ARMFPE 321 add r0, r7, #(USER_SIZE) & 0x00ff 322 add r0, r0, #(USER_SIZE) & 0xff00 323 bl _C_LABEL(arm_fpe_core_changecontext) 324 #endif 325 326 /* We can enable interrupts again */ 327 IRQenableALL 328 329 /* rem: r4 = old lwp */ 330 /* rem: r5 = new lwp's proc */ 331 /* rem: r6 = new lwp */ 332 /* rem: r7 = new PCB */ 333 334 /* 335 * Check for restartable atomic sequences (RAS). 336 */ 337 338 ldr r2, [r5, #(P_RASLIST)] 339 ldr r1, [r7, #(PCB_TF)] /* r1 = trapframe (used below) */ 340 teq r2, #0 /* p->p_nras == 0? */ 341 bne .Lswitch_do_ras /* no, check for one */ 342 343 .Lswitch_return: 344 /* cpu_switchto returns the old lwp */ 345 mov r0, r4 346 /* lwp_trampoline expects new lwp as it's second argument */ 347 mov r1, r6 348 349 /* 350 * Pull the registers that got pushed when either savectx() or 351 * cpu_switchto() was called and return. 352 */ 353 ldmfd sp!, {r4-r7, pc} 354 355 .Lswitch_do_ras: 356 ldr r1, [r1, #(TF_PC)] /* second ras_lookup() arg */ 357 mov r0, r5 /* first ras_lookup() arg */ 358 bl _C_LABEL(ras_lookup) 359 cmn r0, #1 /* -1 means "not in a RAS" */ 360 ldrne r1, [r7, #(PCB_TF)] 361 strne r0, [r1, #(TF_PC)] 362 b .Lswitch_return 363 364 365 /* LINTSTUB: Func: void savectx(struct pcb *pcb) */ 366 ENTRY(savectx) 367 /* 368 * r0 = pcb 369 */ 370 371 /* Push registers.*/ 372 stmfd sp!, {r4-r7, lr} 373 374 /* Store all the registers in the process's pcb */ 375 #ifndef __XSCALE__ 376 add r2, r0, #(PCB_R8) 377 stmia r2, {r8-r13} 378 #else 379 strd r8, [r0, #(PCB_R8)] 380 strd r10, [r0, #(PCB_R10)] 381 strd r12, [r0, #(PCB_R12)] 382 #endif 383 384 /* Pull the regs of the stack */ 385 ldmfd sp!, {r4-r7, pc} 386 387 ENTRY(lwp_trampoline) 388 bl _C_LABEL(lwp_startup) 389 390 mov r0, r5 391 mov r1, sp 392 mov lr, pc 393 mov pc, r4 394 395 /* Kill irq's */ 396 mrs r0, cpsr 397 orr r0, r0, #(I32_bit) 398 msr cpsr_c, r0 399 400 PULLFRAME 401 402 movs pc, lr /* Exit */ 403
Indexes created Sat Oct 25 10:09:55 GMT 2025