cpuswitch.S revision 1.48.10.2
1 /* $NetBSD: cpuswitch.S,v 1.48.10.2 2008/01/20 16:03:55 chris Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 */ 79 80 #include "opt_armfpe.h" 81 #include "opt_arm32_pmap.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_lockdebug.h" 84 85 #include "assym.h" 86 #include <arm/arm32/pte.h> 87 #include <machine/param.h> 88 #include <machine/cpu.h> 89 #include <machine/frame.h> 90 #include <machine/asm.h> 91 92 /* LINTSTUB: include <sys/param.h> */ 93 94 #undef IRQdisable 95 #undef IRQenable 96 97 /* 98 * New experimental definitions of IRQdisable and IRQenable 99 * These keep FIQ's enabled since FIQ's are special. 100 */ 101 102 #define IRQdisable \ 103 mrs r14, cpsr ; \ 104 orr r14, r14, #(I32_bit) ; \ 105 msr cpsr_c, r14 ; \ 106 107 #define IRQenable \ 108 mrs r14, cpsr ; \ 109 bic r14, r14, #(I32_bit) ; \ 110 msr cpsr_c, r14 ; \ 111 112 .text 113 114 #ifdef MULTIPROCESSOR 115 .Lcpu_info_store: 116 .word _C_LABEL(cpu_info_store) 117 .Lcurlwp: 118 /* FIXME: This is bogus in the general case. */ 119 .word _C_LABEL(cpu_info_store) + CI_CURLWP 120 121 .Lcurpcb: 122 .word _C_LABEL(cpu_info_store) + CI_CURPCB 123 #else 124 .Lcurlwp: 125 .word _C_LABEL(curlwp) 126 127 .Lcurpcb: 128 .word _C_LABEL(curpcb) 129 #endif 130 131 #ifndef MULTIPROCESSOR 132 .data 133 .global _C_LABEL(curpcb) 134 _C_LABEL(curpcb): 135 .word 0x00000000 136 .text 137 #endif 138 139 .Lblock_userspace_access: 140 .word _C_LABEL(block_userspace_access) 141 142 143 /* 144 * struct lwp * 145 * cpu_switchto(struct lwp *current, struct lwp *next) 146 * 147 * Switch to the specified next LWP 148 * Arguments: 149 * 150 * r0 'struct lwp *' of the current LWP 151 * r1 'struct lwp *' of the LWP to switch to 152 */ 153 ENTRY(cpu_switchto) 154 mov ip, sp 155 stmfd sp!, {r4-r7, ip, lr} 156 157 /* move lwps and new pcb into caller saved registers */ 158 mov r6, r1 159 mov r4, r0 160 ldr r7, [r6, #(L_ADDR)] 161 162 /* rem: r4 = old lwp */ 163 /* rem: r6 = new lwp */ 164 /* rem: r7 = new pcb */ 165 166 IRQdisable 167 168 #ifdef MULTIPROCESSOR 169 /* XXX use curcpu() */ 170 ldr r0, .Lcpu_info_store 171 str r0, [r6, #(L_CPU)] 172 #else 173 /* l->l_cpu initialized in fork1() for single-processor */ 174 #endif 175 176 /* We have a new curlwp and pcb so make a note of them */ 177 ldr r0, .Lcurlwp 178 ldr r1, .Lcurpcb 179 180 str r6, [r0] 181 str r7, [r1] 182 183 /* At this point we can allow IRQ's again. */ 184 IRQenable 185 186 /* rem: r4 = old lwp */ 187 /* rem: r6 = new lwp */ 188 /* rem: r7 = new pcb */ 189 /* rem: interrupts are enabled */ 190 191 /* 192 * If the old lwp on entry to cpu_switchto was zero then the 193 * process that called it was exiting. This means that we do 194 * not need to save the current context. Instead we can jump 195 * straight to restoring the context for the new process. 196 */ 197 teq r4, #0x00000000 198 beq .Ldo_switch 199 200 /* rem: r4 = old lwp */ 201 /* rem: r6 = new lwp */ 202 /* rem: r7 = new pcb */ 203 /* rem: interrupts are enabled */ 204 205 /* Save old context */ 206 207 /* Get the user structure for the old lwp. */ 208 ldr r5, [r4, #(L_ADDR)] 209 210 /* Save all the registers in the old lwp's pcb */ 211 #ifndef __XSCALE__ 212 add r0, r5, #(PCB_R8) 213 stmia r0, {r8-r13} 214 #else 215 strd r8, [r5, #(PCB_R8)] 216 strd r10, [r5, #(PCB_R10)] 217 strd r12, [r5, #(PCB_R12)] 218 #endif 219 220 /* 221 * NOTE: We can now use r8-r13 until it is time to restore 222 * them for the new process. 223 */ 224 225 /* rem: r4 = old lwp */ 226 /* rem: r5 = old pcb */ 227 /* rem: r6 = new lwp */ 228 /* rem: r7 = new pcb */ 229 /* rem: interrupts are enabled */ 230 231 /* What else needs to be saved? Only FPA stuff when that is supported */ 232 233 /* Restore saved context */ 234 235 .Ldo_switch: 236 mov r0, r4 237 mov r1, r6 238 bl _C_LABEL(pmap_switch) 239 240 /* rem: r4 = old lwp */ 241 /* rem: r6 = new lwp */ 242 /* rem: r7 = new pcb */ 243 /* rem: interrupts are enabled */ 244 245 ldr r5, [r6, #(L_PROC)] /* fetch the proc for below */ 246 247 /* Restore all the saved registers */ 248 #ifndef __XSCALE__ 249 add r0, r7, #PCB_R8 250 ldmia r0, {r8-r13} 251 #else 252 ldr r8, [r7, #(PCB_R8)] 253 ldr r9, [r7, #(PCB_R9)] 254 ldr r10, [r7, #(PCB_R10)] 255 ldr r11, [r7, #(PCB_R11)] 256 ldr r12, [r7, #(PCB_R12)] 257 ldr r13, [r7, #(PCB_SP)] 258 #endif 259 260 /* rem: r4 = old lwp */ 261 /* rem: r5 = new lwp's proc */ 262 /* rem: r6 = new lwp */ 263 /* rem: r7 = new pcb */ 264 265 #ifdef ARMFPE 266 add r0, r7, #(USER_SIZE) & 0x00ff 267 add r0, r0, #(USER_SIZE) & 0xff00 268 bl _C_LABEL(arm_fpe_core_changecontext) 269 #endif 270 271 /* rem: r4 = old lwp */ 272 /* rem: r5 = new lwp's proc */ 273 /* rem: r6 = new lwp */ 274 /* rem: r7 = new PCB */ 275 276 /* 277 * Check for restartable atomic sequences (RAS). 278 */ 279 280 ldr r2, [r5, #(P_RASLIST)] 281 ldr r1, [r7, #(PCB_TF)] /* r1 = trapframe (used below) */ 282 teq r2, #0 /* p->p_nras == 0? */ 283 bne .Lswitch_do_ras /* no, check for one */ 284 285 .Lswitch_return: 286 /* cpu_switchto returns the old lwp */ 287 mov r0, r4 288 /* lwp_trampoline expects new lwp as it's second argument */ 289 mov r1, r6 290 291 /* 292 * Pull the registers that got pushed when cpu_switchto() was called, 293 * and return. 294 */ 295 ldmfd sp, {r4-r7, sp, pc} 296 297 .Lswitch_do_ras: 298 ldr r1, [r1, #(TF_PC)] /* second ras_lookup() arg */ 299 mov r0, r5 /* first ras_lookup() arg */ 300 bl _C_LABEL(ras_lookup) 301 cmn r0, #1 /* -1 means "not in a RAS" */ 302 ldrne r1, [r7, #(PCB_TF)] 303 strne r0, [r1, #(TF_PC)] 304 b .Lswitch_return 305 306 ENTRY(lwp_trampoline) 307 /* 308 * cpu_switchto gives us: 309 * 310 * arg0(r0) = old lwp 311 * arg1(r1) = new lwp 312 */ 313 bl _C_LABEL(lwp_startup) 314 315 mov r0, r5 316 mov r1, sp 317 mov lr, pc 318 mov pc, r4 319 320 /* Kill irq's */ 321 mrs r0, cpsr 322 orr r0, r0, #(I32_bit) 323 msr cpsr_c, r0 324 325 PULLFRAME 326 327 movs pc, lr /* Exit */ 328
Indexes created Sat Oct 25 10:09:55 GMT 2025