cpuswitch.S revision 1.57
1 /* $NetBSD: cpuswitch.S,v 1.57 2008/04/20 15:42:19 scw Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 */ 79 80 #include "opt_armfpe.h" 81 #include "opt_arm32_pmap.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_lockdebug.h" 84 85 #include "assym.h" 86 #include <arm/arm32/pte.h> 87 #include <machine/param.h> 88 #include <machine/cpu.h> 89 #include <machine/frame.h> 90 #include <machine/asm.h> 91 92 /* LINTSTUB: include <sys/param.h> */ 93 94 #undef IRQdisable 95 #undef IRQenable 96 97 /* 98 * New experimental definitions of IRQdisable and IRQenable 99 * These keep FIQ's enabled since FIQ's are special. 100 */ 101 102 #define IRQdisable \ 103 mrs r14, cpsr ; \ 104 orr r14, r14, #(I32_bit) ; \ 105 msr cpsr_c, r14 ; \ 106 107 #define IRQenable \ 108 mrs r14, cpsr ; \ 109 bic r14, r14, #(I32_bit) ; \ 110 msr cpsr_c, r14 ; \ 111 112 .text 113 114 #ifdef MULTIPROCESSOR 115 .Lcpu_info_store: 116 .word _C_LABEL(cpu_info_store) 117 .Lcurlwp: 118 /* FIXME: This is bogus in the general case. */ 119 .word _C_LABEL(cpu_info_store) + CI_CURLWP 120 121 .Lcurpcb: 122 .word _C_LABEL(cpu_info_store) + CI_CURPCB 123 #else 124 .Lcurlwp: 125 .word _C_LABEL(curlwp) 126 127 .Lcurpcb: 128 .word _C_LABEL(curpcb) 129 #endif 130 131 #ifndef MULTIPROCESSOR 132 .data 133 .global _C_LABEL(curpcb) 134 _C_LABEL(curpcb): 135 .word 0x00000000 136 .text 137 #endif 138 139 .Lpmap_previous_active_lwp: 140 .word _C_LABEL(pmap_previous_active_lwp) 141 142 /* 143 * struct lwp * 144 * cpu_switchto(struct lwp *current, struct lwp *next) 145 * 146 * Switch to the specified next LWP 147 * Arguments: 148 * 149 * r0 'struct lwp *' of the current LWP 150 * r1 'struct lwp *' of the LWP to switch to 151 */ 152 ENTRY(cpu_switchto) 153 mov ip, sp 154 stmfd sp!, {r4-r7, ip, lr} 155 156 /* move lwps and new pcb into caller saved registers */ 157 mov r6, r1 158 mov r4, r0 159 ldr r7, [r6, #(L_ADDR)] 160 161 /* rem: r4 = old lwp */ 162 /* rem: r6 = new lwp */ 163 /* rem: r7 = new pcb */ 164 165 IRQdisable 166 167 #ifdef MULTIPROCESSOR 168 /* XXX use curcpu() */ 169 ldr r0, .Lcpu_info_store 170 str r0, [r6, #(L_CPU)] 171 #else 172 /* l->l_cpu initialized in fork1() for single-processor */ 173 #endif 174 175 /* We have a new curlwp and pcb so make a note of them */ 176 ldr r0, .Lcurlwp 177 ldr r1, .Lcurpcb 178 179 str r6, [r0] 180 str r7, [r1] 181 182 /* At this point we can allow IRQ's again. */ 183 IRQenable 184 185 /* rem: r4 = old lwp */ 186 /* rem: r6 = new lwp */ 187 /* rem: r7 = new pcb */ 188 /* rem: interrupts are enabled */ 189 190 /* 191 * If the old lwp on entry to cpu_switchto was zero then the 192 * process that called it was exiting. This means that we do 193 * not need to save the current context. Instead we can jump 194 * straight to restoring the context for the new process. 195 */ 196 teq r4, #0x00000000 197 beq .Ldo_switch 198 199 /* rem: r4 = old lwp */ 200 /* rem: r6 = new lwp */ 201 /* rem: r7 = new pcb */ 202 /* rem: interrupts are enabled */ 203 204 /* Save old context */ 205 206 /* Get the user structure for the old lwp. */ 207 ldr r5, [r4, #(L_ADDR)] 208 209 /* Save all the registers in the old lwp's pcb */ 210 #ifndef __XSCALE__ 211 add r0, r5, #(PCB_R8) 212 stmia r0, {r8-r13} 213 #else 214 strd r8, [r5, #(PCB_R8)] 215 strd r10, [r5, #(PCB_R10)] 216 strd r12, [r5, #(PCB_R12)] 217 #endif 218 219 /* 220 * NOTE: We can now use r8-r13 until it is time to restore 221 * them for the new process. 222 */ 223 224 /* rem: r4 = old lwp */ 225 /* rem: r5 = old pcb */ 226 /* rem: r6 = new lwp */ 227 /* rem: r7 = new pcb */ 228 /* rem: interrupts are enabled */ 229 230 /* What else needs to be saved? Only FPA stuff when that is supported */ 231 #ifdef FPU_VFP 232 /* 233 * Now's a good time to 'save' the VFP context. Note that we 234 * don't really force a save here, which can save time if we 235 * end up restarting the same context. 236 */ 237 bl _C_LABEL(vfp_savecontext) 238 #endif 239 240 /* Restore saved context */ 241 242 .Ldo_switch: 243 /* rem: r4 = old lwp */ 244 /* rem: r6 = new lwp */ 245 /* rem: r7 = new pcb */ 246 /* rem: interrupts are enabled */ 247 248 ldr r1, .Lpmap_previous_active_lwp 249 ldr r5, [r6, #(L_PROC)] /* fetch the proc for below */ 250 251 /* Restore all the saved registers */ 252 #ifndef __XSCALE__ 253 add r0, r7, #PCB_R8 254 ldmia r0, {r8-r13} 255 #else 256 ldr r8, [r7, #(PCB_R8)] 257 ldr r9, [r7, #(PCB_R9)] 258 ldr r10, [r7, #(PCB_R10)] 259 ldr r11, [r7, #(PCB_R11)] 260 ldr r12, [r7, #(PCB_R12)] 261 ldr r13, [r7, #(PCB_SP)] 262 #endif 263 264 /* Record the old lwp for pmap_activate()'s benefit */ 265 str r4, [r1] 266 267 /* rem: r4 = old lwp */ 268 /* rem: r5 = new lwp's proc */ 269 /* rem: r6 = new lwp */ 270 /* rem: r7 = new pcb */ 271 272 #ifdef FPU_VFP 273 mov r0, r6 274 bl _C_LABEL(vfp_loadcontext) 275 #endif 276 #ifdef ARMFPE 277 add r0, r7, #(USER_SIZE) & 0x00ff 278 add r0, r0, #(USER_SIZE) & 0xff00 279 bl _C_LABEL(arm_fpe_core_changecontext) 280 #endif 281 282 /* rem: r4 = old lwp */ 283 /* rem: r5 = new lwp's proc */ 284 /* rem: r6 = new lwp */ 285 /* rem: r7 = new PCB */ 286 287 /* 288 * Check for restartable atomic sequences (RAS). 289 */ 290 291 ldr r2, [r5, #(P_RASLIST)] 292 ldr r1, [r7, #(PCB_TF)] /* r1 = trapframe (used below) */ 293 teq r2, #0 /* p->p_nras == 0? */ 294 bne .Lswitch_do_ras /* no, check for one */ 295 296 .Lswitch_return: 297 /* cpu_switchto returns the old lwp */ 298 mov r0, r4 299 /* lwp_trampoline expects new lwp as it's second argument */ 300 mov r1, r6 301 302 /* 303 * Pull the registers that got pushed when cpu_switchto() was called, 304 * and return. 305 */ 306 ldmfd sp, {r4-r7, sp, pc} 307 308 .Lswitch_do_ras: 309 ldr r1, [r1, #(TF_PC)] /* second ras_lookup() arg */ 310 mov r0, r5 /* first ras_lookup() arg */ 311 bl _C_LABEL(ras_lookup) 312 cmn r0, #1 /* -1 means "not in a RAS" */ 313 ldrne r1, [r7, #(PCB_TF)] 314 strne r0, [r1, #(TF_PC)] 315 b .Lswitch_return 316 317 ENTRY(lwp_trampoline) 318 /* 319 * cpu_switchto gives us: 320 * 321 * arg0(r0) = old lwp 322 * arg1(r1) = new lwp 323 */ 324 bl _C_LABEL(lwp_startup) 325 326 mov r0, r5 327 mov r1, sp 328 mov lr, pc 329 mov pc, r4 330 331 /* Kill irq's */ 332 mrs r0, cpsr 333 orr r0, r0, #(I32_bit) 334 msr cpsr_c, r0 335 336 PULLFRAME 337 338 movs pc, lr /* Exit */ 339
Indexes created Tue Oct 21 19:09:51 GMT 2025