cpuswitch.S revision 1.59
1 /* $NetBSD: cpuswitch.S,v 1.59 2008/11/19 06:34:21 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 */ 79 80 #include "opt_armfpe.h" 81 #include "opt_arm32_pmap.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_cpuoptions.h" 84 #include "opt_lockdebug.h" 85 86 #include "assym.h" 87 #include <arm/arm32/pte.h> 88 #include <machine/param.h> 89 #include <machine/frame.h> 90 #include <machine/asm.h> 91 #include <machine/cpu.h> 92 93 RCSID("$NetBSD: cpuswitch.S,v 1.59 2008/11/19 06:34:21 matt Exp $") 94 95 /* LINTSTUB: include <sys/param.h> */ 96 97 #undef IRQdisable 98 #undef IRQenable 99 100 /* 101 * New experimental definitions of IRQdisable and IRQenable 102 * These keep FIQ's enabled since FIQ's are special. 103 */ 104 105 #ifdef _ARM_ARCH_6 106 #define IRQdisable cpsid i 107 #define IRQenable cpsie i 108 #else 109 #define IRQdisable \ 110 mrs r14, cpsr ; \ 111 orr r14, r14, #(I32_bit) ; \ 112 msr cpsr_c, r14 113 114 #define IRQenable \ 115 mrs r14, cpsr ; \ 116 bic r14, r14, #(I32_bit) ; \ 117 msr cpsr_c, r14 118 119 #endif 120 121 .text 122 .Lpmap_previous_active_lwp: 123 .word _C_LABEL(pmap_previous_active_lwp) 124 125 /* 126 * struct lwp * 127 * cpu_switchto(struct lwp *current, struct lwp *next) 128 * 129 * Switch to the specified next LWP 130 * Arguments: 131 * 132 * r0 'struct lwp *' of the current LWP (or NULL if exiting) 133 * r1 'struct lwp *' of the LWP to switch to 134 * r2 returning 135 */ 136 ENTRY(cpu_switchto) 137 mov ip, sp 138 stmfd sp!, {r4-r7, ip, lr} 139 140 /* move lwps into caller saved registers */ 141 mov r6, r1 142 mov r4, r0 143 144 #ifdef PROCESS_ID_CURCPU 145 GET_CURCPU(r7) 146 #elif defined(PROCESS_ID_IS_CURLWP) 147 mcr p15, 0, r0, c13, c0, 4 /* get old lwp (r4 maybe 0) */ 148 ldr r7, [r0, #(L_CPU)] /* get cpu from old lwp */ 149 #elif !defined(MULTIPROCESSOR) 150 ldr r7, [r6, #L_CPU] /* get cpu from new lwp */ 151 #else 152 #error curcpu() method not defined 153 #endif 154 155 /* rem: r4 = old lwp */ 156 /* rem: r6 = new lwp */ 157 /* rem: r7 = curcpu() */ 158 159 #ifndef __HAVE_UNNESTED_INTRS 160 IRQdisable 161 #endif 162 163 #ifdef MULTIPROCESSOR 164 str r7, [r6, #(L_CPU)] 165 #else 166 /* l->l_cpu initialized in fork1() for single-processor */ 167 #endif 168 169 #if defined(PROCESS_ID_IS_CURLWP) 170 mcr p15, 0, r6, c13, c0, 4 /* set current lwp */ 171 #endif 172 #if !defined(PROCESS_ID_IS_CURLWP) || defined(MULTIPROCESSOR) 173 /* We have a new curlwp now so make a note it */ 174 str r6, [r7, #(CI_CURLWP)] 175 #endif 176 177 /* Hook in a new pcb */ 178 ldr r0, [r6, #(L_ADDR)] 179 str r0, [r7, #(CI_CURPCB)] 180 mov r7, r0 181 182 /* At this point we can allow IRQ's again. */ 183 #ifndef __HAVE_UNNESTED_INTRS 184 IRQenable 185 #endif 186 187 /* rem: r4 = old lwp */ 188 /* rem: r6 = new lwp */ 189 /* rem: r7 = new pcb */ 190 /* rem: interrupts are enabled */ 191 192 /* 193 * If the old lwp on entry to cpu_switchto was zero then the 194 * process that called it was exiting. This means that we do 195 * not need to save the current context. Instead we can jump 196 * straight to restoring the context for the new process. 197 */ 198 teq r4, #0 199 beq .Ldo_switch 200 201 /* rem: r4 = old lwp */ 202 /* rem: r6 = new lwp */ 203 /* rem: r7 = new pcb */ 204 /* rem: interrupts are enabled */ 205 206 /* Save old context */ 207 208 /* Get the user structure for the old lwp. */ 209 ldr r5, [r4, #(L_ADDR)] 210 211 /* Save all the registers in the old lwp's pcb */ 212 #if defined(__XSCALE__) || defined(_ARM_ARCH_6) 213 strd r8, [r5, #(PCB_R8)] 214 strd r10, [r5, #(PCB_R10)] 215 strd r12, [r5, #(PCB_R12)] 216 #else 217 add r0, r5, #(PCB_R8) 218 stmia r0, {r8-r13} 219 #endif 220 221 #ifdef _ARM_ARCH_6 222 /* 223 * Save user read/write thread/process id register 224 */ 225 mrc p15, 0, r0, c13, c0, 2 226 str r0, [r5, #(PCB_USER_PID_RW)] 227 #endif 228 /* 229 * NOTE: We can now use r8-r13 until it is time to restore 230 * them for the new process. 231 */ 232 233 /* rem: r4 = old lwp */ 234 /* rem: r5 = old pcb */ 235 /* rem: r6 = new lwp */ 236 /* rem: r7 = new pcb */ 237 /* rem: interrupts are enabled */ 238 239 #ifdef FPU_VFP 240 /* 241 * Now's a good time to 'save' the VFP context. Note that we 242 * don't really force a save here, which can save time if we 243 * end up restarting the same context. 244 */ 245 bl _C_LABEL(vfp_savecontext) 246 #endif 247 248 /* Restore saved context */ 249 250 .Ldo_switch: 251 /* rem: r4 = old lwp */ 252 /* rem: r6 = new lwp */ 253 /* rem: r7 = new pcb */ 254 /* rem: interrupts are enabled */ 255 256 #ifdef _ARM_ARCH_6 257 /* 258 * Restore user thread/process id registers 259 */ 260 ldr r0, [r7, #(PCB_USER_PID_RW)] 261 mcr p15, 0, r0, c13, c0, 2 262 ldr r0, [r7, #(PCB_USER_PID_RO)] 263 mcr p15, 0, r0, c13, c0, 3 264 #endif 265 266 ldr r5, [r6, #(L_PROC)] /* fetch the proc for below */ 267 268 /* Restore all the saved registers */ 269 #ifdef __XSCALE__ 270 ldr r8, [r7, #(PCB_R8)] 271 ldr r9, [r7, #(PCB_R9)] 272 ldr r10, [r7, #(PCB_R10)] 273 ldr r11, [r7, #(PCB_R11)] 274 ldr r12, [r7, #(PCB_R12)] 275 ldr r13, [r7, #(PCB_SP)] 276 #elif defined(_ARM_ARCH_6) 277 ldrd r8, [r7, #(PCB_R8)] 278 ldrd r10, [r7, #(PCB_R10)] 279 ldrd r12, [r7, #(PCB_R12)] 280 #else 281 add r0, r7, #PCB_R8 282 ldmia r0, {r8-r13} 283 #endif 284 285 /* Record the old lwp for pmap_activate()'s benefit */ 286 ldr r1, .Lpmap_previous_active_lwp 287 str r4, [r1] 288 289 /* rem: r4 = old lwp */ 290 /* rem: r5 = new lwp's proc */ 291 /* rem: r6 = new lwp */ 292 /* rem: r7 = new pcb */ 293 294 #ifdef FPU_VFP 295 mov r0, r6 296 bl _C_LABEL(vfp_loadcontext) 297 #endif 298 #ifdef ARMFPE 299 add r0, r7, #(USER_SIZE) & 0x00ff 300 add r0, r0, #(USER_SIZE) & 0xff00 301 bl _C_LABEL(arm_fpe_core_changecontext) 302 #endif 303 304 /* rem: r4 = old lwp */ 305 /* rem: r5 = new lwp's proc */ 306 /* rem: r6 = new lwp */ 307 /* rem: r7 = new PCB */ 308 309 /* 310 * Check for restartable atomic sequences (RAS). 311 */ 312 313 ldr r2, [r5, #(P_RASLIST)] 314 ldr r1, [r7, #(PCB_TF)] /* r1 = trapframe (used below) */ 315 teq r2, #0 /* p->p_nras == 0? */ 316 bne .Lswitch_do_ras /* no, check for one */ 317 318 .Lswitch_return: 319 /* cpu_switchto returns the old lwp */ 320 mov r0, r4 321 /* lwp_trampoline expects new lwp as it's second argument */ 322 mov r1, r6 323 324 /* 325 * Pull the registers that got pushed when cpu_switchto() was called, 326 * and return. 327 */ 328 ldmfd sp, {r4-r7, sp, pc} 329 330 .Lswitch_do_ras: 331 ldr r1, [r1, #(TF_PC)] /* second ras_lookup() arg */ 332 mov r0, r5 /* first ras_lookup() arg */ 333 bl _C_LABEL(ras_lookup) 334 cmn r0, #1 /* -1 means "not in a RAS" */ 335 ldrne r1, [r7, #(PCB_TF)] 336 strne r0, [r1, #(TF_PC)] 337 b .Lswitch_return 338 339 ENTRY(lwp_trampoline) 340 /* 341 * cpu_switchto gives us: 342 * 343 * arg0(r0) = old lwp 344 * arg1(r1) = new lwp 345 */ 346 bl _C_LABEL(lwp_startup) 347 348 mov r0, r5 349 mov r1, sp 350 mov lr, pc 351 mov pc, r4 352 353 /* Kill irq's */ 354 mrs r0, cpsr 355 orr r0, r0, #(IF32_bits) 356 msr cpsr_c, r0 357 358 PULLFRAME 359 360 movs pc, lr /* Exit */ 361 362 #ifdef __HAVE_FAST_SOFTINTS 363 /* 364 * Called at IPL_HIGH 365 * r0 = new lwp 366 * r1 = ipl for softint_dispatch 367 */ 368 ENTRY_NP(softint_switch) 369 stmfd sp!, {r4, r6, r7, lr} 370 371 ldr r7, [r0, #L_CPU] /* get curcpu */ 372 #if defined(PROCESS_ID_IS_CURLWP) 373 mrc p15, 0, r4, c13, c0, 4 /* get old lwp */ 374 #else 375 ldr r4, [r7, #(CI_CURLWP)] /* get old lwp */ 376 #endif 377 mrs r6, cpsr /* we need to save this */ 378 379 /* 380 * If the soft lwp blocks, it needs to return to softint_tramp 381 */ 382 mov r2, sp /* think ip */ 383 adr r3, softint_tramp /* think lr */ 384 stmfd sp!, {r2-r3} 385 stmfd sp!, {r4-r7} 386 387 mov r5, r0 /* save new lwp */ 388 389 ldr r2, [r4, #(L_ADDR)] /* get old lwp's pcb */ 390 391 /* Save all the registers into the old lwp's pcb */ 392 #if defined(__XSCALE__) || defined(_ARM_ARCH_6) 393 strd r8, [r2, #(PCB_R8)] 394 strd r10, [r2, #(PCB_R10)] 395 strd r12, [r2, #(PCB_R12)] 396 #else 397 add r3, r2, #(PCB_R8) 398 stmia r3, {r8-r13} 399 #endif 400 401 /* this is an invariant so load before disabling intrs */ 402 ldr r2, [r5, #(L_ADDR)] /* get new lwp's pcb */ 403 404 #ifndef __HAVE_UNNESTED_INTRS 405 IRQdisable 406 #endif 407 /* 408 * We're switching to a bound LWP so its l_cpu is already correct. 409 */ 410 #if defined(PROCESS_ID_IS_CURLWP) 411 mcr p15, 0, r5, c13, c0, 4 /* save new lwp */ 412 #endif 413 #if !defined(PROCESS_ID_IS_CURLWP) || defined(MULTIPROCESSOR) 414 str r5, [r7, #(CI_CURLWP)] /* save new lwp */ 415 #endif 416 417 /* Hook in a new pcb */ 418 str r2, [r7, #(CI_CURPCB)] 419 420 /* 421 * Normally, we'd get {r8-r13} but since this is a softint lwp 422 * it's existing state doesn't matter. We start the stack just 423 * below the trapframe. 424 */ 425 ldr sp, [r2, #(PCB_TF)] /* get new lwp's stack ptr */ 426 427 /* At this point we can allow IRQ's again. */ 428 #ifndef __HAVE_UNNESTED_INTRS 429 IRQenable 430 #endif 431 432 /* r1 still has ipl */ 433 mov r0, r4 /* r0 has pinned (old) lwp */ 434 bl _C_LABEL(softint_dispatch) 435 /* 436 * If we've returned, we need to change everything back and return. 437 */ 438 ldr r2, [r4, #(L_ADDR)] /* get pinned lwp's pcb */ 439 440 #ifndef __HAVE_UNNESTED_INTRS 441 IRQdisable 442 #endif 443 /* 444 * We don't need to restore all the registers since another lwp was 445 * never executed. But we do need the SP from the formerly pinned lwp. 446 */ 447 448 #if defined(PROCESS_ID_IS_CURLWP) 449 mcr p15, 0, r4, c13, c0, 4 /* restore pinned lwp */ 450 #endif 451 #if !defined(PROCESS_ID_IS_CURLWP) || defined(MULTIPROCESSOR) 452 str r4, [r7, #(CI_CURLWP)] /* restore pinned lwp */ 453 #endif 454 str r2, [r7, #(CI_CURPCB)] /* restore the curpcb */ 455 ldr sp, [r2, #(PCB_SP)] /* now running on the old stack. */ 456 457 /* At this point we can allow IRQ's again. */ 458 msr cpsr_c, r6 459 460 /* 461 * Grab the registers that got pushed at the start and return. 462 */ 463 ldmfd sp!, {r4-r7, ip, lr} /* eat switch frame */ 464 ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */ 465 466 END(softint_switch) 467 468 /* 469 * r0 = previous LWP (the soft lwp) 470 * r4 = original LWP (the current lwp) 471 * r6 = original CPSR 472 * r7 = curcpu() 473 */ 474 ENTRY_NP(softint_tramp) 475 ldr r3, [r7, #(CI_MTX_COUNT)] /* readust after mi_switch */ 476 add r3, r3, #1 477 str r3, [r7, #(CI_MTX_COUNT)] 478 479 mov r3, #0 /* tell softint_dispatch */ 480 str r3, [r0, #(L_CTXSWTCH)] /* the soft lwp blocked */ 481 482 msr cpsr_c, r6 /* restore interrupts */ 483 ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */ 484 END(softint_tramp) 485 #endif /* __HAVE_FAST_SOFTINTS */ 486
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