cpuswitch.S revision 1.65
1 /* $NetBSD: cpuswitch.S,v 1.65 2012/08/14 20:42:33 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 */ 79 80 #include "opt_armfpe.h" 81 #include "opt_arm32_pmap.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_cpuoptions.h" 84 #include "opt_lockdebug.h" 85 86 #include "assym.h" 87 #include <machine/param.h> 88 #include <machine/frame.h> 89 #include <machine/asm.h> 90 #include <machine/cpu.h> 91 92 RCSID("$NetBSD: cpuswitch.S,v 1.65 2012/08/14 20:42:33 matt Exp $") 93 94 /* LINTSTUB: include <sys/param.h> */ 95 96 #undef IRQdisable 97 #undef IRQenable 98 99 /* 100 * New experimental definitions of IRQdisable and IRQenable 101 * These keep FIQ's enabled since FIQ's are special. 102 */ 103 104 #ifdef _ARM_ARCH_6 105 #define IRQdisable cpsid i 106 #define IRQenable cpsie i 107 #else 108 #define IRQdisable \ 109 mrs r14, cpsr ; \ 110 orr r14, r14, #(I32_bit) ; \ 111 msr cpsr_c, r14 112 113 #define IRQenable \ 114 mrs r14, cpsr ; \ 115 bic r14, r14, #(I32_bit) ; \ 116 msr cpsr_c, r14 117 118 #endif 119 120 .text 121 .Lpmap_previous_active_lwp: 122 .word _C_LABEL(pmap_previous_active_lwp) 123 124 /* 125 * struct lwp * 126 * cpu_switchto(struct lwp *current, struct lwp *next) 127 * 128 * Switch to the specified next LWP 129 * Arguments: 130 * 131 * r0 'struct lwp *' of the current LWP (or NULL if exiting) 132 * r1 'struct lwp *' of the LWP to switch to 133 * r2 returning 134 */ 135 ENTRY(cpu_switchto) 136 mov ip, sp 137 stmfd sp!, {r4-r7, ip, lr} 138 139 /* move lwps into caller saved registers */ 140 mov r6, r1 141 mov r4, r0 142 143 #ifdef PROCESS_ID_CURCPU 144 GET_CURCPU(r7) 145 #elif defined(PROCESS_ID_IS_CURLWP) 146 mcr p15, 0, r0, c13, c0, 4 /* get old lwp (r4 maybe 0) */ 147 ldr r7, [r0, #(L_CPU)] /* get cpu from old lwp */ 148 #elif !defined(MULTIPROCESSOR) 149 ldr r7, [r6, #L_CPU] /* get cpu from new lwp */ 150 #else 151 #error curcpu() method not defined 152 #endif 153 154 /* rem: r4 = old lwp */ 155 /* rem: r6 = new lwp */ 156 /* rem: r7 = curcpu() */ 157 158 #ifndef __HAVE_UNNESTED_INTRS 159 IRQdisable 160 #endif 161 162 #ifdef MULTIPROCESSOR 163 str r7, [r6, #(L_CPU)] 164 #else 165 /* l->l_cpu initialized in fork1() for single-processor */ 166 #endif 167 168 #if defined(PROCESS_ID_IS_CURLWP) 169 mcr p15, 0, r6, c13, c0, 4 /* set current lwp */ 170 #endif 171 #if !defined(PROCESS_ID_IS_CURLWP) || defined(MULTIPROCESSOR) 172 /* We have a new curlwp now so make a note it */ 173 str r6, [r7, #(CI_CURLWP)] 174 #endif 175 176 /* Get the new pcb */ 177 ldr r7, [r6, #(L_PCB)] 178 179 /* At this point we can allow IRQ's again. */ 180 #ifndef __HAVE_UNNESTED_INTRS 181 IRQenable 182 #endif 183 184 /* rem: r4 = old lwp */ 185 /* rem: r6 = new lwp */ 186 /* rem: r7 = new pcb */ 187 /* rem: interrupts are enabled */ 188 189 /* 190 * If the old lwp on entry to cpu_switchto was zero then the 191 * process that called it was exiting. This means that we do 192 * not need to save the current context. Instead we can jump 193 * straight to restoring the context for the new process. 194 */ 195 teq r4, #0 196 beq .Ldo_switch 197 198 /* rem: r4 = old lwp */ 199 /* rem: r6 = new lwp */ 200 /* rem: r7 = new pcb */ 201 /* rem: interrupts are enabled */ 202 203 /* Save old context */ 204 205 /* Get the user structure for the old lwp. */ 206 ldr r5, [r4, #(L_PCB)] 207 208 /* Save all the registers in the old lwp's pcb */ 209 #if defined(__XSCALE__) || defined(_ARM_ARCH_6) 210 strd r8, [r5, #(PCB_R8)] 211 strd r10, [r5, #(PCB_R10)] 212 strd r12, [r5, #(PCB_R12)] 213 #else 214 add r0, r5, #(PCB_R8) 215 stmia r0, {r8-r13} 216 #endif 217 218 #ifdef _ARM_ARCH_6 219 /* 220 * Save user read/write thread/process id register 221 */ 222 mrc p15, 0, r0, c13, c0, 2 223 str r0, [r5, #(PCB_USER_PID_RW)] 224 #endif 225 /* 226 * NOTE: We can now use r8-r13 until it is time to restore 227 * them for the new process. 228 */ 229 230 /* rem: r4 = old lwp */ 231 /* rem: r5 = old pcb */ 232 /* rem: r6 = new lwp */ 233 /* rem: r7 = new pcb */ 234 /* rem: interrupts are enabled */ 235 236 /* Restore saved context */ 237 238 .Ldo_switch: 239 /* rem: r4 = old lwp */ 240 /* rem: r6 = new lwp */ 241 /* rem: r7 = new pcb */ 242 /* rem: interrupts are enabled */ 243 244 #ifdef _ARM_ARCH_6 245 /* 246 * Restore user thread/process id registers 247 */ 248 ldr r0, [r7, #(PCB_USER_PID_RW)] 249 mcr p15, 0, r0, c13, c0, 2 250 ldr r0, [r6, #(L_PRIVATE)] 251 mcr p15, 0, r0, c13, c0, 3 252 #endif 253 254 ldr r5, [r6, #(L_PROC)] /* fetch the proc for below */ 255 256 /* Restore all the saved registers */ 257 #ifdef __XSCALE__ 258 ldr r8, [r7, #(PCB_R8)] 259 ldr r9, [r7, #(PCB_R9)] 260 ldr r10, [r7, #(PCB_R10)] 261 ldr r11, [r7, #(PCB_R11)] 262 ldr r12, [r7, #(PCB_R12)] 263 ldr r13, [r7, #(PCB_SP)] 264 #elif defined(_ARM_ARCH_6) 265 ldrd r8, [r7, #(PCB_R8)] 266 ldrd r10, [r7, #(PCB_R10)] 267 ldrd r12, [r7, #(PCB_R12)] 268 #else 269 add r0, r7, #PCB_R8 270 ldmia r0, {r8-r13} 271 #endif 272 273 /* Record the old lwp for pmap_activate()'s benefit */ 274 ldr r1, .Lpmap_previous_active_lwp 275 str r4, [r1] 276 277 /* rem: r4 = old lwp */ 278 /* rem: r5 = new lwp's proc */ 279 /* rem: r6 = new lwp */ 280 /* rem: r7 = new pcb */ 281 282 #ifdef ARMFPE 283 add r0, r7, #(PCB_SIZE) & 0x00ff 284 add r0, r0, #(PCB_SIZE) & 0xff00 285 bl _C_LABEL(arm_fpe_core_changecontext) 286 #endif 287 288 /* rem: r4 = old lwp */ 289 /* rem: r5 = new lwp's proc */ 290 /* rem: r6 = new lwp */ 291 /* rem: r7 = new PCB */ 292 293 /* 294 * Check for restartable atomic sequences (RAS). 295 */ 296 297 ldr r2, [r5, #(P_RASLIST)] 298 ldr r1, [r7, #(PCB_TF)] /* r1 = trapframe (used below) */ 299 teq r2, #0 /* p->p_nras == 0? */ 300 bne .Lswitch_do_ras /* no, check for one */ 301 302 .Lswitch_return: 303 /* cpu_switchto returns the old lwp */ 304 mov r0, r4 305 /* lwp_trampoline expects new lwp as it's second argument */ 306 mov r1, r6 307 308 /* 309 * Pull the registers that got pushed when cpu_switchto() was called, 310 * and return. 311 */ 312 ldmfd sp, {r4-r7, sp, pc} 313 314 .Lswitch_do_ras: 315 ldr r1, [r1, #(TF_PC)] /* second ras_lookup() arg */ 316 mov r0, r5 /* first ras_lookup() arg */ 317 bl _C_LABEL(ras_lookup) 318 cmn r0, #1 /* -1 means "not in a RAS" */ 319 ldrne r1, [r7, #(PCB_TF)] 320 strne r0, [r1, #(TF_PC)] 321 b .Lswitch_return 322 323 ENTRY(lwp_trampoline) 324 /* 325 * cpu_switchto gives us: 326 * 327 * arg0(r0) = old lwp 328 * arg1(r1) = new lwp 329 */ 330 bl _C_LABEL(lwp_startup) 331 332 mov r0, r5 333 mov r1, sp 334 mov lr, pc 335 mov pc, r4 336 337 /* Kill irq's */ 338 mrs r0, cpsr 339 orr r0, r0, #(IF32_bits) 340 msr cpsr_c, r0 341 342 PULLFRAME 343 344 movs pc, lr /* Exit */ 345 346 #ifdef __HAVE_FAST_SOFTINTS 347 /* 348 * Called at IPL_HIGH 349 * r0 = new lwp 350 * r1 = ipl for softint_dispatch 351 */ 352 ENTRY_NP(softint_switch) 353 stmfd sp!, {r4, r6, r7, lr} 354 355 ldr r7, [r0, #L_CPU] /* get curcpu */ 356 #if defined(PROCESS_ID_IS_CURLWP) 357 mrc p15, 0, r4, c13, c0, 4 /* get old lwp */ 358 #else 359 ldr r4, [r7, #(CI_CURLWP)] /* get old lwp */ 360 #endif 361 mrs r6, cpsr /* we need to save this */ 362 363 /* 364 * If the soft lwp blocks, it needs to return to softint_tramp 365 */ 366 mov r2, sp /* think ip */ 367 adr r3, softint_tramp /* think lr */ 368 stmfd sp!, {r2-r3} 369 stmfd sp!, {r4-r7} 370 371 mov r5, r0 /* save new lwp */ 372 373 ldr r2, [r4, #(L_PCB)] /* get old lwp's pcb */ 374 375 /* Save all the registers into the old lwp's pcb */ 376 #if defined(__XSCALE__) || defined(_ARM_ARCH_6) 377 strd r8, [r2, #(PCB_R8)] 378 strd r10, [r2, #(PCB_R10)] 379 strd r12, [r2, #(PCB_R12)] 380 #else 381 add r3, r2, #(PCB_R8) 382 stmia r3, {r8-r13} 383 #endif 384 385 /* this is an invariant so load before disabling intrs */ 386 ldr r2, [r5, #(L_PCB)] /* get new lwp's pcb */ 387 388 #ifndef __HAVE_UNNESTED_INTRS 389 IRQdisable 390 #endif 391 /* 392 * We're switching to a bound LWP so its l_cpu is already correct. 393 */ 394 #if defined(PROCESS_ID_IS_CURLWP) 395 mcr p15, 0, r5, c13, c0, 4 /* save new lwp */ 396 #endif 397 #if !defined(PROCESS_ID_IS_CURLWP) || defined(MULTIPROCESSOR) 398 str r5, [r7, #(CI_CURLWP)] /* save new lwp */ 399 #endif 400 401 /* 402 * Normally, we'd get {r8-r13} but since this is a softint lwp 403 * it's existing state doesn't matter. We start the stack just 404 * below the trapframe. 405 */ 406 ldr sp, [r2, #(PCB_TF)] /* get new lwp's stack ptr */ 407 408 /* At this point we can allow IRQ's again. */ 409 #ifndef __HAVE_UNNESTED_INTRS 410 IRQenable 411 #endif 412 413 /* r1 still has ipl */ 414 mov r0, r4 /* r0 has pinned (old) lwp */ 415 bl _C_LABEL(softint_dispatch) 416 /* 417 * If we've returned, we need to change everything back and return. 418 */ 419 ldr r2, [r4, #(L_PCB)] /* get pinned lwp's pcb */ 420 421 #ifndef __HAVE_UNNESTED_INTRS 422 IRQdisable 423 #endif 424 /* 425 * We don't need to restore all the registers since another lwp was 426 * never executed. But we do need the SP from the formerly pinned lwp. 427 */ 428 429 #if defined(PROCESS_ID_IS_CURLWP) 430 mcr p15, 0, r4, c13, c0, 4 /* restore pinned lwp */ 431 #endif 432 #if !defined(PROCESS_ID_IS_CURLWP) || defined(MULTIPROCESSOR) 433 str r4, [r7, #(CI_CURLWP)] /* restore pinned lwp */ 434 #endif 435 ldr sp, [r2, #(PCB_SP)] /* now running on the old stack. */ 436 437 /* At this point we can allow IRQ's again. */ 438 msr cpsr_c, r6 439 440 /* 441 * Grab the registers that got pushed at the start and return. 442 */ 443 ldmfd sp!, {r4-r7, ip, lr} /* eat switch frame */ 444 ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */ 445 446 END(softint_switch) 447 448 /* 449 * r0 = previous LWP (the soft lwp) 450 * r4 = original LWP (the current lwp) 451 * r6 = original CPSR 452 * r7 = curcpu() 453 */ 454 ENTRY_NP(softint_tramp) 455 ldr r3, [r7, #(CI_MTX_COUNT)] /* readust after mi_switch */ 456 add r3, r3, #1 457 str r3, [r7, #(CI_MTX_COUNT)] 458 459 mov r3, #0 /* tell softint_dispatch */ 460 str r3, [r0, #(L_CTXSWTCH)] /* the soft lwp blocked */ 461 462 msr cpsr_c, r6 /* restore interrupts */ 463 ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */ 464 END(softint_tramp) 465 #endif /* __HAVE_FAST_SOFTINTS */ 466
Indexes created Wed Oct 22 06:10:02 GMT 2025