cpuswitch.S revision 1.70
1 /* $NetBSD: cpuswitch.S,v 1.70 2012/09/01 14:46:51 matt Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 */ 79 80 #include "opt_armfpe.h" 81 #include "opt_arm32_pmap.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_cpuoptions.h" 84 #include "opt_lockdebug.h" 85 86 #include "assym.h" 87 #include <machine/param.h> 88 #include <machine/frame.h> 89 #include <machine/asm.h> 90 #include <machine/cpu.h> 91 92 RCSID("$NetBSD: cpuswitch.S,v 1.70 2012/09/01 14:46:51 matt Exp $") 93 94 /* LINTSTUB: include <sys/param.h> */ 95 96 #undef IRQdisable 97 #undef IRQenable 98 99 /* 100 * New experimental definitions of IRQdisable and IRQenable 101 * These keep FIQ's enabled since FIQ's are special. 102 */ 103 104 #ifdef _ARM_ARCH_6 105 #define IRQdisable cpsid i 106 #define IRQenable cpsie i 107 #else 108 #define IRQdisable \ 109 mrs r14, cpsr ; \ 110 orr r14, r14, #(I32_bit) ; \ 111 msr cpsr_c, r14 112 113 #define IRQenable \ 114 mrs r14, cpsr ; \ 115 bic r14, r14, #(I32_bit) ; \ 116 msr cpsr_c, r14 117 118 #endif 119 120 .text 121 .Lpmap_previous_active_lwp: 122 .word _C_LABEL(pmap_previous_active_lwp) 123 124 /* 125 * struct lwp * 126 * cpu_switchto(struct lwp *current, struct lwp *next) 127 * 128 * Switch to the specified next LWP 129 * Arguments: 130 * 131 * r0 'struct lwp *' of the current LWP (or NULL if exiting) 132 * r1 'struct lwp *' of the LWP to switch to 133 * r2 returning 134 */ 135 ENTRY(cpu_switchto) 136 mov ip, sp 137 stmfd sp!, {r4-r7, ip, lr} 138 139 /* move lwps into caller saved registers */ 140 mov r6, r1 141 mov r4, r0 142 143 #ifdef TPIDRPRW_IS_CURCPU 144 GET_CURCPU(r7) 145 #elif defined(TPIDRPRW_IS_CURLWP) 146 mcr p15, 0, r0, c13, c0, 4 /* get old lwp (r4 maybe 0) */ 147 ldr r7, [r0, #(L_CPU)] /* get cpu from old lwp */ 148 #elif !defined(MULTIPROCESSOR) 149 ldr r7, [r6, #L_CPU] /* get cpu from new lwp */ 150 #else 151 #error curcpu() method not defined 152 #endif 153 154 /* rem: r4 = old lwp */ 155 /* rem: r6 = new lwp */ 156 /* rem: r7 = curcpu() */ 157 158 #ifndef __HAVE_UNNESTED_INTRS 159 IRQdisable 160 #endif 161 162 #ifdef MULTIPROCESSOR 163 str r7, [r6, #(L_CPU)] 164 #else 165 /* l->l_cpu initialized in fork1() for single-processor */ 166 #endif 167 168 #if defined(TPIDRPRW_IS_CURLWP) 169 mcr p15, 0, r6, c13, c0, 4 /* set current lwp */ 170 #endif 171 /* We have a new curlwp now so make a note it */ 172 str r6, [r7, #(CI_CURLWP)] 173 174 /* Get the new pcb */ 175 ldr r7, [r6, #(L_PCB)] 176 177 /* At this point we can allow IRQ's again. */ 178 #ifndef __HAVE_UNNESTED_INTRS 179 IRQenable 180 #endif 181 182 /* rem: r4 = old lwp */ 183 /* rem: r6 = new lwp */ 184 /* rem: r7 = new pcb */ 185 /* rem: interrupts are enabled */ 186 187 /* 188 * If the old lwp on entry to cpu_switchto was zero then the 189 * process that called it was exiting. This means that we do 190 * not need to save the current context. Instead we can jump 191 * straight to restoring the context for the new process. 192 */ 193 teq r4, #0 194 beq .Ldo_switch 195 196 /* rem: r4 = old lwp */ 197 /* rem: r6 = new lwp */ 198 /* rem: r7 = new pcb */ 199 /* rem: interrupts are enabled */ 200 201 /* Save old context */ 202 203 /* Get the user structure for the old lwp. */ 204 ldr r5, [r4, #(L_PCB)] 205 206 /* Save all the registers in the old lwp's pcb */ 207 #if defined(__XSCALE__) || defined(_ARM_ARCH_6) 208 strd r8, [r5, #(PCB_R8)] 209 strd r10, [r5, #(PCB_R10)] 210 strd r12, [r5, #(PCB_R12)] 211 #else 212 add r0, r5, #(PCB_R8) 213 stmia r0, {r8-r13} 214 #endif 215 216 #ifdef _ARM_ARCH_6 217 /* 218 * Save user read/write thread/process id register 219 */ 220 mrc p15, 0, r0, c13, c0, 2 221 str r0, [r5, #(PCB_USER_PID_RW)] 222 #endif 223 /* 224 * NOTE: We can now use r8-r13 until it is time to restore 225 * them for the new process. 226 */ 227 228 /* rem: r4 = old lwp */ 229 /* rem: r5 = old pcb */ 230 /* rem: r6 = new lwp */ 231 /* rem: r7 = new pcb */ 232 /* rem: interrupts are enabled */ 233 234 /* Restore saved context */ 235 236 .Ldo_switch: 237 /* rem: r4 = old lwp */ 238 /* rem: r6 = new lwp */ 239 /* rem: r7 = new pcb */ 240 /* rem: interrupts are enabled */ 241 242 #ifdef _ARM_ARCH_6 243 /* 244 * Restore user thread/process id registers 245 */ 246 ldr r0, [r7, #(PCB_USER_PID_RW)] 247 mcr p15, 0, r0, c13, c0, 2 248 ldr r0, [r6, #(L_PRIVATE)] 249 mcr p15, 0, r0, c13, c0, 3 250 #endif 251 252 ldr r5, [r6, #(L_PROC)] /* fetch the proc for below */ 253 254 /* Restore all the saved registers */ 255 #ifdef __XSCALE__ 256 ldr r8, [r7, #(PCB_R8)] 257 ldr r9, [r7, #(PCB_R9)] 258 ldr r10, [r7, #(PCB_R10)] 259 ldr r11, [r7, #(PCB_R11)] 260 ldr r12, [r7, #(PCB_R12)] 261 ldr r13, [r7, #(PCB_SP)] 262 #elif defined(_ARM_ARCH_6) 263 ldrd r8, [r7, #(PCB_R8)] 264 ldrd r10, [r7, #(PCB_R10)] 265 ldrd r12, [r7, #(PCB_R12)] 266 #else 267 add r0, r7, #PCB_R8 268 ldmia r0, {r8-r13} 269 #endif 270 271 /* Record the old lwp for pmap_activate()'s benefit */ 272 ldr r1, .Lpmap_previous_active_lwp 273 str r4, [r1] 274 275 /* rem: r4 = old lwp */ 276 /* rem: r5 = new lwp's proc */ 277 /* rem: r6 = new lwp */ 278 /* rem: r7 = new pcb */ 279 280 #ifdef ARMFPE 281 add r0, r7, #(PCB_SIZE) & 0x00ff 282 add r0, r0, #(PCB_SIZE) & 0xff00 283 bl _C_LABEL(arm_fpe_core_changecontext) 284 #endif 285 286 /* rem: r4 = old lwp */ 287 /* rem: r5 = new lwp's proc */ 288 /* rem: r6 = new lwp */ 289 /* rem: r7 = new PCB */ 290 291 /* 292 * Check for restartable atomic sequences (RAS). 293 */ 294 295 ldr r2, [r5, #(P_RASLIST)] 296 ldr r1, [r6, #(L_MD_TF)] /* r1 = trapframe (used below) */ 297 teq r2, #0 /* p->p_nras == 0? */ 298 bne .Lswitch_do_ras /* no, check for one */ 299 300 .Lswitch_return: 301 /* cpu_switchto returns the old lwp */ 302 mov r0, r4 303 /* lwp_trampoline expects new lwp as it's second argument */ 304 mov r1, r6 305 306 #ifdef _ARM_ARCH_7 307 clrex /* cause any subsequent STREX* to fail */ 308 #endif 309 310 /* 311 * Pull the registers that got pushed when cpu_switchto() was called, 312 * and return. 313 */ 314 ldmfd sp, {r4-r7, sp, pc} 315 316 .Lswitch_do_ras: 317 ldr r1, [r1, #(TF_PC)] /* second ras_lookup() arg */ 318 mov r0, r5 /* first ras_lookup() arg */ 319 bl _C_LABEL(ras_lookup) 320 cmn r0, #1 /* -1 means "not in a RAS" */ 321 ldrne r1, [r6, #(L_MD_TF)] 322 strne r0, [r1, #(TF_PC)] 323 b .Lswitch_return 324 325 ENTRY(lwp_trampoline) 326 /* 327 * cpu_switchto gives us: 328 * arg0(r0) = old lwp 329 * arg1(r1) = new lwp 330 * setup by cpu_lwp_fork: 331 * r4 = func to call 332 * r5 = arg to func 333 * r6 = <unused> 334 * r7 = spsr mode 335 */ 336 bl _C_LABEL(lwp_startup) 337 338 mov r0, r5 339 mov r1, sp 340 #ifdef _ARM_ARCH_5 341 blx r4 342 #else 343 mov lr, pc 344 mov pc, r4 345 #endif 346 347 GET_CPSR(r0) 348 CPSID_I(r0, r0) /* Kill irq's */ 349 350 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 351 PULLFRAME 352 353 movs pc, lr /* Exit */ 354 355 AST_ALIGNMENT_FAULT_LOCALS 356 357 #ifdef __HAVE_FAST_SOFTINTS 358 /* 359 * Called at IPL_HIGH 360 * r0 = new lwp 361 * r1 = ipl for softint_dispatch 362 */ 363 ENTRY_NP(softint_switch) 364 stmfd sp!, {r4, r6, r7, lr} 365 366 ldr r7, [r0, #L_CPU] /* get curcpu */ 367 #if defined(TPIDRPRW_IS_CURLWP) 368 mrc p15, 0, r4, c13, c0, 4 /* get old lwp */ 369 #else 370 ldr r4, [r7, #(CI_CURLWP)] /* get old lwp */ 371 #endif 372 mrs r6, cpsr /* we need to save this */ 373 374 /* 375 * If the soft lwp blocks, it needs to return to softint_tramp 376 */ 377 mov r2, sp /* think ip */ 378 adr r3, softint_tramp /* think lr */ 379 stmfd sp!, {r2-r3} 380 stmfd sp!, {r4-r7} 381 382 mov r5, r0 /* save new lwp */ 383 384 ldr r2, [r4, #(L_PCB)] /* get old lwp's pcb */ 385 386 /* Save all the registers into the old lwp's pcb */ 387 #if defined(__XSCALE__) || defined(_ARM_ARCH_6) 388 strd r8, [r2, #(PCB_R8)] 389 strd r10, [r2, #(PCB_R10)] 390 strd r12, [r2, #(PCB_R12)] 391 #else 392 add r3, r2, #(PCB_R8) 393 stmia r3, {r8-r13} 394 #endif 395 396 /* this is an invariant so load before disabling intrs */ 397 ldr r2, [r5, #(L_PCB)] /* get new lwp's pcb */ 398 399 #ifndef __HAVE_UNNESTED_INTRS 400 IRQdisable 401 #endif 402 /* 403 * We're switching to a bound LWP so its l_cpu is already correct. 404 */ 405 #if defined(TPIDRPRW_IS_CURLWP) 406 mcr p15, 0, r5, c13, c0, 4 /* save new lwp */ 407 #endif 408 str r5, [r7, #(CI_CURLWP)] /* save new lwp */ 409 410 /* 411 * Normally, we'd get {r8-r13} but since this is a softint lwp 412 * it's existing state doesn't matter. We start the stack just 413 * below the trapframe. 414 */ 415 ldr sp, [r5, #(L_MD_TF)] /* get new lwp's stack ptr */ 416 417 /* At this point we can allow IRQ's again. */ 418 #ifndef __HAVE_UNNESTED_INTRS 419 IRQenable 420 #endif 421 422 /* r1 still has ipl */ 423 mov r0, r4 /* r0 has pinned (old) lwp */ 424 bl _C_LABEL(softint_dispatch) 425 /* 426 * If we've returned, we need to change everything back and return. 427 */ 428 ldr r2, [r4, #(L_PCB)] /* get pinned lwp's pcb */ 429 430 #ifndef __HAVE_UNNESTED_INTRS 431 IRQdisable 432 #endif 433 /* 434 * We don't need to restore all the registers since another lwp was 435 * never executed. But we do need the SP from the formerly pinned lwp. 436 */ 437 438 #if defined(TPIDRPRW_IS_CURLWP) 439 mcr p15, 0, r4, c13, c0, 4 /* restore pinned lwp */ 440 #endif 441 str r4, [r7, #(CI_CURLWP)] /* restore pinned lwp */ 442 ldr sp, [r2, #(PCB_SP)] /* now running on the old stack. */ 443 444 /* At this point we can allow IRQ's again. */ 445 msr cpsr_c, r6 446 447 /* 448 * Grab the registers that got pushed at the start and return. 449 */ 450 ldmfd sp!, {r4-r7, ip, lr} /* eat switch frame */ 451 ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */ 452 453 END(softint_switch) 454 455 /* 456 * r0 = previous LWP (the soft lwp) 457 * r4 = original LWP (the current lwp) 458 * r6 = original CPSR 459 * r7 = curcpu() 460 */ 461 ENTRY_NP(softint_tramp) 462 ldr r3, [r7, #(CI_MTX_COUNT)] /* readust after mi_switch */ 463 add r3, r3, #1 464 str r3, [r7, #(CI_MTX_COUNT)] 465 466 mov r3, #0 /* tell softint_dispatch */ 467 str r3, [r0, #(L_CTXSWTCH)] /* the soft lwp blocked */ 468 469 msr cpsr_c, r6 /* restore interrupts */ 470 ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */ 471 END(softint_tramp) 472 #endif /* __HAVE_FAST_SOFTINTS */ 473
Indexes created Wed Oct 22 13:09:56 GMT 2025