cpuswitch.S revision 1.72.2.3
1 /* $NetBSD: cpuswitch.S,v 1.72.2.3 2013/06/23 06:19:59 tls Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 */ 79 80 #include "opt_armfpe.h" 81 #include "opt_arm32_pmap.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_cpuoptions.h" 84 #include "opt_lockdebug.h" 85 86 #include "assym.h" 87 #include <machine/asm.h> 88 #include <machine/cpu.h> 89 #include <machine/frame.h> 90 91 RCSID("$NetBSD: cpuswitch.S,v 1.72.2.3 2013/06/23 06:19:59 tls Exp $") 92 93 /* LINTSTUB: include <sys/param.h> */ 94 95 #undef IRQdisable 96 #undef IRQenable 97 98 /* 99 * New experimental definitions of IRQdisable and IRQenable 100 * These keep FIQ's enabled since FIQ's are special. 101 */ 102 103 #ifdef _ARM_ARCH_6 104 #define IRQdisable cpsid i 105 #define IRQenable cpsie i 106 #else 107 #define IRQdisable \ 108 mrs r14, cpsr ; \ 109 orr r14, r14, #(I32_bit) ; \ 110 msr cpsr_c, r14 111 112 #define IRQenable \ 113 mrs r14, cpsr ; \ 114 bic r14, r14, #(I32_bit) ; \ 115 msr cpsr_c, r14 116 117 #endif 118 119 .text 120 .Lpmap_previous_active_lwp: 121 .word _C_LABEL(pmap_previous_active_lwp) 122 123 /* 124 * struct lwp * 125 * cpu_switchto(struct lwp *current, struct lwp *next) 126 * 127 * Switch to the specified next LWP 128 * Arguments: 129 * 130 * r0 'struct lwp *' of the current LWP (or NULL if exiting) 131 * r1 'struct lwp *' of the LWP to switch to 132 * r2 returning 133 */ 134 ENTRY(cpu_switchto) 135 mov ip, sp 136 stmfd sp!, {r4-r7, ip, lr} 137 138 /* move lwps into caller saved registers */ 139 mov r6, r1 140 mov r4, r0 141 142 #ifdef TPIDRPRW_IS_CURCPU 143 GET_CURCPU(r3) 144 #elif defined(TPIDRPRW_IS_CURLWP) 145 mcr p15, 0, r0, c13, c0, 4 /* get old lwp (r4 maybe 0) */ 146 ldr r3, [r0, #(L_CPU)] /* get cpu from old lwp */ 147 #elif !defined(MULTIPROCESSOR) 148 ldr r3, [r6, #L_CPU] /* get cpu from new lwp */ 149 #else 150 #error curcpu() method not defined 151 #endif 152 153 /* rem: r3 = curcpu() */ 154 /* rem: r4 = old lwp */ 155 /* rem: r6 = new lwp */ 156 157 #ifndef __HAVE_UNNESTED_INTRS 158 IRQdisable 159 #endif 160 161 #ifdef MULTIPROCESSOR 162 str r3, [r6, #(L_CPU)] 163 #else 164 /* l->l_cpu initialized in fork1() for single-processor */ 165 #endif 166 167 #if defined(TPIDRPRW_IS_CURLWP) 168 mcr p15, 0, r6, c13, c0, 4 /* set current lwp */ 169 #endif 170 /* We have a new curlwp now so make a note it */ 171 str r6, [r3, #(CI_CURLWP)] 172 173 /* Get the new pcb */ 174 ldr r7, [r6, #(L_PCB)] 175 176 /* At this point we can allow IRQ's again. */ 177 #ifndef __HAVE_UNNESTED_INTRS 178 IRQenable 179 #endif 180 181 /* rem: r3 = curlwp */ 182 /* rem: r4 = old lwp */ 183 /* rem: r6 = new lwp */ 184 /* rem: r7 = new pcb */ 185 /* rem: interrupts are enabled */ 186 187 /* 188 * If the old lwp on entry to cpu_switchto was zero then the 189 * process that called it was exiting. This means that we do 190 * not need to save the current context. Instead we can jump 191 * straight to restoring the context for the new process. 192 */ 193 teq r4, #0 194 beq .Ldo_switch 195 196 /* rem: r3 = curlwp */ 197 /* rem: r4 = old lwp */ 198 /* rem: r6 = new lwp */ 199 /* rem: r7 = new pcb */ 200 /* rem: interrupts are enabled */ 201 202 /* Save old context */ 203 204 /* Get the user structure for the old lwp. */ 205 ldr r5, [r4, #(L_PCB)] 206 207 /* Save all the registers in the old lwp's pcb */ 208 #if defined(_ARM_ARCH_DWORD_OK) 209 strd r8, [r5, #(PCB_R8)] 210 strd r10, [r5, #(PCB_R10)] 211 strd r12, [r5, #(PCB_R12)] 212 #else 213 add r0, r5, #(PCB_R8) 214 stmia r0, {r8-r13} 215 #endif 216 217 #ifdef _ARM_ARCH_6 218 /* 219 * Save user read/write thread/process id register 220 */ 221 mrc p15, 0, r0, c13, c0, 2 222 str r0, [r5, #(PCB_USER_PID_RW)] 223 #endif 224 /* 225 * NOTE: We can now use r8-r13 until it is time to restore 226 * them for the new process. 227 */ 228 229 /* rem: r3 = curlwp */ 230 /* rem: r4 = old lwp */ 231 /* rem: r5 = old pcb */ 232 /* rem: r6 = new lwp */ 233 /* rem: r7 = new pcb */ 234 /* rem: interrupts are enabled */ 235 236 /* Restore saved context */ 237 238 .Ldo_switch: 239 /* rem: r3 = curlwp */ 240 /* rem: r4 = old lwp */ 241 /* rem: r6 = new lwp */ 242 /* rem: r7 = new pcb */ 243 /* rem: interrupts are enabled */ 244 245 #ifdef _ARM_ARCH_6 246 /* 247 * Restore user thread/process id registers 248 */ 249 ldr r0, [r7, #(PCB_USER_PID_RW)] 250 mcr p15, 0, r0, c13, c0, 2 251 ldr r0, [r6, #(L_PRIVATE)] 252 mcr p15, 0, r0, c13, c0, 3 253 #endif 254 255 #ifdef FPU_VFP 256 /* 257 * If we have a VFP, we need to load FPEXC. 258 */ 259 ldr r0, [r3, #(CI_VFP_ID)] 260 cmp r0, #0 261 ldrne r0, [r7, #(PCB_VFP_FPEXC)] 262 mcrne p10, 7, r0, c8, c0, 0 263 #endif 264 265 ldr r5, [r6, #(L_PROC)] /* fetch the proc for below */ 266 267 /* Restore all the saved registers */ 268 #ifdef __XSCALE__ 269 ldr r8, [r7, #(PCB_R8)] 270 ldr r9, [r7, #(PCB_R9)] 271 ldr r10, [r7, #(PCB_R10)] 272 ldr r11, [r7, #(PCB_R11)] 273 ldr r12, [r7, #(PCB_R12)] 274 ldr r13, [r7, #(PCB_KSP)] /* sp */ 275 #elif defined(_ARM_ARCH_DWORD_OK) 276 ldrd r8, [r7, #(PCB_R8)] 277 ldrd r10, [r7, #(PCB_R10)] 278 ldrd r12, [r7, #(PCB_R12)] /* sp */ 279 #else 280 add r0, r7, #PCB_R8 281 ldmia r0, {r8-r13} 282 #endif 283 284 /* Record the old lwp for pmap_activate()'s benefit */ 285 ldr r1, .Lpmap_previous_active_lwp /* XXXSMP */ 286 str r4, [r1] 287 288 /* rem: r4 = old lwp */ 289 /* rem: r5 = new lwp's proc */ 290 /* rem: r6 = new lwp */ 291 /* rem: r7 = new pcb */ 292 293 /* 294 * Check for restartable atomic sequences (RAS). 295 */ 296 297 ldr r2, [r5, #(P_RASLIST)] 298 ldr r1, [r6, #(L_MD_TF)] /* r1 = trapframe (used below) */ 299 teq r2, #0 /* p->p_nras == 0? */ 300 bne .Lswitch_do_ras /* no, check for one */ 301 302 .Lswitch_return: 303 /* cpu_switchto returns the old lwp */ 304 mov r0, r4 305 /* lwp_trampoline expects new lwp as it's second argument */ 306 mov r1, r6 307 308 #ifdef _ARM_ARCH_7 309 clrex /* cause any subsequent STREX* to fail */ 310 #endif 311 312 /* 313 * Pull the registers that got pushed when cpu_switchto() was called, 314 * and return. 315 */ 316 ldmfd sp, {r4-r7, sp, pc} 317 318 .Lswitch_do_ras: 319 ldr r1, [r1, #(TF_PC)] /* second ras_lookup() arg */ 320 mov r0, r5 /* first ras_lookup() arg */ 321 bl _C_LABEL(ras_lookup) 322 cmn r0, #1 /* -1 means "not in a RAS" */ 323 ldrne r1, [r6, #(L_MD_TF)] 324 strne r0, [r1, #(TF_PC)] 325 b .Lswitch_return 326 327 ENTRY_NP(lwp_trampoline) 328 /* 329 * cpu_switchto gives us: 330 * arg0(r0) = old lwp 331 * arg1(r1) = new lwp 332 * setup by cpu_lwp_fork: 333 * r4 = func to call 334 * r5 = arg to func 335 * r6 = <unused> 336 * r7 = spsr mode 337 */ 338 bl _C_LABEL(lwp_startup) 339 340 mov fp, #0 /* top stack frame */ 341 mov r0, r5 342 mov r1, sp 343 #ifdef _ARM_ARCH_5 344 blx r4 345 #else 346 mov lr, pc 347 mov pc, r4 348 #endif 349 350 GET_CPSR(r0) 351 CPSID_I(r0, r0) /* Kill irq's */ 352 353 GET_CURCPU(r4) /* for DO_AST */ 354 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 355 PULLFRAME 356 357 movs pc, lr /* Exit */ 358 359 AST_ALIGNMENT_FAULT_LOCALS 360 361 #ifdef __HAVE_FAST_SOFTINTS 362 /* 363 * Called at IPL_HIGH 364 * r0 = new lwp 365 * r1 = ipl for softint_dispatch 366 */ 367 ENTRY_NP(softint_switch) 368 stmfd sp!, {r4, r6, r7, lr} 369 370 ldr r7, [r0, #L_CPU] /* get curcpu */ 371 #if defined(TPIDRPRW_IS_CURLWP) 372 mrc p15, 0, r4, c13, c0, 4 /* get old lwp */ 373 #else 374 ldr r4, [r7, #(CI_CURLWP)] /* get old lwp */ 375 #endif 376 mrs r6, cpsr /* we need to save this */ 377 378 /* 379 * If the soft lwp blocks, it needs to return to softint_tramp 380 */ 381 mov r2, sp /* think ip */ 382 adr r3, softint_tramp /* think lr */ 383 stmfd sp!, {r2-r3} 384 stmfd sp!, {r4-r7} 385 386 mov r5, r0 /* save new lwp */ 387 388 ldr r2, [r4, #(L_PCB)] /* get old lwp's pcb */ 389 390 /* Save all the registers into the old lwp's pcb */ 391 #if defined(__XSCALE__) || defined(_ARM_ARCH_6) 392 strd r8, [r2, #(PCB_R8)] 393 strd r10, [r2, #(PCB_R10)] 394 strd r12, [r2, #(PCB_R12)] 395 #else 396 add r3, r2, #(PCB_R8) 397 stmia r3, {r8-r13} 398 #endif 399 400 /* this is an invariant so load before disabling intrs */ 401 ldr r2, [r5, #(L_PCB)] /* get new lwp's pcb */ 402 403 #ifndef __HAVE_UNNESTED_INTRS 404 IRQdisable 405 #endif 406 /* 407 * We're switching to a bound LWP so its l_cpu is already correct. 408 */ 409 #if defined(TPIDRPRW_IS_CURLWP) 410 mcr p15, 0, r5, c13, c0, 4 /* save new lwp */ 411 #endif 412 str r5, [r7, #(CI_CURLWP)] /* save new lwp */ 413 414 /* 415 * Normally, we'd get {r8-r13} but since this is a softint lwp 416 * it's existing state doesn't matter. We start the stack just 417 * below the trapframe. 418 */ 419 ldr sp, [r5, #(L_MD_TF)] /* get new lwp's stack ptr */ 420 421 /* At this point we can allow IRQ's again. */ 422 #ifndef __HAVE_UNNESTED_INTRS 423 IRQenable 424 #endif 425 426 /* r1 still has ipl */ 427 mov r0, r4 /* r0 has pinned (old) lwp */ 428 bl _C_LABEL(softint_dispatch) 429 /* 430 * If we've returned, we need to change everything back and return. 431 */ 432 ldr r2, [r4, #(L_PCB)] /* get pinned lwp's pcb */ 433 434 #ifndef __HAVE_UNNESTED_INTRS 435 IRQdisable 436 #endif 437 /* 438 * We don't need to restore all the registers since another lwp was 439 * never executed. But we do need the SP from the formerly pinned lwp. 440 */ 441 442 #if defined(TPIDRPRW_IS_CURLWP) 443 mcr p15, 0, r4, c13, c0, 4 /* restore pinned lwp */ 444 #endif 445 str r4, [r7, #(CI_CURLWP)] /* restore pinned lwp */ 446 ldr sp, [r2, #(PCB_KSP)] /* now running on the old stack. */ 447 448 /* At this point we can allow IRQ's again. */ 449 msr cpsr_c, r6 450 451 /* 452 * Grab the registers that got pushed at the start and return. 453 */ 454 ldmfd sp!, {r4-r7, ip, lr} /* eat switch frame */ 455 ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */ 456 457 END(softint_switch) 458 459 /* 460 * r0 = previous LWP (the soft lwp) 461 * r4 = original LWP (the current lwp) 462 * r6 = original CPSR 463 * r7 = curcpu() 464 */ 465 ENTRY_NP(softint_tramp) 466 ldr r3, [r7, #(CI_MTX_COUNT)] /* readust after mi_switch */ 467 add r3, r3, #1 468 str r3, [r7, #(CI_MTX_COUNT)] 469 470 mov r3, #0 /* tell softint_dispatch */ 471 str r3, [r0, #(L_CTXSWTCH)] /* the soft lwp blocked */ 472 473 msr cpsr_c, r6 /* restore interrupts */ 474 ldmfd sp!, {r4, r6, r7, pc} /* pop stack and return */ 475 END(softint_tramp) 476 #endif /* __HAVE_FAST_SOFTINTS */ 477
Indexes created Sat Oct 25 10:09:55 GMT 2025