db_interface.c revision 1.19
1 /* $NetBSD: db_interface.c,v 1.19 2002/04/09 19:37:16 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 #include "opt_ddb.h" 37 38 #include <sys/param.h> 39 #include <sys/proc.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> /* just for boothowto */ 42 #include <sys/exec.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <arm/arm32/db_machdep.h> 47 #include <arm/arm32/katelib.h> 48 #include <arm/undefined.h> 49 #include <ddb/db_access.h> 50 #include <ddb/db_command.h> 51 #include <ddb/db_output.h> 52 #include <ddb/db_variables.h> 53 #include <ddb/db_sym.h> 54 #include <ddb/db_extern.h> 55 #include <ddb/db_interface.h> 56 #include <dev/cons.h> 57 58 static int nil; 59 60 int db_access_und_sp __P((const struct db_variable *, db_expr_t *, int)); 61 int db_access_abt_sp __P((const struct db_variable *, db_expr_t *, int)); 62 int db_access_irq_sp __P((const struct db_variable *, db_expr_t *, int)); 63 u_int db_fetch_reg __P((int, db_regs_t *)); 64 65 int db_trapper __P((u_int, u_int, trapframe_t *, int)); 66 67 const struct db_variable db_regs[] = { 68 { "spsr", (long *)&DDB_REGS->tf_spsr, FCN_NULL, }, 69 { "r0", (long *)&DDB_REGS->tf_r0, FCN_NULL, }, 70 { "r1", (long *)&DDB_REGS->tf_r1, FCN_NULL, }, 71 { "r2", (long *)&DDB_REGS->tf_r2, FCN_NULL, }, 72 { "r3", (long *)&DDB_REGS->tf_r3, FCN_NULL, }, 73 { "r4", (long *)&DDB_REGS->tf_r4, FCN_NULL, }, 74 { "r5", (long *)&DDB_REGS->tf_r5, FCN_NULL, }, 75 { "r6", (long *)&DDB_REGS->tf_r6, FCN_NULL, }, 76 { "r7", (long *)&DDB_REGS->tf_r7, FCN_NULL, }, 77 { "r8", (long *)&DDB_REGS->tf_r8, FCN_NULL, }, 78 { "r9", (long *)&DDB_REGS->tf_r9, FCN_NULL, }, 79 { "r10", (long *)&DDB_REGS->tf_r10, FCN_NULL, }, 80 { "r11", (long *)&DDB_REGS->tf_r11, FCN_NULL, }, 81 { "r12", (long *)&DDB_REGS->tf_r12, FCN_NULL, }, 82 { "usr_sp", (long *)&DDB_REGS->tf_usr_sp, FCN_NULL, }, 83 { "usr_lr", (long *)&DDB_REGS->tf_usr_lr, FCN_NULL, }, 84 { "svc_sp", (long *)&DDB_REGS->tf_svc_sp, FCN_NULL, }, 85 { "svc_lr", (long *)&DDB_REGS->tf_svc_lr, FCN_NULL, }, 86 { "pc", (long *)&DDB_REGS->tf_pc, FCN_NULL, }, 87 { "und_sp", (long *)&nil, db_access_und_sp, }, 88 { "abt_sp", (long *)&nil, db_access_abt_sp, }, 89 { "irq_sp", (long *)&nil, db_access_irq_sp, }, 90 }; 91 92 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 93 94 extern label_t *db_recover; 95 96 int db_active = 0; 97 98 int 99 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 100 { 101 102 if (rw == DB_VAR_GET) 103 *valp = get_stackptr(PSR_UND32_MODE); 104 return(0); 105 } 106 107 int 108 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 109 { 110 111 if (rw == DB_VAR_GET) 112 *valp = get_stackptr(PSR_ABT32_MODE); 113 return(0); 114 } 115 116 int 117 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 118 { 119 120 if (rw == DB_VAR_GET) 121 *valp = get_stackptr(PSR_IRQ32_MODE); 122 return(0); 123 } 124 125 /* 126 * kdb_trap - field a TRACE or BPT trap 127 */ 128 int 129 kdb_trap(int type, db_regs_t *regs) 130 { 131 int s; 132 133 switch (type) { 134 case T_BREAKPOINT: /* breakpoint */ 135 case -1: /* keyboard interrupt */ 136 break; 137 default: 138 db_printf("kernel: trap"); 139 if (db_recover != 0) { 140 db_error("Faulted in DDB; continuing...\n"); 141 /*NOTREACHED*/ 142 } 143 } 144 145 /* Should switch to kdb`s own stack here. */ 146 147 ddb_regs = *regs; 148 149 s = splhigh(); 150 db_active++; 151 cnpollc(TRUE); 152 db_trap(type, 0/*code*/); 153 cnpollc(FALSE); 154 db_active--; 155 splx(s); 156 157 *regs = ddb_regs; 158 159 return (1); 160 } 161 162 163 static int 164 db_validate_address(vaddr_t addr) 165 { 166 struct proc *p = curproc; 167 struct pmap *pmap; 168 169 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap) 170 pmap = pmap_kernel(); 171 else 172 pmap = p->p_vmspace->vm_map.pmap; 173 174 return (pmap_extract(pmap, addr, NULL) == FALSE); 175 } 176 177 /* 178 * Read bytes from kernel address space for debugger. 179 */ 180 void 181 db_read_bytes(addr, size, data) 182 vm_offset_t addr; 183 size_t size; 184 char *data; 185 { 186 char *src; 187 188 src = (char *)addr; 189 190 while (size-- > 0) { 191 if (db_validate_address((u_int)src)) { 192 db_printf("address %p is invalid\n", src); 193 return; 194 } 195 *data++ = *src++; 196 } 197 } 198 199 static void 200 db_write_text(vaddr_t addr, size_t size, char *data) 201 { 202 struct pmap *pmap = pmap_kernel(); 203 pd_entry_t *pde, oldpde, tmppde; 204 pt_entry_t *pte, oldpte, tmppte; 205 vaddr_t pgva; 206 size_t limit, savesize; 207 char *dst; 208 209 if ((savesize = size) == 0) 210 return; 211 212 dst = (char *) addr; 213 214 do { 215 /* Get the PDE of the current VA. */ 216 pde = pmap_pde(pmap, (vaddr_t) dst); 217 switch ((oldpde = *pde) & L1_TYPE_MASK) { 218 case L1_TYPE_S: 219 pgva = (vaddr_t)dst & L1_S_FRAME; 220 limit = L1_S_SIZE - ((vaddr_t)dst & L1_S_OFFSET); 221 222 tmppde = oldpde | L1_S_PROT_W; 223 *pde = tmppde; 224 break; 225 226 case L1_TYPE_C: 227 pgva = (vaddr_t)dst & L2_S_FRAME; 228 limit = L2_S_SIZE - ((vaddr_t)dst & L2_S_OFFSET); 229 230 pte = vtopte(pgva); 231 oldpte = *pte; 232 tmppte = oldpte | L2_S_PROT_W; 233 *pte = tmppte; 234 break; 235 236 default: 237 printf(" address 0x%08lx not a valid page\n", 238 (vaddr_t) dst); 239 return; 240 } 241 cpu_tlb_flushD_SE(pgva); 242 cpu_cpwait(); 243 244 if (limit > size) 245 limit = size; 246 size -= limit; 247 248 /* 249 * Page is now writable. Do as much access as we 250 * can in this page. 251 */ 252 for (; limit > 0; limit--) 253 *dst++ = *data++; 254 255 /* 256 * Restore old mapping permissions. 257 */ 258 switch (oldpde & L1_TYPE_MASK) { 259 case L1_TYPE_S: 260 *pde = oldpde; 261 break; 262 263 case L1_TYPE_C: 264 *pte = oldpte; 265 break; 266 } 267 cpu_tlb_flushD_SE(pgva); 268 cpu_cpwait(); 269 } while (size != 0); 270 271 /* Sync the I-cache. */ 272 cpu_icache_sync_range(addr, savesize); 273 } 274 275 /* 276 * Write bytes to kernel address space for debugger. 277 */ 278 void 279 db_write_bytes(vaddr_t addr, size_t size, char *data) 280 { 281 extern char etext[]; 282 char *dst; 283 size_t loop; 284 285 /* If any part is in kernel text, use db_write_text() */ 286 if (addr >= KERNEL_TEXT_BASE && addr < (vaddr_t) etext) { 287 db_write_text(addr, size, data); 288 return; 289 } 290 291 dst = (char *)addr; 292 loop = size; 293 while (loop-- > 0) { 294 if (db_validate_address((u_int)dst)) { 295 db_printf("address %p is invalid\n", dst); 296 return; 297 } 298 *dst++ = *data++; 299 } 300 /* make sure the caches and memory are in sync */ 301 cpu_icache_sync_range(addr, size); 302 303 /* In case the current page tables have been modified ... */ 304 cpu_tlb_flushID(); 305 cpu_cpwait(); 306 } 307 308 void 309 cpu_Debugger(void) 310 { 311 asm(".word 0xe7ffffff"); 312 } 313 314 const struct db_command db_machine_command_table[] = { 315 { "frame", db_show_frame_cmd, 0, NULL }, 316 { "panic", db_show_panic_cmd, 0, NULL }, 317 #ifdef ARM32_DB_COMMANDS 318 ARM32_DB_COMMANDS, 319 #endif 320 { NULL, NULL, 0, NULL } 321 }; 322 323 int 324 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 325 { 326 327 if (fault_code == 0) { 328 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 329 kdb_trap(T_BREAKPOINT, frame); 330 else 331 kdb_trap(-1, frame); 332 } else 333 return (1); 334 return (0); 335 } 336 337 extern u_int esym; 338 extern u_int end; 339 340 static struct undefined_handler db_uh; 341 342 void 343 db_machine_init(void) 344 { 345 #ifndef __ELF__ 346 struct exec *kernexec = (struct exec *)KERNEL_TEXT_BASE; 347 int len; 348 349 /* 350 * The boot loader currently loads the kernel with the a.out 351 * header still attached. 352 */ 353 354 if (kernexec->a_syms == 0) { 355 printf("ddb: No symbol table\n"); 356 } else { 357 /* cover the symbols themselves (what is the int for?? XXX) */ 358 esym = (int)&end + kernexec->a_syms + sizeof(int); 359 360 /* 361 * and the string table. (int containing size of string 362 * table is included in string table size). 363 */ 364 len = *((u_int *)esym); 365 esym += (len + (sizeof(u_int) - 1)) & ~(sizeof(u_int) - 1); 366 } 367 #endif 368 369 /* 370 * We get called before malloc() is available, so supply a static 371 * struct undefined_handler. 372 */ 373 db_uh.uh_handler = db_trapper; 374 install_coproc_handler_static(0, &db_uh); 375 } 376 377 u_int 378 db_fetch_reg(int reg, db_regs_t *db_regs) 379 { 380 381 switch (reg) { 382 case 0: 383 return (db_regs->tf_r0); 384 case 1: 385 return (db_regs->tf_r1); 386 case 2: 387 return (db_regs->tf_r2); 388 case 3: 389 return (db_regs->tf_r3); 390 case 4: 391 return (db_regs->tf_r4); 392 case 5: 393 return (db_regs->tf_r5); 394 case 6: 395 return (db_regs->tf_r6); 396 case 7: 397 return (db_regs->tf_r7); 398 case 8: 399 return (db_regs->tf_r8); 400 case 9: 401 return (db_regs->tf_r9); 402 case 10: 403 return (db_regs->tf_r10); 404 case 11: 405 return (db_regs->tf_r11); 406 case 12: 407 return (db_regs->tf_r12); 408 case 13: 409 return (db_regs->tf_svc_sp); 410 case 14: 411 return (db_regs->tf_svc_lr); 412 case 15: 413 return (db_regs->tf_pc); 414 default: 415 panic("db_fetch_reg: botch"); 416 } 417 } 418 419 u_int 420 branch_taken(u_int insn, u_int pc, db_regs_t *db_regs) 421 { 422 u_int addr, nregs; 423 424 switch ((insn >> 24) & 0xf) { 425 case 0xa: /* b ... */ 426 case 0xb: /* bl ... */ 427 addr = ((insn << 2) & 0x03ffffff); 428 if (addr & 0x02000000) 429 addr |= 0xfc000000; 430 return (pc + 8 + addr); 431 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 432 addr = db_fetch_reg(insn & 0xf, db_regs); 433 addr = pc + 8 + (addr << 2); 434 db_read_bytes(addr, 4, (char *)&addr); 435 return (addr); 436 case 0x1: /* mov pc, reg */ 437 addr = db_fetch_reg(insn & 0xf, db_regs); 438 return (addr); 439 case 0x8: /* ldmxx reg, {..., pc} */ 440 case 0x9: 441 addr = db_fetch_reg((insn >> 16) & 0xf, db_regs); 442 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 443 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 444 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 445 nregs = (nregs + (nregs >> 8)) & 0x001f; 446 switch ((insn >> 23) & 0x3) { 447 case 0x0: /* ldmda */ 448 addr = addr - 0; 449 break; 450 case 0x1: /* ldmia */ 451 addr = addr + 0 + ((nregs - 1) << 2); 452 break; 453 case 0x2: /* ldmdb */ 454 addr = addr - 4; 455 break; 456 case 0x3: /* ldmib */ 457 addr = addr + 4 + ((nregs - 1) << 2); 458 break; 459 } 460 db_read_bytes(addr, 4, (char *)&addr); 461 return (addr); 462 default: 463 panic("branch_taken: botch"); 464 } 465 } 466
Indexes created Tue Sep 30 11:09:46 GMT 2025