db_interface.c revision 1.23
1 /* $NetBSD: db_interface.c,v 1.23 2003/04/18 11:08:25 scw Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 #include "opt_ddb.h" 37 38 #include <sys/param.h> 39 #include <sys/proc.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> /* just for boothowto */ 42 #include <sys/exec.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <arm/arm32/db_machdep.h> 47 #include <arm/arm32/katelib.h> 48 #include <arm/undefined.h> 49 #include <ddb/db_access.h> 50 #include <ddb/db_command.h> 51 #include <ddb/db_output.h> 52 #include <ddb/db_variables.h> 53 #include <ddb/db_sym.h> 54 #include <ddb/db_extern.h> 55 #include <ddb/db_interface.h> 56 #include <dev/cons.h> 57 58 static int nil; 59 60 int db_access_und_sp __P((const struct db_variable *, db_expr_t *, int)); 61 int db_access_abt_sp __P((const struct db_variable *, db_expr_t *, int)); 62 int db_access_irq_sp __P((const struct db_variable *, db_expr_t *, int)); 63 u_int db_fetch_reg __P((int, db_regs_t *)); 64 65 int db_trapper __P((u_int, u_int, trapframe_t *, int)); 66 67 const struct db_variable db_regs[] = { 68 { "spsr", (long *)&DDB_REGS->tf_spsr, FCN_NULL, }, 69 { "r0", (long *)&DDB_REGS->tf_r0, FCN_NULL, }, 70 { "r1", (long *)&DDB_REGS->tf_r1, FCN_NULL, }, 71 { "r2", (long *)&DDB_REGS->tf_r2, FCN_NULL, }, 72 { "r3", (long *)&DDB_REGS->tf_r3, FCN_NULL, }, 73 { "r4", (long *)&DDB_REGS->tf_r4, FCN_NULL, }, 74 { "r5", (long *)&DDB_REGS->tf_r5, FCN_NULL, }, 75 { "r6", (long *)&DDB_REGS->tf_r6, FCN_NULL, }, 76 { "r7", (long *)&DDB_REGS->tf_r7, FCN_NULL, }, 77 { "r8", (long *)&DDB_REGS->tf_r8, FCN_NULL, }, 78 { "r9", (long *)&DDB_REGS->tf_r9, FCN_NULL, }, 79 { "r10", (long *)&DDB_REGS->tf_r10, FCN_NULL, }, 80 { "r11", (long *)&DDB_REGS->tf_r11, FCN_NULL, }, 81 { "r12", (long *)&DDB_REGS->tf_r12, FCN_NULL, }, 82 { "usr_sp", (long *)&DDB_REGS->tf_usr_sp, FCN_NULL, }, 83 { "usr_lr", (long *)&DDB_REGS->tf_usr_lr, FCN_NULL, }, 84 { "svc_sp", (long *)&DDB_REGS->tf_svc_sp, FCN_NULL, }, 85 { "svc_lr", (long *)&DDB_REGS->tf_svc_lr, FCN_NULL, }, 86 { "pc", (long *)&DDB_REGS->tf_pc, FCN_NULL, }, 87 { "und_sp", (long *)&nil, db_access_und_sp, }, 88 { "abt_sp", (long *)&nil, db_access_abt_sp, }, 89 { "irq_sp", (long *)&nil, db_access_irq_sp, }, 90 }; 91 92 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 93 94 int db_active = 0; 95 96 int 97 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 98 { 99 100 if (rw == DB_VAR_GET) 101 *valp = get_stackptr(PSR_UND32_MODE); 102 return(0); 103 } 104 105 int 106 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 107 { 108 109 if (rw == DB_VAR_GET) 110 *valp = get_stackptr(PSR_ABT32_MODE); 111 return(0); 112 } 113 114 int 115 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 116 { 117 118 if (rw == DB_VAR_GET) 119 *valp = get_stackptr(PSR_IRQ32_MODE); 120 return(0); 121 } 122 123 /* 124 * kdb_trap - field a TRACE or BPT trap 125 */ 126 int 127 kdb_trap(int type, db_regs_t *regs) 128 { 129 int s; 130 131 switch (type) { 132 case T_BREAKPOINT: /* breakpoint */ 133 case -1: /* keyboard interrupt */ 134 break; 135 default: 136 db_printf("kernel: trap"); 137 if (db_recover != 0) { 138 db_error("Faulted in DDB; continuing...\n"); 139 /*NOTREACHED*/ 140 } 141 } 142 143 /* Should switch to kdb`s own stack here. */ 144 145 ddb_regs = *regs; 146 147 s = splhigh(); 148 db_active++; 149 cnpollc(TRUE); 150 db_trap(type, 0/*code*/); 151 cnpollc(FALSE); 152 db_active--; 153 splx(s); 154 155 *regs = ddb_regs; 156 157 return (1); 158 } 159 160 161 static int 162 db_validate_address(vaddr_t addr) 163 { 164 struct proc *p = curproc; 165 struct pmap *pmap; 166 167 #ifndef ARM32_PMAP_NEW 168 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap) 169 #else 170 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 171 #ifndef ARM32_NEW_VM_LAYOUT 172 addr >= VM_MAXUSER_ADDRESS) 173 #else 174 addr >= VM_MIN_KERNEL_ADDRESS) 175 #endif 176 #endif 177 pmap = pmap_kernel(); 178 else 179 pmap = p->p_vmspace->vm_map.pmap; 180 181 return (pmap_extract(pmap, addr, NULL) == FALSE); 182 } 183 184 /* 185 * Read bytes from kernel address space for debugger. 186 */ 187 void 188 db_read_bytes(addr, size, data) 189 vaddr_t addr; 190 size_t size; 191 char *data; 192 { 193 char *src; 194 195 src = (char *)addr; 196 197 while (size-- > 0) { 198 if (db_validate_address((u_int)src)) { 199 db_printf("address %p is invalid\n", src); 200 return; 201 } 202 *data++ = *src++; 203 } 204 } 205 206 static void 207 db_write_text(vaddr_t addr, size_t size, char *data) 208 { 209 struct pmap *pmap = pmap_kernel(); 210 pd_entry_t *pde, oldpde, tmppde; 211 pt_entry_t *pte, oldpte, tmppte; 212 vaddr_t pgva; 213 size_t limit, savesize; 214 char *dst; 215 216 if ((savesize = size) == 0) 217 return; 218 219 dst = (char *) addr; 220 221 do { 222 /* Get the PDE of the current VA. */ 223 #ifndef ARM32_PMAP_NEW 224 pde = pmap_pde(pmap, (vaddr_t) dst); 225 #else 226 if (pmap_get_pde_pte(pmap, (vaddr_t) dst, &pde, &pte) == FALSE) 227 goto no_mapping; 228 #endif 229 switch ((oldpde = *pde) & L1_TYPE_MASK) { 230 case L1_TYPE_S: 231 pgva = (vaddr_t)dst & L1_S_FRAME; 232 limit = L1_S_SIZE - ((vaddr_t)dst & L1_S_OFFSET); 233 234 tmppde = oldpde | L1_S_PROT_W; 235 *pde = tmppde; 236 PTE_SYNC(pde); 237 break; 238 239 case L1_TYPE_C: 240 pgva = (vaddr_t)dst & L2_S_FRAME; 241 limit = L2_S_SIZE - ((vaddr_t)dst & L2_S_OFFSET); 242 243 #ifndef ARM32_PMAP_NEW 244 pte = vtopte(pgva); 245 #else 246 if (pte == NULL) 247 goto no_mapping; 248 #endif 249 oldpte = *pte; 250 tmppte = oldpte | L2_S_PROT_W; 251 *pte = tmppte; 252 PTE_SYNC(pte); 253 break; 254 255 default: 256 #ifdef ARM32_PMAP_NEW 257 no_mapping: 258 #endif 259 printf(" address 0x%08lx not a valid page\n", 260 (vaddr_t) dst); 261 return; 262 } 263 cpu_tlb_flushD_SE(pgva); 264 cpu_cpwait(); 265 266 if (limit > size) 267 limit = size; 268 size -= limit; 269 270 /* 271 * Page is now writable. Do as much access as we 272 * can in this page. 273 */ 274 for (; limit > 0; limit--) 275 *dst++ = *data++; 276 277 /* 278 * Restore old mapping permissions. 279 */ 280 switch (oldpde & L1_TYPE_MASK) { 281 case L1_TYPE_S: 282 *pde = oldpde; 283 PTE_SYNC(pde); 284 break; 285 286 case L1_TYPE_C: 287 *pte = oldpte; 288 PTE_SYNC(pte); 289 break; 290 } 291 cpu_tlb_flushD_SE(pgva); 292 cpu_cpwait(); 293 } while (size != 0); 294 295 /* Sync the I-cache. */ 296 cpu_icache_sync_range(addr, savesize); 297 } 298 299 /* 300 * Write bytes to kernel address space for debugger. 301 */ 302 void 303 db_write_bytes(vaddr_t addr, size_t size, char *data) 304 { 305 extern char etext[]; 306 char *dst; 307 size_t loop; 308 309 /* If any part is in kernel text, use db_write_text() */ 310 if (addr >= KERNEL_TEXT_BASE && addr < (vaddr_t) etext) { 311 db_write_text(addr, size, data); 312 return; 313 } 314 315 dst = (char *)addr; 316 loop = size; 317 while (loop-- > 0) { 318 if (db_validate_address((u_int)dst)) { 319 db_printf("address %p is invalid\n", dst); 320 return; 321 } 322 *dst++ = *data++; 323 } 324 /* make sure the caches and memory are in sync */ 325 cpu_icache_sync_range(addr, size); 326 327 /* In case the current page tables have been modified ... */ 328 cpu_tlb_flushID(); 329 cpu_cpwait(); 330 } 331 332 void 333 cpu_Debugger(void) 334 { 335 asm(".word 0xe7ffffff"); 336 } 337 338 const struct db_command db_machine_command_table[] = { 339 { "frame", db_show_frame_cmd, 0, NULL }, 340 { "panic", db_show_panic_cmd, 0, NULL }, 341 #ifdef ARM32_DB_COMMANDS 342 ARM32_DB_COMMANDS, 343 #endif 344 { NULL, NULL, 0, NULL } 345 }; 346 347 int 348 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 349 { 350 351 if (fault_code == 0) { 352 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 353 kdb_trap(T_BREAKPOINT, frame); 354 else 355 kdb_trap(-1, frame); 356 } else 357 return (1); 358 return (0); 359 } 360 361 extern u_int esym; 362 extern u_int end; 363 364 static struct undefined_handler db_uh; 365 366 void 367 db_machine_init(void) 368 { 369 #ifndef __ELF__ 370 struct exec *kernexec = (struct exec *)KERNEL_TEXT_BASE; 371 int len; 372 373 /* 374 * The boot loader currently loads the kernel with the a.out 375 * header still attached. 376 */ 377 378 if (kernexec->a_syms == 0) { 379 printf("ddb: No symbol table\n"); 380 } else { 381 /* cover the symbols themselves (what is the int for?? XXX) */ 382 esym = (int)&end + kernexec->a_syms + sizeof(int); 383 384 /* 385 * and the string table. (int containing size of string 386 * table is included in string table size). 387 */ 388 len = *((u_int *)esym); 389 esym += (len + (sizeof(u_int) - 1)) & ~(sizeof(u_int) - 1); 390 } 391 #endif 392 393 /* 394 * We get called before malloc() is available, so supply a static 395 * struct undefined_handler. 396 */ 397 db_uh.uh_handler = db_trapper; 398 install_coproc_handler_static(0, &db_uh); 399 } 400 401 u_int 402 db_fetch_reg(int reg, db_regs_t *db_regs) 403 { 404 405 switch (reg) { 406 case 0: 407 return (db_regs->tf_r0); 408 case 1: 409 return (db_regs->tf_r1); 410 case 2: 411 return (db_regs->tf_r2); 412 case 3: 413 return (db_regs->tf_r3); 414 case 4: 415 return (db_regs->tf_r4); 416 case 5: 417 return (db_regs->tf_r5); 418 case 6: 419 return (db_regs->tf_r6); 420 case 7: 421 return (db_regs->tf_r7); 422 case 8: 423 return (db_regs->tf_r8); 424 case 9: 425 return (db_regs->tf_r9); 426 case 10: 427 return (db_regs->tf_r10); 428 case 11: 429 return (db_regs->tf_r11); 430 case 12: 431 return (db_regs->tf_r12); 432 case 13: 433 return (db_regs->tf_svc_sp); 434 case 14: 435 return (db_regs->tf_svc_lr); 436 case 15: 437 return (db_regs->tf_pc); 438 default: 439 panic("db_fetch_reg: botch"); 440 } 441 } 442 443 u_int 444 branch_taken(u_int insn, u_int pc, db_regs_t *db_regs) 445 { 446 u_int addr, nregs; 447 448 switch ((insn >> 24) & 0xf) { 449 case 0xa: /* b ... */ 450 case 0xb: /* bl ... */ 451 addr = ((insn << 2) & 0x03ffffff); 452 if (addr & 0x02000000) 453 addr |= 0xfc000000; 454 return (pc + 8 + addr); 455 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 456 addr = db_fetch_reg(insn & 0xf, db_regs); 457 addr = pc + 8 + (addr << 2); 458 db_read_bytes(addr, 4, (char *)&addr); 459 return (addr); 460 case 0x1: /* mov pc, reg */ 461 addr = db_fetch_reg(insn & 0xf, db_regs); 462 return (addr); 463 case 0x8: /* ldmxx reg, {..., pc} */ 464 case 0x9: 465 addr = db_fetch_reg((insn >> 16) & 0xf, db_regs); 466 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 467 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 468 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 469 nregs = (nregs + (nregs >> 8)) & 0x001f; 470 switch ((insn >> 23) & 0x3) { 471 case 0x0: /* ldmda */ 472 addr = addr - 0; 473 break; 474 case 0x1: /* ldmia */ 475 addr = addr + 0 + ((nregs - 1) << 2); 476 break; 477 case 0x2: /* ldmdb */ 478 addr = addr - 4; 479 break; 480 case 0x3: /* ldmib */ 481 addr = addr + 4 + ((nregs - 1) << 2); 482 break; 483 } 484 db_read_bytes(addr, 4, (char *)&addr); 485 return (addr); 486 default: 487 panic("branch_taken: botch"); 488 } 489 } 490
Indexes created Mon Sep 29 21:09:56 GMT 2025