db_interface.c revision 1.30
1 /* $NetBSD: db_interface.c,v 1.30 2003/06/06 10:07:07 scw Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 #include "opt_ddb.h" 37 #include "opt_kgdb.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/reboot.h> 42 #include <sys/systm.h> /* just for boothowto */ 43 #include <sys/exec.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <arm/arm32/db_machdep.h> 48 #include <arm/arm32/katelib.h> 49 #include <arm/undefined.h> 50 #include <ddb/db_access.h> 51 #include <ddb/db_command.h> 52 #include <ddb/db_output.h> 53 #include <ddb/db_variables.h> 54 #include <ddb/db_sym.h> 55 #include <ddb/db_extern.h> 56 #include <ddb/db_interface.h> 57 #include <dev/cons.h> 58 59 #if defined(KGDB) || !defined(DDB) 60 #define db_printf printf 61 #endif 62 63 static int nil; 64 65 int db_access_und_sp __P((const struct db_variable *, db_expr_t *, int)); 66 int db_access_abt_sp __P((const struct db_variable *, db_expr_t *, int)); 67 int db_access_irq_sp __P((const struct db_variable *, db_expr_t *, int)); 68 u_int db_fetch_reg __P((int, db_regs_t *)); 69 70 int db_trapper __P((u_int, u_int, trapframe_t *, int)); 71 72 const struct db_variable db_regs[] = { 73 { "spsr", (long *)&DDB_REGS->tf_spsr, FCN_NULL, }, 74 { "r0", (long *)&DDB_REGS->tf_r0, FCN_NULL, }, 75 { "r1", (long *)&DDB_REGS->tf_r1, FCN_NULL, }, 76 { "r2", (long *)&DDB_REGS->tf_r2, FCN_NULL, }, 77 { "r3", (long *)&DDB_REGS->tf_r3, FCN_NULL, }, 78 { "r4", (long *)&DDB_REGS->tf_r4, FCN_NULL, }, 79 { "r5", (long *)&DDB_REGS->tf_r5, FCN_NULL, }, 80 { "r6", (long *)&DDB_REGS->tf_r6, FCN_NULL, }, 81 { "r7", (long *)&DDB_REGS->tf_r7, FCN_NULL, }, 82 { "r8", (long *)&DDB_REGS->tf_r8, FCN_NULL, }, 83 { "r9", (long *)&DDB_REGS->tf_r9, FCN_NULL, }, 84 { "r10", (long *)&DDB_REGS->tf_r10, FCN_NULL, }, 85 { "r11", (long *)&DDB_REGS->tf_r11, FCN_NULL, }, 86 { "r12", (long *)&DDB_REGS->tf_r12, FCN_NULL, }, 87 { "usr_sp", (long *)&DDB_REGS->tf_usr_sp, FCN_NULL, }, 88 { "usr_lr", (long *)&DDB_REGS->tf_usr_lr, FCN_NULL, }, 89 { "svc_sp", (long *)&DDB_REGS->tf_svc_sp, FCN_NULL, }, 90 { "svc_lr", (long *)&DDB_REGS->tf_svc_lr, FCN_NULL, }, 91 { "pc", (long *)&DDB_REGS->tf_pc, FCN_NULL, }, 92 { "und_sp", (long *)&nil, db_access_und_sp, }, 93 { "abt_sp", (long *)&nil, db_access_abt_sp, }, 94 { "irq_sp", (long *)&nil, db_access_irq_sp, }, 95 }; 96 97 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 98 99 int db_active = 0; 100 101 int 102 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 103 { 104 105 if (rw == DB_VAR_GET) 106 *valp = get_stackptr(PSR_UND32_MODE); 107 return(0); 108 } 109 110 int 111 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 112 { 113 114 if (rw == DB_VAR_GET) 115 *valp = get_stackptr(PSR_ABT32_MODE); 116 return(0); 117 } 118 119 int 120 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 121 { 122 123 if (rw == DB_VAR_GET) 124 *valp = get_stackptr(PSR_IRQ32_MODE); 125 return(0); 126 } 127 128 #ifdef DDB 129 /* 130 * kdb_trap - field a TRACE or BPT trap 131 */ 132 int 133 kdb_trap(int type, db_regs_t *regs) 134 { 135 int s; 136 137 switch (type) { 138 case T_BREAKPOINT: /* breakpoint */ 139 case -1: /* keyboard interrupt */ 140 break; 141 default: 142 db_printf("kernel: trap"); 143 if (db_recover != 0) { 144 db_error("Faulted in DDB; continuing...\n"); 145 /*NOTREACHED*/ 146 } 147 } 148 149 /* Should switch to kdb`s own stack here. */ 150 151 ddb_regs = *regs; 152 153 s = splhigh(); 154 db_active++; 155 cnpollc(TRUE); 156 db_trap(type, 0/*code*/); 157 cnpollc(FALSE); 158 db_active--; 159 splx(s); 160 161 *regs = ddb_regs; 162 163 return (1); 164 } 165 #endif 166 167 int 168 db_validate_address(vaddr_t addr) 169 { 170 struct proc *p = curproc; 171 struct pmap *pmap; 172 173 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 174 #ifndef ARM32_NEW_VM_LAYOUT 175 addr >= VM_MAXUSER_ADDRESS 176 #else 177 addr >= VM_MIN_KERNEL_ADDRESS 178 #endif 179 ) 180 pmap = pmap_kernel(); 181 else 182 pmap = p->p_vmspace->vm_map.pmap; 183 184 return (pmap_extract(pmap, addr, NULL) == FALSE); 185 } 186 187 /* 188 * Read bytes from kernel address space for debugger. 189 */ 190 void 191 db_read_bytes(addr, size, data) 192 vaddr_t addr; 193 size_t size; 194 char *data; 195 { 196 char *src = (char *)addr; 197 198 if (db_validate_address((u_int)src)) { 199 db_printf("address %p is invalid\n", src); 200 return; 201 } 202 203 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 204 *((int*)data) = *((int*)src); 205 return; 206 } 207 208 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 209 *((short*)data) = *((short*)src); 210 return; 211 } 212 213 while (size-- > 0) { 214 if (db_validate_address((u_int)src)) { 215 db_printf("address %p is invalid\n", src); 216 return; 217 } 218 *data++ = *src++; 219 } 220 } 221 222 static void 223 db_write_text(vaddr_t addr, size_t size, char *data) 224 { 225 struct pmap *pmap = pmap_kernel(); 226 pd_entry_t *pde, oldpde, tmppde; 227 pt_entry_t *pte, oldpte, tmppte; 228 vaddr_t pgva; 229 size_t limit, savesize; 230 char *dst; 231 232 if ((savesize = size) == 0) 233 return; 234 235 dst = (char *) addr; 236 237 do { 238 /* Get the PDE of the current VA. */ 239 if (pmap_get_pde_pte(pmap, (vaddr_t) dst, &pde, &pte) == FALSE) 240 goto no_mapping; 241 switch ((oldpde = *pde) & L1_TYPE_MASK) { 242 case L1_TYPE_S: 243 pgva = (vaddr_t)dst & L1_S_FRAME; 244 limit = L1_S_SIZE - ((vaddr_t)dst & L1_S_OFFSET); 245 246 tmppde = oldpde | L1_S_PROT_W; 247 *pde = tmppde; 248 PTE_SYNC(pde); 249 break; 250 251 case L1_TYPE_C: 252 pgva = (vaddr_t)dst & L2_S_FRAME; 253 limit = L2_S_SIZE - ((vaddr_t)dst & L2_S_OFFSET); 254 255 if (pte == NULL) 256 goto no_mapping; 257 oldpte = *pte; 258 tmppte = oldpte | L2_S_PROT_W; 259 *pte = tmppte; 260 PTE_SYNC(pte); 261 break; 262 263 default: 264 no_mapping: 265 printf(" address 0x%08lx not a valid page\n", 266 (vaddr_t) dst); 267 return; 268 } 269 cpu_tlb_flushD_SE(pgva); 270 cpu_cpwait(); 271 272 if (limit > size) 273 limit = size; 274 size -= limit; 275 276 /* 277 * Page is now writable. Do as much access as we 278 * can in this page. 279 */ 280 for (; limit > 0; limit--) 281 *dst++ = *data++; 282 283 /* 284 * Restore old mapping permissions. 285 */ 286 switch (oldpde & L1_TYPE_MASK) { 287 case L1_TYPE_S: 288 *pde = oldpde; 289 PTE_SYNC(pde); 290 break; 291 292 case L1_TYPE_C: 293 *pte = oldpte; 294 PTE_SYNC(pte); 295 break; 296 } 297 cpu_tlb_flushD_SE(pgva); 298 cpu_cpwait(); 299 } while (size != 0); 300 301 /* Sync the I-cache. */ 302 cpu_icache_sync_range(addr, savesize); 303 } 304 305 /* 306 * Write bytes to kernel address space for debugger. 307 */ 308 void 309 db_write_bytes(vaddr_t addr, size_t size, char *data) 310 { 311 extern char kernel_text[]; 312 extern char etext[]; 313 char *dst; 314 size_t loop; 315 316 /* If any part is in kernel text, use db_write_text() */ 317 if (addr >= (vaddr_t) kernel_text && addr < (vaddr_t) etext) { 318 db_write_text(addr, size, data); 319 return; 320 } 321 322 dst = (char *)addr; 323 if (db_validate_address((u_int)dst)) { 324 db_printf("address %p is invalid\n", dst); 325 return; 326 } 327 328 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 329 *((int*)dst) = *((int*)data); 330 else 331 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 332 *((short*)dst) = *((short*)data); 333 else { 334 loop = size; 335 while (loop-- > 0) { 336 if (db_validate_address((u_int)dst)) { 337 db_printf("address %p is invalid\n", dst); 338 return; 339 } 340 *dst++ = *data++; 341 } 342 } 343 344 /* make sure the caches and memory are in sync */ 345 cpu_icache_sync_range(addr, size); 346 347 /* In case the current page tables have been modified ... */ 348 cpu_tlb_flushID(); 349 cpu_cpwait(); 350 } 351 352 #ifdef DDB 353 void 354 cpu_Debugger(void) 355 { 356 asm(".word 0xe7ffffff"); 357 } 358 359 const struct db_command db_machine_command_table[] = { 360 { "frame", db_show_frame_cmd, 0, NULL }, 361 { "panic", db_show_panic_cmd, 0, NULL }, 362 #ifdef ARM32_DB_COMMANDS 363 ARM32_DB_COMMANDS, 364 #endif 365 { NULL, NULL, 0, NULL } 366 }; 367 368 int 369 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 370 { 371 372 if (fault_code == 0) { 373 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 374 kdb_trap(T_BREAKPOINT, frame); 375 else 376 kdb_trap(-1, frame); 377 } else 378 return (1); 379 return (0); 380 } 381 382 extern u_int esym; 383 extern u_int end; 384 385 static struct undefined_handler db_uh; 386 387 void 388 db_machine_init(void) 389 { 390 391 /* 392 * We get called before malloc() is available, so supply a static 393 * struct undefined_handler. 394 */ 395 db_uh.uh_handler = db_trapper; 396 install_coproc_handler_static(0, &db_uh); 397 } 398 #endif 399 400 u_int 401 db_fetch_reg(int reg, db_regs_t *db_regs) 402 { 403 404 switch (reg) { 405 case 0: 406 return (db_regs->tf_r0); 407 case 1: 408 return (db_regs->tf_r1); 409 case 2: 410 return (db_regs->tf_r2); 411 case 3: 412 return (db_regs->tf_r3); 413 case 4: 414 return (db_regs->tf_r4); 415 case 5: 416 return (db_regs->tf_r5); 417 case 6: 418 return (db_regs->tf_r6); 419 case 7: 420 return (db_regs->tf_r7); 421 case 8: 422 return (db_regs->tf_r8); 423 case 9: 424 return (db_regs->tf_r9); 425 case 10: 426 return (db_regs->tf_r10); 427 case 11: 428 return (db_regs->tf_r11); 429 case 12: 430 return (db_regs->tf_r12); 431 case 13: 432 return (db_regs->tf_svc_sp); 433 case 14: 434 return (db_regs->tf_svc_lr); 435 case 15: 436 return (db_regs->tf_pc); 437 default: 438 panic("db_fetch_reg: botch"); 439 } 440 } 441 442 u_int 443 branch_taken(u_int insn, u_int pc, db_regs_t *db_regs) 444 { 445 u_int addr, nregs; 446 447 switch ((insn >> 24) & 0xf) { 448 case 0xa: /* b ... */ 449 case 0xb: /* bl ... */ 450 addr = ((insn << 2) & 0x03ffffff); 451 if (addr & 0x02000000) 452 addr |= 0xfc000000; 453 return (pc + 8 + addr); 454 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 455 addr = db_fetch_reg(insn & 0xf, db_regs); 456 addr = pc + 8 + (addr << 2); 457 db_read_bytes(addr, 4, (char *)&addr); 458 return (addr); 459 case 0x1: /* mov pc, reg */ 460 addr = db_fetch_reg(insn & 0xf, db_regs); 461 return (addr); 462 case 0x8: /* ldmxx reg, {..., pc} */ 463 case 0x9: 464 addr = db_fetch_reg((insn >> 16) & 0xf, db_regs); 465 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 466 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 467 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 468 nregs = (nregs + (nregs >> 8)) & 0x001f; 469 switch ((insn >> 23) & 0x3) { 470 case 0x0: /* ldmda */ 471 addr = addr - 0; 472 break; 473 case 0x1: /* ldmia */ 474 addr = addr + 0 + ((nregs - 1) << 2); 475 break; 476 case 0x2: /* ldmdb */ 477 addr = addr - 4; 478 break; 479 case 0x3: /* ldmib */ 480 addr = addr + 4 + ((nregs - 1) << 2); 481 break; 482 } 483 db_read_bytes(addr, 4, (char *)&addr); 484 return (addr); 485 default: 486 panic("branch_taken: botch"); 487 } 488 } 489
Indexes created Tue Sep 30 11:09:46 GMT 2025