db_interface.c revision 1.32
1 /* $NetBSD: db_interface.c,v 1.32 2003/07/15 00:24:41 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.32 2003/07/15 00:24:41 lukem Exp $"); 39 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 43 #include <sys/param.h> 44 #include <sys/proc.h> 45 #include <sys/reboot.h> 46 #include <sys/systm.h> /* just for boothowto */ 47 #include <sys/exec.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <arm/arm32/db_machdep.h> 52 #include <arm/arm32/katelib.h> 53 #include <arm/undefined.h> 54 #include <ddb/db_access.h> 55 #include <ddb/db_command.h> 56 #include <ddb/db_output.h> 57 #include <ddb/db_variables.h> 58 #include <ddb/db_sym.h> 59 #include <ddb/db_extern.h> 60 #include <ddb/db_interface.h> 61 #include <dev/cons.h> 62 63 #if defined(KGDB) || !defined(DDB) 64 #define db_printf printf 65 #endif 66 67 static int nil; 68 69 int db_access_und_sp __P((const struct db_variable *, db_expr_t *, int)); 70 int db_access_abt_sp __P((const struct db_variable *, db_expr_t *, int)); 71 int db_access_irq_sp __P((const struct db_variable *, db_expr_t *, int)); 72 u_int db_fetch_reg __P((int, db_regs_t *)); 73 74 int db_trapper __P((u_int, u_int, trapframe_t *, int)); 75 76 const struct db_variable db_regs[] = { 77 { "spsr", (long *)&DDB_REGS->tf_spsr, FCN_NULL, }, 78 { "r0", (long *)&DDB_REGS->tf_r0, FCN_NULL, }, 79 { "r1", (long *)&DDB_REGS->tf_r1, FCN_NULL, }, 80 { "r2", (long *)&DDB_REGS->tf_r2, FCN_NULL, }, 81 { "r3", (long *)&DDB_REGS->tf_r3, FCN_NULL, }, 82 { "r4", (long *)&DDB_REGS->tf_r4, FCN_NULL, }, 83 { "r5", (long *)&DDB_REGS->tf_r5, FCN_NULL, }, 84 { "r6", (long *)&DDB_REGS->tf_r6, FCN_NULL, }, 85 { "r7", (long *)&DDB_REGS->tf_r7, FCN_NULL, }, 86 { "r8", (long *)&DDB_REGS->tf_r8, FCN_NULL, }, 87 { "r9", (long *)&DDB_REGS->tf_r9, FCN_NULL, }, 88 { "r10", (long *)&DDB_REGS->tf_r10, FCN_NULL, }, 89 { "r11", (long *)&DDB_REGS->tf_r11, FCN_NULL, }, 90 { "r12", (long *)&DDB_REGS->tf_r12, FCN_NULL, }, 91 { "usr_sp", (long *)&DDB_REGS->tf_usr_sp, FCN_NULL, }, 92 { "usr_lr", (long *)&DDB_REGS->tf_usr_lr, FCN_NULL, }, 93 { "svc_sp", (long *)&DDB_REGS->tf_svc_sp, FCN_NULL, }, 94 { "svc_lr", (long *)&DDB_REGS->tf_svc_lr, FCN_NULL, }, 95 { "pc", (long *)&DDB_REGS->tf_pc, FCN_NULL, }, 96 { "und_sp", (long *)&nil, db_access_und_sp, }, 97 { "abt_sp", (long *)&nil, db_access_abt_sp, }, 98 { "irq_sp", (long *)&nil, db_access_irq_sp, }, 99 }; 100 101 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 102 103 int db_active = 0; 104 105 int 106 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 107 { 108 109 if (rw == DB_VAR_GET) 110 *valp = get_stackptr(PSR_UND32_MODE); 111 return(0); 112 } 113 114 int 115 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 116 { 117 118 if (rw == DB_VAR_GET) 119 *valp = get_stackptr(PSR_ABT32_MODE); 120 return(0); 121 } 122 123 int 124 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 125 { 126 127 if (rw == DB_VAR_GET) 128 *valp = get_stackptr(PSR_IRQ32_MODE); 129 return(0); 130 } 131 132 #ifdef DDB 133 /* 134 * kdb_trap - field a TRACE or BPT trap 135 */ 136 int 137 kdb_trap(int type, db_regs_t *regs) 138 { 139 int s; 140 141 switch (type) { 142 case T_BREAKPOINT: /* breakpoint */ 143 case -1: /* keyboard interrupt */ 144 break; 145 default: 146 if (db_recover != 0) { 147 /* This will longjmp back into db_command_loop() */ 148 db_error("Faulted in DDB; continuing...\n"); 149 /*NOTREACHED*/ 150 } 151 } 152 153 /* Should switch to kdb`s own stack here. */ 154 155 ddb_regs = *regs; 156 157 s = splhigh(); 158 db_active++; 159 cnpollc(TRUE); 160 db_trap(type, 0/*code*/); 161 cnpollc(FALSE); 162 db_active--; 163 splx(s); 164 165 *regs = ddb_regs; 166 167 return (1); 168 } 169 #endif 170 171 int 172 db_validate_address(vaddr_t addr) 173 { 174 struct proc *p = curproc; 175 struct pmap *pmap; 176 177 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 178 #ifndef ARM32_NEW_VM_LAYOUT 179 addr >= VM_MAXUSER_ADDRESS 180 #else 181 addr >= VM_MIN_KERNEL_ADDRESS 182 #endif 183 ) 184 pmap = pmap_kernel(); 185 else 186 pmap = p->p_vmspace->vm_map.pmap; 187 188 return (pmap_extract(pmap, addr, NULL) == FALSE); 189 } 190 191 /* 192 * Read bytes from kernel address space for debugger. 193 */ 194 void 195 db_read_bytes(addr, size, data) 196 vaddr_t addr; 197 size_t size; 198 char *data; 199 { 200 char *src = (char *)addr; 201 202 if (db_validate_address((u_int)src)) { 203 db_printf("address %p is invalid\n", src); 204 return; 205 } 206 207 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 208 *((int*)data) = *((int*)src); 209 return; 210 } 211 212 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 213 *((short*)data) = *((short*)src); 214 return; 215 } 216 217 while (size-- > 0) { 218 if (db_validate_address((u_int)src)) { 219 db_printf("address %p is invalid\n", src); 220 return; 221 } 222 *data++ = *src++; 223 } 224 } 225 226 static void 227 db_write_text(vaddr_t addr, size_t size, char *data) 228 { 229 struct pmap *pmap = pmap_kernel(); 230 pd_entry_t *pde, oldpde, tmppde; 231 pt_entry_t *pte, oldpte, tmppte; 232 vaddr_t pgva; 233 size_t limit, savesize; 234 char *dst; 235 236 if ((savesize = size) == 0) 237 return; 238 239 dst = (char *) addr; 240 241 do { 242 /* Get the PDE of the current VA. */ 243 if (pmap_get_pde_pte(pmap, (vaddr_t) dst, &pde, &pte) == FALSE) 244 goto no_mapping; 245 switch ((oldpde = *pde) & L1_TYPE_MASK) { 246 case L1_TYPE_S: 247 pgva = (vaddr_t)dst & L1_S_FRAME; 248 limit = L1_S_SIZE - ((vaddr_t)dst & L1_S_OFFSET); 249 250 tmppde = oldpde | L1_S_PROT_W; 251 *pde = tmppde; 252 PTE_SYNC(pde); 253 break; 254 255 case L1_TYPE_C: 256 pgva = (vaddr_t)dst & L2_S_FRAME; 257 limit = L2_S_SIZE - ((vaddr_t)dst & L2_S_OFFSET); 258 259 if (pte == NULL) 260 goto no_mapping; 261 oldpte = *pte; 262 tmppte = oldpte | L2_S_PROT_W; 263 *pte = tmppte; 264 PTE_SYNC(pte); 265 break; 266 267 default: 268 no_mapping: 269 printf(" address 0x%08lx not a valid page\n", 270 (vaddr_t) dst); 271 return; 272 } 273 cpu_tlb_flushD_SE(pgva); 274 cpu_cpwait(); 275 276 if (limit > size) 277 limit = size; 278 size -= limit; 279 280 /* 281 * Page is now writable. Do as much access as we 282 * can in this page. 283 */ 284 for (; limit > 0; limit--) 285 *dst++ = *data++; 286 287 /* 288 * Restore old mapping permissions. 289 */ 290 switch (oldpde & L1_TYPE_MASK) { 291 case L1_TYPE_S: 292 *pde = oldpde; 293 PTE_SYNC(pde); 294 break; 295 296 case L1_TYPE_C: 297 *pte = oldpte; 298 PTE_SYNC(pte); 299 break; 300 } 301 cpu_tlb_flushD_SE(pgva); 302 cpu_cpwait(); 303 } while (size != 0); 304 305 /* Sync the I-cache. */ 306 cpu_icache_sync_range(addr, savesize); 307 } 308 309 /* 310 * Write bytes to kernel address space for debugger. 311 */ 312 void 313 db_write_bytes(vaddr_t addr, size_t size, char *data) 314 { 315 extern char kernel_text[]; 316 extern char etext[]; 317 char *dst; 318 size_t loop; 319 320 /* If any part is in kernel text, use db_write_text() */ 321 if (addr >= (vaddr_t) kernel_text && addr < (vaddr_t) etext) { 322 db_write_text(addr, size, data); 323 return; 324 } 325 326 dst = (char *)addr; 327 if (db_validate_address((u_int)dst)) { 328 db_printf("address %p is invalid\n", dst); 329 return; 330 } 331 332 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 333 *((int*)dst) = *((int*)data); 334 else 335 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 336 *((short*)dst) = *((short*)data); 337 else { 338 loop = size; 339 while (loop-- > 0) { 340 if (db_validate_address((u_int)dst)) { 341 db_printf("address %p is invalid\n", dst); 342 return; 343 } 344 *dst++ = *data++; 345 } 346 } 347 348 /* make sure the caches and memory are in sync */ 349 cpu_icache_sync_range(addr, size); 350 351 /* In case the current page tables have been modified ... */ 352 cpu_tlb_flushID(); 353 cpu_cpwait(); 354 } 355 356 #ifdef DDB 357 void 358 cpu_Debugger(void) 359 { 360 asm(".word 0xe7ffffff"); 361 } 362 363 const struct db_command db_machine_command_table[] = { 364 { "frame", db_show_frame_cmd, 0, NULL }, 365 { "panic", db_show_panic_cmd, 0, NULL }, 366 #ifdef ARM32_DB_COMMANDS 367 ARM32_DB_COMMANDS, 368 #endif 369 { NULL, NULL, 0, NULL } 370 }; 371 372 int 373 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 374 { 375 376 if (fault_code == 0) { 377 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 378 kdb_trap(T_BREAKPOINT, frame); 379 else 380 kdb_trap(-1, frame); 381 } else 382 return (1); 383 return (0); 384 } 385 386 extern u_int esym; 387 extern u_int end; 388 389 static struct undefined_handler db_uh; 390 391 void 392 db_machine_init(void) 393 { 394 395 /* 396 * We get called before malloc() is available, so supply a static 397 * struct undefined_handler. 398 */ 399 db_uh.uh_handler = db_trapper; 400 install_coproc_handler_static(0, &db_uh); 401 } 402 #endif 403 404 u_int 405 db_fetch_reg(int reg, db_regs_t *db_regs) 406 { 407 408 switch (reg) { 409 case 0: 410 return (db_regs->tf_r0); 411 case 1: 412 return (db_regs->tf_r1); 413 case 2: 414 return (db_regs->tf_r2); 415 case 3: 416 return (db_regs->tf_r3); 417 case 4: 418 return (db_regs->tf_r4); 419 case 5: 420 return (db_regs->tf_r5); 421 case 6: 422 return (db_regs->tf_r6); 423 case 7: 424 return (db_regs->tf_r7); 425 case 8: 426 return (db_regs->tf_r8); 427 case 9: 428 return (db_regs->tf_r9); 429 case 10: 430 return (db_regs->tf_r10); 431 case 11: 432 return (db_regs->tf_r11); 433 case 12: 434 return (db_regs->tf_r12); 435 case 13: 436 return (db_regs->tf_svc_sp); 437 case 14: 438 return (db_regs->tf_svc_lr); 439 case 15: 440 return (db_regs->tf_pc); 441 default: 442 panic("db_fetch_reg: botch"); 443 } 444 } 445 446 u_int 447 branch_taken(u_int insn, u_int pc, db_regs_t *db_regs) 448 { 449 u_int addr, nregs; 450 451 switch ((insn >> 24) & 0xf) { 452 case 0xa: /* b ... */ 453 case 0xb: /* bl ... */ 454 addr = ((insn << 2) & 0x03ffffff); 455 if (addr & 0x02000000) 456 addr |= 0xfc000000; 457 return (pc + 8 + addr); 458 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 459 addr = db_fetch_reg(insn & 0xf, db_regs); 460 addr = pc + 8 + (addr << 2); 461 db_read_bytes(addr, 4, (char *)&addr); 462 return (addr); 463 case 0x1: /* mov pc, reg */ 464 addr = db_fetch_reg(insn & 0xf, db_regs); 465 return (addr); 466 case 0x8: /* ldmxx reg, {..., pc} */ 467 case 0x9: 468 addr = db_fetch_reg((insn >> 16) & 0xf, db_regs); 469 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 470 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 471 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 472 nregs = (nregs + (nregs >> 8)) & 0x001f; 473 switch ((insn >> 23) & 0x3) { 474 case 0x0: /* ldmda */ 475 addr = addr - 0; 476 break; 477 case 0x1: /* ldmia */ 478 addr = addr + 0 + ((nregs - 1) << 2); 479 break; 480 case 0x2: /* ldmdb */ 481 addr = addr - 4; 482 break; 483 case 0x3: /* ldmib */ 484 addr = addr + 4 + ((nregs - 1) << 2); 485 break; 486 } 487 db_read_bytes(addr, 4, (char *)&addr); 488 return (addr); 489 default: 490 panic("branch_taken: botch"); 491 } 492 } 493
Indexes created Mon Sep 29 21:09:56 GMT 2025