db_interface.c revision 1.37
1 /* $NetBSD: db_interface.c,v 1.37 2005/06/02 19:33:04 uwe Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.37 2005/06/02 19:33:04 uwe Exp $"); 39 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 43 #include <sys/param.h> 44 #include <sys/proc.h> 45 #include <sys/reboot.h> 46 #include <sys/systm.h> /* just for boothowto */ 47 #include <sys/exec.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <arm/arm32/db_machdep.h> 52 #include <arm/arm32/katelib.h> 53 #include <arm/undefined.h> 54 #include <ddb/db_access.h> 55 #include <ddb/db_command.h> 56 #include <ddb/db_output.h> 57 #include <ddb/db_variables.h> 58 #include <ddb/db_sym.h> 59 #include <ddb/db_extern.h> 60 #include <ddb/db_interface.h> 61 #include <dev/cons.h> 62 63 #if defined(KGDB) || !defined(DDB) 64 #define db_printf printf 65 #endif 66 67 static long nil; 68 69 int db_access_und_sp __P((const struct db_variable *, db_expr_t *, int)); 70 int db_access_abt_sp __P((const struct db_variable *, db_expr_t *, int)); 71 int db_access_irq_sp __P((const struct db_variable *, db_expr_t *, int)); 72 u_int db_fetch_reg __P((int, db_regs_t *)); 73 74 int db_trapper __P((u_int, u_int, trapframe_t *, int)); 75 76 const struct db_variable db_regs[] = { 77 { "spsr", (long *)&DDB_REGS->tf_spsr, FCN_NULL, }, 78 { "r0", (long *)&DDB_REGS->tf_r0, FCN_NULL, }, 79 { "r1", (long *)&DDB_REGS->tf_r1, FCN_NULL, }, 80 { "r2", (long *)&DDB_REGS->tf_r2, FCN_NULL, }, 81 { "r3", (long *)&DDB_REGS->tf_r3, FCN_NULL, }, 82 { "r4", (long *)&DDB_REGS->tf_r4, FCN_NULL, }, 83 { "r5", (long *)&DDB_REGS->tf_r5, FCN_NULL, }, 84 { "r6", (long *)&DDB_REGS->tf_r6, FCN_NULL, }, 85 { "r7", (long *)&DDB_REGS->tf_r7, FCN_NULL, }, 86 { "r8", (long *)&DDB_REGS->tf_r8, FCN_NULL, }, 87 { "r9", (long *)&DDB_REGS->tf_r9, FCN_NULL, }, 88 { "r10", (long *)&DDB_REGS->tf_r10, FCN_NULL, }, 89 { "r11", (long *)&DDB_REGS->tf_r11, FCN_NULL, }, 90 { "r12", (long *)&DDB_REGS->tf_r12, FCN_NULL, }, 91 { "usr_sp", (long *)&DDB_REGS->tf_usr_sp, FCN_NULL, }, 92 { "usr_lr", (long *)&DDB_REGS->tf_usr_lr, FCN_NULL, }, 93 { "svc_sp", (long *)&DDB_REGS->tf_svc_sp, FCN_NULL, }, 94 { "svc_lr", (long *)&DDB_REGS->tf_svc_lr, FCN_NULL, }, 95 { "pc", (long *)&DDB_REGS->tf_pc, FCN_NULL, }, 96 { "und_sp", &nil, db_access_und_sp, }, 97 { "abt_sp", &nil, db_access_abt_sp, }, 98 { "irq_sp", &nil, db_access_irq_sp, }, 99 }; 100 101 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 102 103 int db_active = 0; 104 105 int 106 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 107 { 108 109 if (rw == DB_VAR_GET) 110 *valp = get_stackptr(PSR_UND32_MODE); 111 return(0); 112 } 113 114 int 115 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 116 { 117 118 if (rw == DB_VAR_GET) 119 *valp = get_stackptr(PSR_ABT32_MODE); 120 return(0); 121 } 122 123 int 124 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 125 { 126 127 if (rw == DB_VAR_GET) 128 *valp = get_stackptr(PSR_IRQ32_MODE); 129 return(0); 130 } 131 132 #ifdef DDB 133 /* 134 * kdb_trap - field a TRACE or BPT trap 135 */ 136 int 137 kdb_trap(int type, db_regs_t *regs) 138 { 139 int s; 140 141 switch (type) { 142 case T_BREAKPOINT: /* breakpoint */ 143 case -1: /* keyboard interrupt */ 144 break; 145 default: 146 if (db_recover != 0) { 147 /* This will longjmp back into db_command_loop() */ 148 db_error("Faulted in DDB; continuing...\n"); 149 /*NOTREACHED*/ 150 } 151 } 152 153 /* Should switch to kdb`s own stack here. */ 154 155 ddb_regs = *regs; 156 157 s = splhigh(); 158 db_active++; 159 cnpollc(TRUE); 160 db_trap(type, 0/*code*/); 161 cnpollc(FALSE); 162 db_active--; 163 splx(s); 164 165 *regs = ddb_regs; 166 167 return (1); 168 } 169 #endif 170 171 int 172 db_validate_address(vaddr_t addr) 173 { 174 struct proc *p = curproc; 175 struct pmap *pmap; 176 177 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 178 #ifndef ARM32_NEW_VM_LAYOUT 179 addr >= VM_MAXUSER_ADDRESS 180 #else 181 addr >= VM_MIN_KERNEL_ADDRESS 182 #endif 183 ) 184 pmap = pmap_kernel(); 185 else 186 pmap = p->p_vmspace->vm_map.pmap; 187 188 return (pmap_extract(pmap, addr, NULL) == FALSE); 189 } 190 191 /* 192 * Read bytes from kernel address space for debugger. 193 */ 194 void 195 db_read_bytes(addr, size, data) 196 vaddr_t addr; 197 size_t size; 198 char *data; 199 { 200 char *src = (char *)addr; 201 202 if (db_validate_address((u_int)src)) { 203 db_printf("address %p is invalid\n", src); 204 return; 205 } 206 207 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 208 *((int*)data) = *((int*)src); 209 return; 210 } 211 212 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 213 *((short*)data) = *((short*)src); 214 return; 215 } 216 217 while (size-- > 0) { 218 if (db_validate_address((u_int)src)) { 219 db_printf("address %p is invalid\n", src); 220 return; 221 } 222 *data++ = *src++; 223 } 224 } 225 226 static void 227 db_write_text(vaddr_t addr, size_t size, const char *data) 228 { 229 struct pmap *pmap = pmap_kernel(); 230 pd_entry_t *pde, oldpde, tmppde; 231 pt_entry_t *pte, oldpte, tmppte; 232 vaddr_t pgva; 233 size_t limit, savesize; 234 char *dst; 235 236 /* XXX: gcc */ 237 oldpte = 0; 238 239 if ((savesize = size) == 0) 240 return; 241 242 dst = (char *) addr; 243 244 do { 245 /* Get the PDE of the current VA. */ 246 if (pmap_get_pde_pte(pmap, (vaddr_t) dst, &pde, &pte) == FALSE) 247 goto no_mapping; 248 switch ((oldpde = *pde) & L1_TYPE_MASK) { 249 case L1_TYPE_S: 250 pgva = (vaddr_t)dst & L1_S_FRAME; 251 limit = L1_S_SIZE - ((vaddr_t)dst & L1_S_OFFSET); 252 253 tmppde = oldpde | L1_S_PROT_W; 254 *pde = tmppde; 255 PTE_SYNC(pde); 256 break; 257 258 case L1_TYPE_C: 259 pgva = (vaddr_t)dst & L2_S_FRAME; 260 limit = L2_S_SIZE - ((vaddr_t)dst & L2_S_OFFSET); 261 262 if (pte == NULL) 263 goto no_mapping; 264 oldpte = *pte; 265 tmppte = oldpte | L2_S_PROT_W; 266 *pte = tmppte; 267 PTE_SYNC(pte); 268 break; 269 270 default: 271 no_mapping: 272 printf(" address 0x%08lx not a valid page\n", 273 (vaddr_t) dst); 274 return; 275 } 276 cpu_tlb_flushD_SE(pgva); 277 cpu_cpwait(); 278 279 if (limit > size) 280 limit = size; 281 size -= limit; 282 283 /* 284 * Page is now writable. Do as much access as we 285 * can in this page. 286 */ 287 for (; limit > 0; limit--) 288 *dst++ = *data++; 289 290 /* 291 * Restore old mapping permissions. 292 */ 293 switch (oldpde & L1_TYPE_MASK) { 294 case L1_TYPE_S: 295 *pde = oldpde; 296 PTE_SYNC(pde); 297 break; 298 299 case L1_TYPE_C: 300 *pte = oldpte; 301 PTE_SYNC(pte); 302 break; 303 } 304 cpu_tlb_flushD_SE(pgva); 305 cpu_cpwait(); 306 } while (size != 0); 307 308 /* Sync the I-cache. */ 309 cpu_icache_sync_range(addr, savesize); 310 } 311 312 /* 313 * Write bytes to kernel address space for debugger. 314 */ 315 void 316 db_write_bytes(vaddr_t addr, size_t size, const char *data) 317 { 318 extern char kernel_text[]; 319 extern char etext[]; 320 char *dst; 321 size_t loop; 322 323 /* If any part is in kernel text, use db_write_text() */ 324 if (addr >= (vaddr_t) kernel_text && addr < (vaddr_t) etext) { 325 db_write_text(addr, size, data); 326 return; 327 } 328 329 dst = (char *)addr; 330 if (db_validate_address((u_int)dst)) { 331 db_printf("address %p is invalid\n", dst); 332 return; 333 } 334 335 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 336 *((int*)dst) = *((const int *)data); 337 else 338 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 339 *((short*)dst) = *((const short *)data); 340 else { 341 loop = size; 342 while (loop-- > 0) { 343 if (db_validate_address((u_int)dst)) { 344 db_printf("address %p is invalid\n", dst); 345 return; 346 } 347 *dst++ = *data++; 348 } 349 } 350 351 /* make sure the caches and memory are in sync */ 352 cpu_icache_sync_range(addr, size); 353 354 /* In case the current page tables have been modified ... */ 355 cpu_tlb_flushID(); 356 cpu_cpwait(); 357 } 358 359 #ifdef DDB 360 void 361 cpu_Debugger(void) 362 { 363 asm(".word 0xe7ffffff"); 364 } 365 366 const struct db_command db_machine_command_table[] = { 367 { "frame", db_show_frame_cmd, 0, NULL }, 368 { "panic", db_show_panic_cmd, 0, NULL }, 369 #ifdef ARM32_DB_COMMANDS 370 ARM32_DB_COMMANDS, 371 #endif 372 { NULL, NULL, 0, NULL } 373 }; 374 375 int 376 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 377 { 378 379 if (fault_code == 0) { 380 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 381 kdb_trap(T_BREAKPOINT, frame); 382 else 383 kdb_trap(-1, frame); 384 } else 385 return (1); 386 return (0); 387 } 388 389 extern u_int esym; 390 extern u_int end; 391 392 static struct undefined_handler db_uh; 393 394 void 395 db_machine_init(void) 396 { 397 398 /* 399 * We get called before malloc() is available, so supply a static 400 * struct undefined_handler. 401 */ 402 db_uh.uh_handler = db_trapper; 403 install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &db_uh); 404 } 405 #endif 406 407 u_int 408 db_fetch_reg(int reg, db_regs_t *regs) 409 { 410 411 switch (reg) { 412 case 0: 413 return (regs->tf_r0); 414 case 1: 415 return (regs->tf_r1); 416 case 2: 417 return (regs->tf_r2); 418 case 3: 419 return (regs->tf_r3); 420 case 4: 421 return (regs->tf_r4); 422 case 5: 423 return (regs->tf_r5); 424 case 6: 425 return (regs->tf_r6); 426 case 7: 427 return (regs->tf_r7); 428 case 8: 429 return (regs->tf_r8); 430 case 9: 431 return (regs->tf_r9); 432 case 10: 433 return (regs->tf_r10); 434 case 11: 435 return (regs->tf_r11); 436 case 12: 437 return (regs->tf_r12); 438 case 13: 439 return (regs->tf_svc_sp); 440 case 14: 441 return (regs->tf_svc_lr); 442 case 15: 443 return (regs->tf_pc); 444 default: 445 panic("db_fetch_reg: botch"); 446 } 447 } 448 449 u_int 450 branch_taken(u_int insn, u_int pc, db_regs_t *regs) 451 { 452 u_int addr, nregs; 453 454 switch ((insn >> 24) & 0xf) { 455 case 0xa: /* b ... */ 456 case 0xb: /* bl ... */ 457 addr = ((insn << 2) & 0x03ffffff); 458 if (addr & 0x02000000) 459 addr |= 0xfc000000; 460 return (pc + 8 + addr); 461 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 462 addr = db_fetch_reg(insn & 0xf, regs); 463 addr = pc + 8 + (addr << 2); 464 db_read_bytes(addr, 4, (char *)&addr); 465 return (addr); 466 case 0x1: /* mov pc, reg */ 467 addr = db_fetch_reg(insn & 0xf, regs); 468 return (addr); 469 case 0x8: /* ldmxx reg, {..., pc} */ 470 case 0x9: 471 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 472 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 473 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 474 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 475 nregs = (nregs + (nregs >> 8)) & 0x001f; 476 switch ((insn >> 23) & 0x3) { 477 case 0x0: /* ldmda */ 478 addr = addr - 0; 479 break; 480 case 0x1: /* ldmia */ 481 addr = addr + 0 + ((nregs - 1) << 2); 482 break; 483 case 0x2: /* ldmdb */ 484 addr = addr - 4; 485 break; 486 case 0x3: /* ldmib */ 487 addr = addr + 4 + ((nregs - 1) << 2); 488 break; 489 } 490 db_read_bytes(addr, 4, (char *)&addr); 491 return (addr); 492 default: 493 panic("branch_taken: botch"); 494 } 495 } 496
Indexes created Tue Sep 30 07:10:03 GMT 2025