db_interface.c revision 1.46
1 /* $NetBSD: db_interface.c,v 1.46 2009/03/14 14:45:55 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.46 2009/03/14 14:45:55 dsl Exp $"); 39 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 43 #include <sys/param.h> 44 #include <sys/proc.h> 45 #include <sys/reboot.h> 46 #include <sys/systm.h> /* just for boothowto */ 47 #include <sys/exec.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <arm/arm32/db_machdep.h> 52 #include <arm/arm32/katelib.h> 53 #include <arm/undefined.h> 54 #include <ddb/db_access.h> 55 #include <ddb/db_command.h> 56 #include <ddb/db_output.h> 57 #include <ddb/db_variables.h> 58 #include <ddb/db_sym.h> 59 #include <ddb/db_extern.h> 60 #include <ddb/db_interface.h> 61 #include <dev/cons.h> 62 63 #if defined(KGDB) || !defined(DDB) 64 #define db_printf printf 65 #endif 66 67 static long nil; 68 69 int db_access_und_sp(const struct db_variable *, db_expr_t *, int); 70 int db_access_abt_sp(const struct db_variable *, db_expr_t *, int); 71 int db_access_irq_sp(const struct db_variable *, db_expr_t *, int); 72 u_int db_fetch_reg(int, db_regs_t *); 73 74 int db_trapper(u_int, u_int, trapframe_t *, int); 75 76 const struct db_variable db_regs[] = { 77 { "spsr", (long *)&DDB_REGS->tf_spsr, FCN_NULL, }, 78 { "r0", (long *)&DDB_REGS->tf_r0, FCN_NULL, }, 79 { "r1", (long *)&DDB_REGS->tf_r1, FCN_NULL, }, 80 { "r2", (long *)&DDB_REGS->tf_r2, FCN_NULL, }, 81 { "r3", (long *)&DDB_REGS->tf_r3, FCN_NULL, }, 82 { "r4", (long *)&DDB_REGS->tf_r4, FCN_NULL, }, 83 { "r5", (long *)&DDB_REGS->tf_r5, FCN_NULL, }, 84 { "r6", (long *)&DDB_REGS->tf_r6, FCN_NULL, }, 85 { "r7", (long *)&DDB_REGS->tf_r7, FCN_NULL, }, 86 { "r8", (long *)&DDB_REGS->tf_r8, FCN_NULL, }, 87 { "r9", (long *)&DDB_REGS->tf_r9, FCN_NULL, }, 88 { "r10", (long *)&DDB_REGS->tf_r10, FCN_NULL, }, 89 { "r11", (long *)&DDB_REGS->tf_r11, FCN_NULL, }, 90 { "r12", (long *)&DDB_REGS->tf_r12, FCN_NULL, }, 91 { "usr_sp", (long *)&DDB_REGS->tf_usr_sp, FCN_NULL, }, 92 { "usr_lr", (long *)&DDB_REGS->tf_usr_lr, FCN_NULL, }, 93 { "svc_sp", (long *)&DDB_REGS->tf_svc_sp, FCN_NULL, }, 94 { "svc_lr", (long *)&DDB_REGS->tf_svc_lr, FCN_NULL, }, 95 { "pc", (long *)&DDB_REGS->tf_pc, FCN_NULL, }, 96 { "und_sp", &nil, db_access_und_sp, }, 97 { "abt_sp", &nil, db_access_abt_sp, }, 98 { "irq_sp", &nil, db_access_irq_sp, }, 99 }; 100 101 const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); 102 103 int db_active = 0; 104 db_regs_t ddb_regs; /* register state */ 105 106 int 107 db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 108 { 109 110 if (rw == DB_VAR_GET) 111 *valp = get_stackptr(PSR_UND32_MODE); 112 return(0); 113 } 114 115 int 116 db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 117 { 118 119 if (rw == DB_VAR_GET) 120 *valp = get_stackptr(PSR_ABT32_MODE); 121 return(0); 122 } 123 124 int 125 db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw) 126 { 127 128 if (rw == DB_VAR_GET) 129 *valp = get_stackptr(PSR_IRQ32_MODE); 130 return(0); 131 } 132 133 #ifdef DDB 134 /* 135 * kdb_trap - field a TRACE or BPT trap 136 */ 137 int 138 kdb_trap(int type, db_regs_t *regs) 139 { 140 int s; 141 142 switch (type) { 143 case T_BREAKPOINT: /* breakpoint */ 144 case -1: /* keyboard interrupt */ 145 break; 146 default: 147 if (db_recover != 0) { 148 /* This will longjmp back into db_command_loop() */ 149 db_error("Faulted in DDB; continuing...\n"); 150 /*NOTREACHED*/ 151 } 152 } 153 154 /* Should switch to kdb`s own stack here. */ 155 156 ddb_regs = *regs; 157 158 s = splhigh(); 159 db_active++; 160 cnpollc(true); 161 db_trap(type, 0/*code*/); 162 cnpollc(false); 163 db_active--; 164 splx(s); 165 166 *regs = ddb_regs; 167 168 return (1); 169 } 170 #endif 171 172 int 173 db_validate_address(vaddr_t addr) 174 { 175 struct proc *p = curproc; 176 struct pmap *pmap; 177 178 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 179 #ifndef ARM32_NEW_VM_LAYOUT 180 addr >= VM_MAXUSER_ADDRESS 181 #else 182 addr >= VM_MIN_KERNEL_ADDRESS 183 #endif 184 ) 185 pmap = pmap_kernel(); 186 else 187 pmap = p->p_vmspace->vm_map.pmap; 188 189 return (pmap_extract(pmap, addr, NULL) == false); 190 } 191 192 /* 193 * Read bytes from kernel address space for debugger. 194 */ 195 void 196 db_read_bytes(addr, size, data) 197 vaddr_t addr; 198 size_t size; 199 char *data; 200 { 201 char *src = (char *)addr; 202 203 if (db_validate_address((u_int)src)) { 204 db_printf("address %p is invalid\n", src); 205 return; 206 } 207 208 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 209 *((int*)data) = *((int*)src); 210 return; 211 } 212 213 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 214 *((short*)data) = *((short*)src); 215 return; 216 } 217 218 while (size-- > 0) { 219 if (db_validate_address((u_int)src)) { 220 db_printf("address %p is invalid\n", src); 221 return; 222 } 223 *data++ = *src++; 224 } 225 } 226 227 static void 228 db_write_text(vaddr_t addr, size_t size, const char *data) 229 { 230 struct pmap *pmap = pmap_kernel(); 231 pd_entry_t *pde, oldpde, tmppde; 232 pt_entry_t *pte, oldpte, tmppte; 233 vaddr_t pgva; 234 size_t limit, savesize; 235 char *dst; 236 237 /* XXX: gcc */ 238 oldpte = 0; 239 240 if ((savesize = size) == 0) 241 return; 242 243 dst = (char *) addr; 244 245 do { 246 /* Get the PDE of the current VA. */ 247 if (pmap_get_pde_pte(pmap, (vaddr_t) dst, &pde, &pte) == false) 248 goto no_mapping; 249 switch ((oldpde = *pde) & L1_TYPE_MASK) { 250 case L1_TYPE_S: 251 pgva = (vaddr_t)dst & L1_S_FRAME; 252 limit = L1_S_SIZE - ((vaddr_t)dst & L1_S_OFFSET); 253 254 tmppde = oldpde | L1_S_PROT_W; 255 *pde = tmppde; 256 PTE_SYNC(pde); 257 break; 258 259 case L1_TYPE_C: 260 pgva = (vaddr_t)dst & L2_S_FRAME; 261 limit = L2_S_SIZE - ((vaddr_t)dst & L2_S_OFFSET); 262 263 if (pte == NULL) 264 goto no_mapping; 265 oldpte = *pte; 266 tmppte = oldpte | L2_S_PROT_W; 267 *pte = tmppte; 268 PTE_SYNC(pte); 269 break; 270 271 default: 272 no_mapping: 273 printf(" address 0x%08lx not a valid page\n", 274 (vaddr_t) dst); 275 return; 276 } 277 cpu_tlb_flushD_SE(pgva); 278 cpu_cpwait(); 279 280 if (limit > size) 281 limit = size; 282 size -= limit; 283 284 /* 285 * Page is now writable. Do as much access as we 286 * can in this page. 287 */ 288 for (; limit > 0; limit--) 289 *dst++ = *data++; 290 291 /* 292 * Restore old mapping permissions. 293 */ 294 switch (oldpde & L1_TYPE_MASK) { 295 case L1_TYPE_S: 296 *pde = oldpde; 297 PTE_SYNC(pde); 298 break; 299 300 case L1_TYPE_C: 301 *pte = oldpte; 302 PTE_SYNC(pte); 303 break; 304 } 305 cpu_tlb_flushD_SE(pgva); 306 cpu_cpwait(); 307 } while (size != 0); 308 309 /* Sync the I-cache. */ 310 cpu_icache_sync_range(addr, savesize); 311 } 312 313 /* 314 * Write bytes to kernel address space for debugger. 315 */ 316 void 317 db_write_bytes(vaddr_t addr, size_t size, const char *data) 318 { 319 extern char kernel_text[]; 320 extern char etext[]; 321 char *dst; 322 size_t loop; 323 324 /* If any part is in kernel text, use db_write_text() */ 325 if (addr >= (vaddr_t) kernel_text && addr < (vaddr_t) etext) { 326 db_write_text(addr, size, data); 327 return; 328 } 329 330 dst = (char *)addr; 331 if (db_validate_address((u_int)dst)) { 332 db_printf("address %p is invalid\n", dst); 333 return; 334 } 335 336 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 337 *((int*)dst) = *((const int *)data); 338 else 339 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 340 *((short*)dst) = *((const short *)data); 341 else { 342 loop = size; 343 while (loop-- > 0) { 344 if (db_validate_address((u_int)dst)) { 345 db_printf("address %p is invalid\n", dst); 346 return; 347 } 348 *dst++ = *data++; 349 } 350 } 351 352 /* make sure the caches and memory are in sync */ 353 cpu_icache_sync_range(addr, size); 354 355 /* In case the current page tables have been modified ... */ 356 cpu_tlb_flushID(); 357 cpu_cpwait(); 358 } 359 360 #ifdef DDB 361 void 362 cpu_Debugger(void) 363 { 364 __asm(".word 0xe7ffffff"); 365 } 366 367 const struct db_command db_machine_command_table[] = { 368 { DDB_ADD_CMD("frame", db_show_frame_cmd, 0, 369 "Displays the contents of a trapframe", 370 "[address]", 371 " address:\taddress of trapfame to display")}, 372 { DDB_ADD_CMD("panic", db_show_panic_cmd, 0, 373 "Displays the last panic string", 374 NULL,NULL) }, 375 #ifdef ARM32_DB_COMMANDS 376 ARM32_DB_COMMANDS, 377 #endif 378 { DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) } 379 }; 380 381 int 382 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 383 { 384 385 if (fault_code == 0) { 386 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 387 kdb_trap(T_BREAKPOINT, frame); 388 else 389 kdb_trap(-1, frame); 390 } else 391 return (1); 392 return (0); 393 } 394 395 extern u_int esym; 396 extern u_int end; 397 398 static struct undefined_handler db_uh; 399 400 void 401 db_machine_init(void) 402 { 403 404 /* 405 * We get called before malloc() is available, so supply a static 406 * struct undefined_handler. 407 */ 408 db_uh.uh_handler = db_trapper; 409 install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &db_uh); 410 } 411 #endif 412 413 u_int 414 db_fetch_reg(int reg, db_regs_t *regs) 415 { 416 417 switch (reg) { 418 case 0: 419 return (regs->tf_r0); 420 case 1: 421 return (regs->tf_r1); 422 case 2: 423 return (regs->tf_r2); 424 case 3: 425 return (regs->tf_r3); 426 case 4: 427 return (regs->tf_r4); 428 case 5: 429 return (regs->tf_r5); 430 case 6: 431 return (regs->tf_r6); 432 case 7: 433 return (regs->tf_r7); 434 case 8: 435 return (regs->tf_r8); 436 case 9: 437 return (regs->tf_r9); 438 case 10: 439 return (regs->tf_r10); 440 case 11: 441 return (regs->tf_r11); 442 case 12: 443 return (regs->tf_r12); 444 case 13: 445 return (regs->tf_svc_sp); 446 case 14: 447 return (regs->tf_svc_lr); 448 case 15: 449 return (regs->tf_pc); 450 default: 451 panic("db_fetch_reg: botch"); 452 } 453 } 454 455 u_int 456 branch_taken(u_int insn, u_int pc, db_regs_t *regs) 457 { 458 u_int addr, nregs; 459 460 switch ((insn >> 24) & 0xf) { 461 case 0xa: /* b ... */ 462 case 0xb: /* bl ... */ 463 addr = ((insn << 2) & 0x03ffffff); 464 if (addr & 0x02000000) 465 addr |= 0xfc000000; 466 return (pc + 8 + addr); 467 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 468 addr = db_fetch_reg(insn & 0xf, regs); 469 addr = pc + 8 + (addr << 2); 470 db_read_bytes(addr, 4, (char *)&addr); 471 return (addr); 472 case 0x5: /* ldr pc, [reg] */ 473 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 474 db_read_bytes(addr, 4, (char *)&addr); 475 return (addr); 476 case 0x1: /* mov pc, reg */ 477 addr = db_fetch_reg(insn & 0xf, regs); 478 return (addr); 479 case 0x8: /* ldmxx reg, {..., pc} */ 480 case 0x9: 481 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 482 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 483 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 484 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 485 nregs = (nregs + (nregs >> 8)) & 0x001f; 486 switch ((insn >> 23) & 0x3) { 487 case 0x0: /* ldmda */ 488 addr = addr - 0; 489 break; 490 case 0x1: /* ldmia */ 491 addr = addr + 0 + ((nregs - 1) << 2); 492 break; 493 case 0x2: /* ldmdb */ 494 addr = addr - 4; 495 break; 496 case 0x3: /* ldmib */ 497 addr = addr + 4 + ((nregs - 1) << 2); 498 break; 499 } 500 db_read_bytes(addr, 4, (char *)&addr); 501 return (addr); 502 default: 503 panic("branch_taken: botch"); 504 } 505 } 506
Indexes created Mon Sep 29 21:09:56 GMT 2025